CN108630669A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN108630669A
CN108630669A CN201710713265.XA CN201710713265A CN108630669A CN 108630669 A CN108630669 A CN 108630669A CN 201710713265 A CN201710713265 A CN 201710713265A CN 108630669 A CN108630669 A CN 108630669A
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CN
China
Prior art keywords
wiring
layer
weld pad
semiconductor device
round
Prior art date
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Granted
Application number
CN201710713265.XA
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CN108630669B (zh
Inventor
岩本正次
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN108630669A publication Critical patent/CN108630669A/zh
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
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    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Abstract

本发明的实施方式提供一种能够在变得无法动作前检测出该预兆的半导体装置。实施方式的半导体装置具备衬底、半导体芯片、第1～第3导体层、检测用配线以及第1、第2焊垫。衬底具有第1、第2主面。半导体芯片配置在第1主面上。第1、第2导体层分别配置在第1、第2主面上。第3导体层配置在所述第1、第2导体层之间。检测用配线配置在所述第1或第3导体层内，不用于所述半导体芯片的动作。第1、第2焊垫配置在所述第2导体层，且连接于所述检测用配线。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2017-56212号(申请日：2017年3月22日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
存储器积层封装是将存储芯片(存储元件)积层并利用模具树脂进行密封而成，且安装在板上而使用。
有在安装并开始使用后，存储器积层封装内的配线被切断而无法驱动的情况。在此情况下，无法读出存储在存储器积层封装的数据，从而数据丢失。
发明内容
本发明的实施方式提供一种能够在变得无法动作前检测出该预兆的半导体装置。
实施方式的半导体装置具备衬底、半导体芯片、第1～第3导体层、检测用配线以及第1、第2焊垫。衬底具有第1、第2主面。半导体芯片配置在第1主面上。第1、第2导体层分别配置在第1、第2主面上。第3导体层配置在所述第1、第2导体层之间。检测用配线配置在所述第1或第3导体层内，不用于所述半导体芯片的动作。第1、第2焊垫配置在所述第2导体层，且连接于所述检测用配线。
附图说明
图1是表示实施方式的半导体装置的剖视图。
图2是表示安装着实施方式的半导体装置的状态的剖视图。
图3是检测衬底产生龟裂的检测用配线W的示意图。
图4是表示变化例的半导体装置的剖视图。
图5是表示安装着变化例的半导体装置的状态的剖视图。
具体实施方式
以下，参照附图，对实施方式详细地进行说明。
(第1实施方式)
如图1所示，半导体装置10具有配线衬底20(绝缘层21、22、配线层23～25、通孔26、抗蚀层27、28)、外部端子31、连接部件33、存储芯片41～48、模具树脂层51。
配线衬底20为具有4条边的大致矩形形状，作为具有第1及第2主面的衬底发挥功能。配线衬底20的上表面、下表面分别对应于第1及第2主面。
配线衬底20具有绝缘层21、22、配线层23～25、通孔26、抗蚀层27、28。
绝缘层21、22例如由玻璃-环氧树脂等绝缘体构成。
配线层23～25(顶层、内层、底层)包含例如使用Cu或Al的多个配线，配置在绝缘层21、22之间及上下。
配线层23对应于配置在第1主面上的第1导体层。配线层25对应于配置在第2主面上的第2导体层。配线层24对应于配置在第1、第2导体层之间的至少一个第3导体层。
此处，使用两个绝缘层21、22，配置3个配线层23～25。也可以使用3个以上的绝缘层，配置4个以上的配线层。在此情况下，作为内层的配线层24有多层。
配线层24具有检测用配线W，配线层25具有信号用焊垫(焊盘)P、检测用焊垫P1、P2。焊垫(焊盘)P、P1、P2连接于外部端子31。
焊垫P1、P2对应于配置在第2导体层且连接于所述配线的第1、第2焊垫。
焊垫P对应于第2导体层中的连接于所述半导体芯片的多个第3焊垫。
通孔26由导电体形成，作为将配线层23～25间连接的层间连接部。
抗蚀层27、28分别配置在配线层23～25的外侧，作为保护配线层23、25的树脂层(例如环氧树脂的层)。
外部端子31是用来将半导体装置10连接于安装衬底60的端子，例如为导电性凸块。外部端子31配置在配线衬底20的下表面，且连接于配线层25的焊垫P。外部端子31配置在第2主面上。
此处，如图1所示，半导体装置10表示BGA(Ball Grid Array，球形阵列)。BGA为焊球，通过熔融、固化，将配线衬底20与安装衬底60之间电性及机械性连接。
连接部件33是用来将配线层23与存储芯片41～48连接的导电性部件，例如是导电性导线。
存储芯片41～48是用来进行数据的写入及读出的例如NAND(Not AND，与非)闪存的半导体芯片。存储芯片41～48分别作为配置在第1主面上的半导体芯片发挥功能。
通过在配线衬底20上积层存储芯片41～48，谋求增大配线衬底20的单位面积的存储器容量。存储芯片41～48的上表面具有用来与外部电连接的端子(未图示)。连接部件33连接于该端子。
模具树脂层51包含树脂材料及无机填充材料，将配线层23、连接部件33、存储芯片41～48密封，从而保护这些部件不受外部影响。
如图2所示，半导体装置10连接于安装衬底(安装板)60而使用。外部端子31(此处为焊球)熔融、固化，成为焊料接合部32，而将半导体装置10的配线层25与安装衬底60的配线层61电性、机械性连接。
视需要在半导体装置10与安装衬底60之间配置底部填充层52，而将焊料接合部32密封保护。底部填充层52由树脂材料(例如为环氧树脂)构成。
以下，对通过检测用配线W检测配线衬底20的龟裂的详细情况进行说明。
图3是从上表面表示在安装衬底60上安装着具有配线衬底20、存储芯片41等的半导体装置10的状态的俯视图。
此处，以实线表示配线层24上的元件(检测用配线W、通孔26)。以虚线表示比配线层24更靠下方的元件(配线层25上的焊垫(焊盘)P、P1、P2)，以单点链线表示比配线层24更靠上方的元件(存储芯片41)。
检测用配线W被区分为往返部位R1～R3、检测用配线W1～W6、通孔26，其两端连接于焊垫P1、P2。检测用配线W对应于具有往返部位且不用于半导体芯片的动作的检测用配线，所述往返部位配置在第1或第3导体层内且将配线回折而往返。
通过检查焊垫P1、P2间的导通(例如测定电阻值)，如下所述，能够检测出半导体装置10变得无法动作的征兆(衬底20产生龟裂)。
依次连接焊垫P1、检测用配线W1、通孔26、检测用配线W2、往返部位R1、检测用配线W3、往返部位R2、检测用配线W4、往返部位R3、检测用配线W5、通孔26、检测用配线W6、焊垫P2。
其中，焊垫P1、P2及检测用配线W1、W6配置在配线层25。往返部位R1～R3、检测用配线W2～W5配置在配线层24。检测用配线W内的通孔26跨及配线层24、25。
检测用配线W配置在除焊垫P1、P2以外的焊垫P的一部分的正上方，但由于配线层不同，因而未电连接。
检测用配线W、焊垫P1、P2并不作为用于存储芯片41～48的动作的信号线使用(未连接于存储芯片41～48)。也就是说，即使检测用配线W断线，也不会对存储芯片41～48的动作产生影响。因此，能够在半导体装置10能够动作的状态下，检测出检测用配线W的断线，并将存储在半导体装置10的数据读出并保存。
检测用配线W如下所述配置在容易断线的部位(配线容易产生裂痕的部位)，并且具有比通常的信号线更容易断线的往返部位R1～R3。结果，检测用配线W先于信号线被切断，从而能够检测出信号线切断的预兆。
此处，对信号线或检测用配线W切断的机制进行说明。
如上所述，当半导体装置10安装在安装衬底60时，半导体装置10与安装衬底60通过焊料接合部32连接。
如果对所安装的半导体装置10施加热应力，则配线衬底20的配线有可能被切断。存储芯片41～48(硅等半导体材料)与安装衬底60(绝缘体材料)的材料不同，热膨胀系数的差大，从而其间产生大应力。特别是在存储芯片41～48的个数多(硅厚)的情况下，应力变大。
存在如下情况：因为该应力，裂痕从配线衬底20的焊料接合部32附近进入到配线衬底20，从而将信号配线切断。如果信号配线被切断，则半导体装置10变得无法动作，必须更换半导体装置。例如，SSD(solid state drive，固态硬盘)通常包含多个半导体装置10(存储器封装)，仅更换变得不良的半导体装置10。
然而，在信号配线被切断后，难以读出存储在半导体装置10的数据。通过使用检测用配线W，能够在信号配线被切断前检测出该预兆并保存数据。
焊垫P1、P2配置在与用于收发信号的信号用焊垫P不同的位置。通常，信号用焊垫P集中在配线衬底20(配线层25)的中央附近。因此，焊垫P1、P2配置在比信号用焊垫P的集合更靠近配线衬底20的外周的位置(靠近存储芯片41的端部处)。
但如果空间允许，也可以将焊垫P1、P2配置在信号用焊垫P之间。
往返部位R1～R3是配线连续往返的部位。该往返的方向优选为将配线衬底20的中央侧与外周侧连结的方向。如下所述，沿着配线衬底20的外周(边缘)、存储芯片41的外周(边缘)施加热应力，而在配线衬底20产生龟裂、甚至断线，因而往返部位R1～R3的配线优选为如相对于配线衬底20或存储芯片41的外周(边缘)交叉(不沿着配线衬底20或存储芯片41的外周)的方向。
此处，往返部位R1～R3的配线的往返方向相对于配线衬底20的边正交，但也可以相对于配线衬底20的边倾斜。
如上所述，往返部位R1～R3配置在配线层24的容易断线的部位。
往返部位R1配置在配线衬底20与存储芯片41的边界、也就是对应于存储芯片41的外周(边缘)的部位，从而跨及该存储芯片41的外周。配线衬底20与存储芯片41的热膨胀系数的差大，对其边界施加大的应力，因此配线衬底20(特别是绝缘层21)容易在该部位产生龟裂。该龟裂会导致配线层23的信号线断线。即，总体来说，往返部位R1是用来事先检测配线层23中的信号线的配线的部位。
此处，往返部位R1覆盖信号用焊垫P的一部分，但也可以不覆盖。
在往返部位R1，检测用配线W对应于存储芯片41的外周的一部分而配置。这样一来，通过使配线沿着应力大的部位往返并延长其长度，检测用配线W的一部分变得容易断线，而能够提高检测灵敏度。
检测用配线W优选为线宽与信号用配线为大致相同以下。
检测用配线W的线宽越小越容易因为应力而断线，从而能够提高检测灵敏度。也就是说，在提高灵敏度方面，优选为减小往返部位R1(往返部位R2、R3也一样)的线宽及检测用配线W的间隔(例如35μm左右以下，优选为30μm左右以下)。此外，在提高灵敏度方面，还优选为延长往返部位R1(往返部位R2、R3也一样)的宽度或长度(将宽度设为例如1mm左右以上、优选为2mm左右以上，将长度设为例如1mm左右以上、优选为2mm左右以上)。
但在配线层24配置着信号用配线的情况下，必须以避开这些配线的方式配置检测用配线W。
往返部位R2配置在对应于配线衬底20的最外周的信号用焊垫Po的部位。焊垫Po对应于多个第3焊垫中最外周的焊垫。
另外，焊垫Pp配置在比焊垫Po更靠配线衬底20的外周的位置，由于焊垫Pp用于供给电力(Vcc)，因而从最外周的信号用焊垫Po中被排除。电力用配线一般比信号用配线粗，不容易被切断，因而也可以从检测对象中被排除。
因为配线衬底20与安装衬底60之间的热膨胀差，导致应力从外部端子31施加到配线衬底20。存在如下倾向：该外部端子31越靠近配线衬底20的外周，此应力变得越大。也就是说，存在如下可能性：在配线衬底20的最外周的靠近外部端子31的配线衬底20(特别是绝缘层22)产生龟裂，从而配线层25内的信号线被切断。即，总体来说，往返部位R2是用来事先检测配线层25中的信号线的配线的部位。
此处，往返部位R2不仅配置在焊垫Pp的正上方，也配置在存储芯片41的外周上，也检测绝缘层21的龟裂(配线层23内的信号线的断线)。
另外，往返部位R2覆盖焊垫Po的外周(边缘)整体，但也可以仅覆盖焊垫Po的外周的一部分、例如外周的外侧部分(外侧边缘)。
往返部位R3配置在存储芯片41的外周(边界)且对应于最外周的焊垫P的部位。该焊垫P对应于多个第3焊垫中最靠近所述半导体芯片的外周的焊垫。
在该部位，配线衬底20从存储芯片41及连接于最外周的焊垫P的外部端子31这两个部位受到大的应力，而在绝缘层21、22(配线层23～25)中的任一层都有断线的可能性。
这样一来，靠近存储芯片41的外周并且配置着焊垫P的部位容易产生断线，具有配置往返部位R的意义。
如上所述，通过配置不与信号线连接的焊垫P1、P2，并利用检测用配线W将其间连接，而能够检测出配线衬底20的裂痕。在容易引起配线裂痕的部位，配置往返部位R1～R3(比信号线更容易被切断)。能够在信号线切断前检测出裂痕，从而能够在变得无法动作前，更换半导体装置10(例如存储器封装)。
此处，在配线层24(内层)配置着检测用配线W，但也可以在配线层23(顶层)或配线层23、24这两层配置检测用配线W。此外，在具有多个配线层24(内层)的情况下，可以配置在其中至少1层。此时，如果在最下层(最靠近配线层25)的配线层24配置检测用配线W(往返部位R1～R3)，则容易检测出配线层25中断线的预兆。
(变化例)
对变化例的半导体装置10进行说明。此处，半导体装置10的外部端子31是LGA(Land Grid Array)，在安装时将半导体装置10与安装衬底60连接的焊料接合部32的高度小。
在BGA的情况下，半导体装置10与安装衬底60间的应力有可能被焊料接合部32缓和，但在变化例中半导体装置10与安装衬底60间的应力难以被缓和，从而容易在配线衬底20产生裂痕(断线)。
此外，如图5所示，在如变化例的LGA的半导体装置10中，由于不具有底部填充层52，因而配线衬底20更容易产生裂痕(断线)。
对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并不想要限定发明的范围。这些新颖的实施方式可以通过其他各种方式实施，可以在不脱离发明的主旨的范围内，进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围中。
[符号的说明]
10 半导体装置
20 配线衬底
21、22 绝缘层
23～25 配线层
26 通孔
27、28 抗蚀层
31 外部端子
32 焊料接合部
33 连接部件
41～48 存储芯片
51 模具树脂层
52 底部填充层
60 安装衬底
61 配线层
W1～W6 配线
R1～R6 往返部位

Claims (5)

1.一种半导体装置，其特征在于具备：
衬底，具有第1、第2主面；
半导体芯片，配置在所述第1主面上；
第1导体层，配置在所述第1主面上；
第2导体层，配置在所述第2主面上；
至少一个第3导体层，配置在所述第1、第2导体层之间；
检测用配线，配置在所述第1或第3导体层内，不用于所述半导体芯片的动作；以及
第1、第2焊垫，配置在所述第2导体层，且连接于所述检测用配线。
2.根据权利要求1所述的半导体装置，其特征在于：
所述检测用配线具有配置在所述第1导体层内且将配线回折而往返的往返部位。
3.根据权利要求2所述的半导体装置，其特征在于：
所述往返部位对应于所述半导体芯片的外周的一部分而配置。
4.根据权利要求2或3所述的半导体装置，其特征在于：
所述第2导体层还具有电连接于所述半导体芯片的多个第3焊垫，并且
所述往返部位对应于所述多个第3焊垫的任一个而配置。
5.根据权利要求2或3所述的半导体装置，其特征在于：
所述往返部位对应于所述多个第3焊垫中设置在所述半导体芯片的外侧的焊垫而配置。
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