TWI704662B - 半導體裝置及半導體封裝 - Google Patents

半導體裝置及半導體封裝 Download PDF

Info

Publication number
TWI704662B
TWI704662B TW106126188A TW106126188A TWI704662B TW I704662 B TWI704662 B TW I704662B TW 106126188 A TW106126188 A TW 106126188A TW 106126188 A TW106126188 A TW 106126188A TW I704662 B TWI704662 B TW I704662B
Authority
TW
Taiwan
Prior art keywords
wiring
reciprocating
semiconductor
plane detection
substrate
Prior art date
Application number
TW106126188A
Other languages
English (en)
Other versions
TW201843790A (zh
Inventor
岩本正次
Original Assignee
日商東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東芝記憶體股份有限公司 filed Critical 日商東芝記憶體股份有限公司
Publication of TW201843790A publication Critical patent/TW201843790A/zh
Application granted granted Critical
Publication of TWI704662B publication Critical patent/TWI704662B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206—Location of test circuitry on chip or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明之實施形態提供一種能夠於無法動作之前檢測出該預兆之半導體裝置。
實施形態之半導體裝置具備基板、半導體晶片、第1~第3導體層、檢測用配線及第1、第2焊墊。基板具有第1、第2主面。半導體晶片配置於第1主面上。第1、第2導體層分別配置於第1、第2主面上。第3導體層配置於上述第1、第2導體層之間。檢測用配線配置於上述第1或第3導體層內，不使用於上述半導體晶片之動作。第1、第2焊墊配置於上述第2導體層，且連接於上述檢測用配線。

Description

半導體裝置及半導體封裝
本發明之實施形態係關於一種半導體裝置。
記憶體積層封裝係將記憶體晶片(記憶體元件)積層並利用塑模樹脂進行密封而成，且安裝於板上而使用。
有於安裝並開始使用後，記憶體積層封裝內之配線被切斷而無法驅動之情況。於此情形時，無法讀出記憶於記憶體積層封裝之資料，從而資料丟失。
本發明之實施形態提供一種能夠於無法動作之前檢測出該預兆之半導體裝置。
實施形態之半導體裝置具備基板、半導體晶片、第1~第3導體層、檢測用配線及第1、第2焊墊。基板具有第1、第2主面。半導體晶片配置於第1主面上。第1、第2導體層分別配置於第1、第2主面上。第3導體層配置於上述第1、第2導體層之間。檢測用配線配置於上述第1或第3導體層內，不使用於上述半導體晶片之動作。第1、第2焊墊配置於上述第2導體層，且連接於上述檢測用配線。
10:半導體裝置
20:配線基板
21:絕緣層
22:絕緣層
23:配線層
24:配線層
25:配線層
26:通孔
27、28:抗蝕層
31:外部端子
32:焊料接合部
33:連接構件
41~48:記憶體晶片
51:塑模樹脂層
52:底部填充層
60:安裝基板
61:配線層
P:焊墊
P1:焊墊
P2:焊墊
Po:焊墊
Pp:焊墊
R1~R6:往返部位
W:配線
W1:配線
W2:配線
W3:配線
W4:配線
W5:配線
W6:配線
圖1係表示實施形態之半導體裝置之剖視圖。
圖2係表示安裝有實施形態之半導體裝置之狀態之剖視圖。
圖3係檢測基板產生龜裂之檢測用配線W之模式圖。
圖4係表示變化例之半導體裝置之剖視圖。
圖5係表示安裝有變化例之半導體裝置之狀態之剖視圖。
以下，參照圖式，對實施形態詳細地進行說明。
(第1實施形態)
如圖1所示，半導體裝置10具有配線基板20(絕緣層21、22、配線層23~25、通孔26、抗蝕層27、28)、外部端子31、連接構件33、記憶體晶片41~48、塑模樹脂層51。
配線基板20為具有4條邊之大致矩形形狀，作為具有第1及第2主面之基板發揮功能。配線基板20之上表面、下表面分別對應於第1及第2主面。
配線基板20具有絕緣層21、22、配線層23~25、通孔26、抗蝕層27、28。
絕緣層21、22例如由玻璃-環氧樹脂等絕緣體構成。
配線層23~25(頂層、內層、底層)包含例如使用Cu或Al之複數條配線，且配置於絕緣層21、22之間及上下。
配線層23對應於配置在第1主面上之第1導體層。配線層25對應於配置在第2主面上之第2導體層。配線層24對應於配置在第1、第2導體層之間之至少一個第3導體層。
此處，使用兩個絕緣層21、22，配置3個配線層23~25。亦可使用3個以上之絕緣層，配置4個以上之配線層。於此情形時，成為內層之配線層24有複數層。
配線層24具有檢測用配線W，配線層25具有信號用焊墊(焊盤)P、檢測用焊墊P1、P2。焊墊(焊盤)P、P1、P2連接於外部端子31。
焊墊P1、P2對應於配置在第2導體層且連接於上述配線之第1、第2焊墊。
焊墊P對應於第2導體層中之連接於上述半導體晶片之複數個第3焊墊。
通孔26由導電體形成，作為連接配線層23~25間之層間連接部。
抗蝕層27、28配置於配線層23~25各者之外側，為保護配線層23、25之樹脂層(例如環氧樹脂之層)。
外部端子31係用以將半導體裝置10連接於安裝基板60之端子，例如為導電性凸塊。外部端子31配置於配線基板20之下表面，且連接於配線層25之焊墊P。外部端子31配置於第2主面上。
此處，如圖1所示，半導體裝置10表示BGA(Ball Grid Array，球形陣列)。BGA為焊球，藉由熔融、固化而將配線基板20與安裝基板60之間電性及機械性連接。
連接構件33係用以將配線層23與記憶體晶片41~48連接之導電性構件，例如為導電性導線。
記憶體晶片41~48係用以進行資料之寫入及讀出之例如NAND(Not AND，反及)快閃記憶體之半導體晶片。記憶體晶片41~48各自作為配置於第1主面上之半導體晶片發揮功能。
藉由於配線基板20上積層記憶體晶片41~48，而謀求增大配線基板20之單位面積之記憶體容量。記憶體晶片41~48之上表面具有用以與外部電性連接之端子(未圖示)。連接構件33連接於該端子。
塑模樹脂層51包含樹脂材料及無機填充材料，將配線層23、連接構件33、記憶體晶片41~48密封，從而保護該等構件不受外部影響。
如圖2所示，半導體裝置10連接於安裝基板(安裝板)60而使用。外部端子31(此處為焊球)熔融、固化，成為焊料接合部32，而將半導體裝置10之配線層25與安裝基板60之配線層61電性、機械性連接。
視需要於半導體裝置10與安裝基板60之間配置底部填充層52，而密封、保護焊料接合部32。底部填充層52由樹脂材料(例如為環氧樹脂)構成。
以下，對藉由檢測用配線W檢測配線基板20之龜裂之詳情進行說明。
圖3係自上表面表示於安裝基板60上安裝有具有配線基板20、記憶體晶片41等之半導體裝置10之狀態之俯視圖。
此處，以實線表示配線層24上之要素(檢測用配線W、通孔26)。以虛線表示較配線層24更靠下方之要素(配線層25上之焊墊(焊盤)P、P1、P2)，以單點鏈線表示較配線層24更靠上方之要素(記憶體晶片41)。
檢測用配線W區分為往返部位R1~R3、檢測用配線W1~W6、通孔26，其兩端連接於焊墊P1、P2。檢測用配線W對應於具有往返部位且不使用於半導體晶片之動作之檢測用配線，該往返部位配置於第1或第3導體層內且將配線回折而往返。
藉由檢查焊墊P1、P2間之導通(例如測定電阻值)，如下所述，可檢測半導體裝置10將要無法動作之徵兆(於基板20產生龜裂)。
依次連接焊墊P1、檢測用配線W1、通孔26、檢測用配線W2、往返部位R1、檢測用配線W3、往返部位R2、檢測用配線W4、往返部位R3、 檢測用配線W5、通孔26、檢測用配線W6、焊墊P2。
其中，焊墊P1、P2及檢測用配線W1、W6配置於配線層25。往返部位R1~R3、檢測用配線W2~W5配置於配線層24。檢測用配線W內之通孔26跨及配線層24、25。
檢測用配線W配置於除焊墊P1、P2以外的焊墊P之一部分之正上方，但由於配線層不同，故而未被電性連接。
檢測用配線W、焊墊P1、P2不作為用於記憶體晶片41~48之動作之信號線使用(未連接於記憶體晶片41~48)。即，即使檢測用配線W斷線，亦不會對記憶體晶片41~48之動作產生影響。因此，可於半導體裝置10能夠動作之狀態下，檢測檢測用配線W之斷線，將記憶於半導體裝置10之資料讀出並保存。
檢測用配線W如下所述配置於容易斷線之部位(配線容易產生裂痕之部位)，並且具有較通常之信號線更容易斷線之往返部位R1~R3。其結果，檢測用配線W比信號線先切斷，而可檢測出信號線切斷之預兆。
此處，對信號線或檢測用配線W切斷之機制進行說明。
如上所述，半導體裝置10被安裝於安裝基板60時，半導體裝置10與安裝基板60係以焊料接合部32而連接。
若對所安裝之半導體裝置10施加熱應力，則配線基板20之配線有可能被切斷。記憶體晶片41~48(矽等半導體材料)與安裝基板60(絕緣體材料)之材料不同，熱膨脹係數之差較大，於其間會產生較大之應力。尤其是，於記憶體晶片41~48之個數較多(矽較厚)之情形時，應力變大。
因該應力，可能使得裂痕自配線基板20之焊料接合部32附近進入配線基板20，從而將信號配線切斷。若信號配線被切斷，則半導體裝置10 無法動作，必須予以更換。例如，SSD(solid state drive，固體狀態驅動機)通常包含複數個半導體裝置10(記憶體封裝)，僅需更換不良之半導體裝置10。
然而，於信號配線被切斷後，難以讀出記憶於半導體裝置10之資料。藉由使用檢測用配線W，可於信號配線被切斷之前檢測出該預兆並保存資料。
焊墊P1、P2配置於與用於收發信號之信號用焊墊P不同之位置。通常，信號用焊墊P集中在配線基板20(配線層25)之中央附近。因此，焊墊P1、P2配置於較信號用焊墊P之集合更靠近配線基板20之外周之位置(靠近記憶體晶片41之端處)。
惟若空間允許，亦可將焊墊P1、P2配置於信號用焊墊P之間。
往返部位R1~R3係配線連續往返之部位。該往返之方向較佳為將配線基板20之中央側與外周側連結之方向。如下所述，沿著配線基板20之外周(邊緣)、記憶體晶片41之外周(邊緣)施加熱應力，而於配線基板20產生龜裂、甚至斷線，故而往返部位R1~R3之配線較佳為如相對於配線基板20或記憶體晶片41之外周(邊緣)交叉(不沿著配線基板20或記憶體晶片41之外周)之方向。
此處，往返部位R1~R3之配線之往返方向相對於配線基板20之邊正交，但亦可相對於配線基板20之邊傾斜。
如上所述，往返部位R1~R3配置於配線層24之容易斷線之部位。
往返部位R1配置於配線基板20與記憶體晶片41之邊界、即對應於記憶體晶片41之外周(邊緣)之部位，跨及該外周。配線基板20與記憶體晶片41之熱膨脹係數之差較大，對其邊界施加較大之應力，因此配線基板 20(尤其是絕緣層21)容易於該部位產生龜裂。該龜裂會導致配線層23之信號線斷線。即，總體而言，往返部位R1係用以事先檢測配線層23中之信號線之配線的部位。
此處，往返部位R1覆蓋信號用焊墊P之一部分，但亦可不覆蓋。
於往返部位R1，檢測用配線W對應於記憶體晶片41之外周之一部分而配置。如此，藉由使配線沿著應力較大之部位往返並延長其長度，檢測用配線W之一部分變得容易斷線，而可提高檢測感度。
檢測用配線W較佳為線寬與信號用配線為大致相同以下。
檢測用配線W之線寬越小越容易因應力而斷線，從而可提高檢測感度。即，於提高感度方面，較佳為減小往返部位R1(往返部位R2、R3亦相同)之線寬及檢測用配線W之間隔(例如35μm左右以下，較佳為30μm左右以下)。又，於提高感度方面，亦較佳為延長往返部位R1(往返部位R2、R3亦相同)之寬度或長度(將寬度設為例如1mm左右以上、較佳為2mm左右以上，將長度設為例如1mm左右以上、較佳為2mm左右以上)。
但是，於在配線層24配置有信號用配線之情形時，必須以避開該等配線之方式配置檢測用配線W。
往返部位R2配置於對應於配線基板20之最外周之信號用焊墊Po之部位。焊墊Po對應於複數個第3焊墊中最外周之焊墊。
再者，焊墊Pp配置於較焊墊Po更靠配線基板20之外周之位置，由於該焊墊Pp用於供給電力(Vcc)，故而自最外周之信號用焊墊Po中被排除。電力用配線一般較信號用配線粗，不容易被切斷，故而亦可自檢測對象中被排除。
因配線基板20與安裝基板60之間之熱膨脹差，導致應力自外部端子 31施加至配線基板20。存在如下傾向：該外部端子31越靠近配線基板20之外周，此應力變得越大。即，存在如下可能性：於配線基板20之最外周之靠近外部端子31之配線基板20(尤其是絕緣層22)產生龜裂，從而配線層25內之信號線被切斷。即，總體而言，往返部位R2係用以事先檢測配線層25中之信號線之配線的部位。
此處，往返部位R2不僅配置於焊墊Pp之正上方，亦配置於記憶體晶片41之外周上，亦檢測絕緣層21之龜裂(配線層23內之信號線之斷線)。
再者，往返部位R2覆蓋焊墊Po之外周(邊緣)整體，但亦可僅覆蓋焊墊Po之外周之一部分、例如外周之外側部分(外側邊緣)。
往返部位R3配置於記憶體晶片41之外周(邊界)且對應於最外周之焊墊P之部位。該焊墊P對應於複數個第3焊墊中最靠近上述半導體晶片之外周之焊墊。
於該部位，配線基板20自記憶體晶片41及連接於最外周之焊墊P之外部端子31之兩者受到較大之應力，而於絕緣層21、22(配線層23~25)之任一者均有斷線之可能性。
如此，接近記憶體晶片41之外周並且配置有焊墊P之部位容易產生斷線，具有配置往返部位R之意義。
如上所述，藉由配置不與信號線連接之焊墊P1、P2，並利用檢測用配線W將其間連接，而可檢測出配線基板20之裂痕。於容易引起配線裂痕之部位，配置往返部位R1~R3(較信號線更容易被切斷)。可於信號線切斷之前檢測出裂痕，從而可於無法動作之前，更換半導體裝置10(例如記憶體封裝)。
此處，於配線層24(內層)配置有檢測用配線W，但亦可於配線層 23(頂層)或配線層23、24之兩者配置檢測用配線W。又，於具有複數個配線層24(內層)之情形時，可配置於其中至少1層。此時，若於最下層(最靠近配線層25)之配線層24配置檢測用配線W(往返部位R1~R3)，則容易檢測出配線層25中斷線之預兆。
(變化例)
對變化例之半導體裝置10進行說明。此處，半導體裝置10之外部端子31為LGA(Land Grid Array，平台柵格陣列)，於安裝時將半導體裝置10與安裝基板60連接之焊料接合部32之高度較小。
於BGA之情形時，半導體裝置10與安裝基板60間之應力有可能被焊料接合部32緩和，但於變化例中半導體裝置10與安裝基板60間之應力難以被緩和，從而容易於配線基板20產生裂痕(斷線)。
又，如圖5所示，於如變化例之LGA之半導體裝置10中，由於不具有底部填充層52，故而配線基板20更容易產生裂痕(斷線)。
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出，並不意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態加以實施，可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍中。
[相關申請案]
本申請案享有以日本專利申請案2017-56212號(申請日：2017年3月22日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
20:配線基板
24:配線層
26:通孔
41:記憶體晶片
60:安裝基板
P:焊墊
P1:焊墊
P2:焊墊
Po:焊墊
Pp:焊墊
R1:往返部位
R2:往返部位
R3:往返部位
W:配線
W1:配線
W2:配線
W3:配線
W4:配線
W5:配線
W6:配線

Claims (18)

  1. 一種半導體裝置，其具備：基板，其具有：絕緣層、第1導體層、第2導體層、第3導體層及通孔，上述第1導體層係於上述絕緣層之第1面上，上述第2導體層係於上述絕緣層之相對於上述第1面之第2面上，上述第3導體層係於上述絕緣層中於上述基板之平面方向(plane direction)沿著上述第1及第2面延伸，上述通孔係於上述絕緣層中延伸於上述基板之厚度方向；及半導體晶片，其配置於上述第1面之上的上述基板之第1主面上；其中，上述基板更包含：平面檢測用配線(planar detection interconnection)，其作為上述第1導體層或上述第3導體層之任一者的一部分而設置，其中上述平面檢測用配線不是於上述半導體晶片之動作期間所使用之信號配線之一部分，且不與上述半導體晶片之任何電路電性連接，且上述平面檢測用配線之寬度小於上述信號配線之寬度；及第1、第2焊墊，其等連接至球形陣列(Ball Grid Array，BGA)或平台柵格陣列(Land Grid Array，LGA)之一部分，上述第1、第2焊墊作為上述第2導體層之一部分而設置，且經由上述通孔而電性連接於上述平面檢測用配線。
  2. 如請求項1之半導體裝置，其中上述平面檢測用配線具有往返部位(serpentine region)，其中上述平面檢測用配線係：於上述往返部位中以鋸齒形方式(zigzag manner)回折而 往返(folded back and forth)。
  3. 如請求項2之半導體裝置，其中上述往返部位對應於上述半導體晶片之外周之一部分而配置。
  4. 如請求項2或3之半導體裝置，其中上述第2導體層進而具有電性連接於上述半導體晶片之複數個第3焊墊，且上述往返部位對應於上述複數個第3焊墊之任一者而配置。
  5. 如請求項4之半導體裝置，其中上述往返部位對應於上述複數個第3焊墊中設置於上述半導體晶片之外側之一者而配置。
  6. 如請求項5之半導體裝置，其中上述平面檢測用配線係：於上述往返部位中具有複數個直線部分(linear portion)，且上述直線部分垂直於上述半導體晶片之上述外側地延伸。
  7. 如請求項1之半導體裝置，其中上述平面檢測用配線具有第1及第2往返部位，上述平面檢測用配線係：於上述第1及第2往返部位之各者中以鋸齒形方式回折而往返。
  8. 如請求項7之半導體裝置，其中上述平面檢測用配線係：於上述第1往返部位中，具有延伸於第1方向之複數個第1直線部分；且上述平面檢測用配線係：於上述第2往返部位中，具有延伸於與上述第1方向交叉的第2方向之複數個第2直線部分。
  9. 如請求項8之半導體裝置，其中上述第1及第2方向互相垂直。
  10. 一種半導體封裝(semiconductor package)，其具備：基板，其具有：絕緣層、第1導體層、第2導體層、第3導體層及通孔，上述第1導體層係於上述絕緣層之第1面上，上述第2導體層係於上述絕緣層之相對於上述第1面之第2面上，上述第3導體層係於上述絕緣層中於上述基板之平面方向沿著上述第1及第2面延伸，上述通孔係於上述絕緣層中延伸於上述基板之厚度方向；及複數個半導體晶片，其等堆疊於上述第1面之上的上述基板之第1主面上；複數個外部端子，其等配置於上述基板之相對於上述第1主面之第2主面上，上述複數個外部端子係球形陣列或平台柵格陣列；其中，上述基板更包含：信號配線，其作為上述第1導體層之一部分而設置，且電性連接至上述半導體晶片；平面檢測用配線，其作為上述第1導體層或第3導體層之任一者的一部分而設置，其中上述平面檢測用配線不與任一個上述信號配線電性連 接，且上述平面檢測用配線之寬度小於上述信號配線之寬度；及第1、第2焊墊，其等連接至上述外部端子之一部分，上述第1、第2焊墊作為上述第2導體層之一部分而設置，且經由上述通孔而電性連接於上述平面檢測用配線。
  11. 如請求項10之半導體封裝，其中上述平面檢測用配線具有往返部位，其中上述平面檢測用配線係：於上述往返部位中以鋸齒形方式回折而往返。
  12. 如請求項11之半導體封裝，其中上述往返部位對應於上述複數個半導體晶片之一者之外周之一部分而配置。
  13. 如請求項11之半導體封裝，其中上述第2導體層進而具有與上述複數個半導體晶片之一者電性連接之複數個第3焊墊，且上述往返部位對應於上述複數個第3焊墊之一者而配置。
  14. 如請求項13之半導體封裝，其中上述往返部位係對應於上述複數個第3焊墊之設置於上述複數個半導體晶片之上述一者之外側的一者而配置。
  15. 如請求項14之半導體封裝，其中 上述平面檢測用配線係：於上述往返部位中具有複數個直線部分，且上述直線部分垂直於上述複數個半導體晶片之上述一者之上述外側地延伸。
  16. 如請求項10之半導體封裝，其中上述平面檢測用配線具有第1及第2往返部位，上述平面檢測用配線係：於上述第1及第2往返部位之各者中以鋸齒形方式回折而往返。
  17. 如請求項16之半導體封裝，其中上述平面檢測用配線係：於上述第1往返部位中，具有延伸於第1方向之複數個第1直線部分；且上述平面檢測用配線係：於上述第2往返部位中，具有延伸於與上述第1方向交叉的第2方向之複數個第2直線部分。
  18. 如請求項17之半導體封裝，其中上述第1及第2方向互相垂直。
TW106126188A 2017-03-22 2017-08-03 半導體裝置及半導體封裝 TWI704662B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP??2017-056212 2017-03-22
JP2017056212A JP2018160521A (ja) 2017-03-22 2017-03-22 半導体装置

Publications (2)

Publication Number Publication Date
TW201843790A TW201843790A (zh) 2018-12-16
TWI704662B true TWI704662B (zh) 2020-09-11

Family

ID=63583629

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106126188A TWI704662B (zh) 2017-03-22 2017-08-03 半導體裝置及半導體封裝

Country Status (4)

Country Link
US (1) US10483236B2 (zh)
JP (1) JP2018160521A (zh)
CN (1) CN108630669B (zh)
TW (1) TWI704662B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210041078A (ko) 2018-10-11 2021-04-14 양쯔 메모리 테크놀로지스 씨오., 엘티디. 수직 메모리 장치
WO2020087253A1 (en) * 2018-10-30 2020-05-07 Yangtze Memory Technologies Co., Ltd. Ic package
KR20210000530A (ko) 2019-06-25 2021-01-05 삼성전자주식회사 칩 적층 반도체 패키지 및 그 제조 방법
US11195799B2 (en) 2020-03-31 2021-12-07 International Business Machines Corporation Hybrid readout package for quantum multichip bonding
KR20220097725A (ko) 2020-12-31 2022-07-08 삼성전자주식회사 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466562B2 (en) * 2011-12-22 2016-10-11 Ps4 Luxco S.A.R.L. Semiconductor chip having plural penetration electrode penetrating therethrough
US20170040306A1 (en) * 2015-06-30 2017-02-09 Apple Inc. Electronic Devices With Soft Input-Output Components

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091562B2 (en) * 2004-08-13 2006-08-15 Himax Technologies, Inc. CMOS power sensor
US7250311B2 (en) * 2005-02-23 2007-07-31 International Business Machines Corporation Wirebond crack sensor for low-k die
JP2007071753A (ja) * 2005-09-08 2007-03-22 Jsr Corp 電気抵抗測定用コネクター並びに回路基板の電気抵抗測定装置および測定方法
JP2008021915A (ja) * 2006-07-14 2008-01-31 Mitsubishi Electric Corp 電子部品装置及びその製造方法
TW201003880A (en) * 2008-05-30 2010-01-16 Advanced Micro Devices Inc Semiconductor device comprising a chip internal electrical test structure allowing electrical measurements during the fabrication process
CN101752345B (zh) * 2008-12-17 2012-02-15 上海华虹Nec电子有限公司 半导体器件p2id和sm的测试结构
JP5262945B2 (ja) 2009-04-15 2013-08-14 株式会社デンソー 電子装置
JP2010278212A (ja) * 2009-05-28 2010-12-09 Hitachi Ltd 電子部品用パッケージ、および電子部品用パッケージの異常検出方法
US20110221460A1 (en) * 2010-03-10 2011-09-15 Heinrich Trebo Integrated Circuit Arrangement Having a Defect Sensor
US8618827B2 (en) * 2010-10-13 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device
JP2012151272A (ja) * 2011-01-19 2012-08-09 Renesas Electronics Corp 半導体チップ及び半導体装置
JP2013080750A (ja) 2011-09-30 2013-05-02 Toshiba Corp 半導体パッケージおよびそれを用いた半導体ディスク装置
US9222961B1 (en) * 2014-07-29 2015-12-29 Chung Hua University Vertical probe card and method for manufacturing the same
KR20170051085A (ko) * 2015-11-02 2017-05-11 삼성전자주식회사 3차원 크랙 검출 구조물을 포함하는 반도체 장치 및 크랙 검출 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466562B2 (en) * 2011-12-22 2016-10-11 Ps4 Luxco S.A.R.L. Semiconductor chip having plural penetration electrode penetrating therethrough
US20170040306A1 (en) * 2015-06-30 2017-02-09 Apple Inc. Electronic Devices With Soft Input-Output Components

Also Published As

Publication number Publication date
US20180277514A1 (en) 2018-09-27
CN108630669A (zh) 2018-10-09
JP2018160521A (ja) 2018-10-11
CN108630669B (zh) 2021-11-30
TW201843790A (zh) 2018-12-16
US10483236B2 (en) 2019-11-19

Similar Documents

Publication Publication Date Title
TWI704662B (zh) 半導體裝置及半導體封裝
JP4473807B2 (ja) 積層半導体装置及び積層半導体装置の下層モジュール
KR100683027B1 (ko) 반도체장치 및 그 제조방법
US8525349B2 (en) Semiconductor device packages stacked together having a redistribution layer
KR100690922B1 (ko) 반도체 소자 패키지
US11171128B2 (en) Semiconductor package
US11291146B2 (en) Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same
US6798071B2 (en) Semiconductor integrated circuit device
US8796847B2 (en) Package substrate having main dummy pattern located in path of stress
US10361177B2 (en) Semiconductor package having a molding layer including a molding cavity and method of fabricating the same
KR20070088688A (ko) 반도체 장치 및 그 장착 구조물
KR20130075251A (ko) 복수의 세그먼트로 구성된 인터포저를 포함하는 반도체 패키지
JP2011155203A (ja) 半導体装置
KR20190125887A (ko) 반도체 다이와 이격된 브리지 다이를 포함하는 반도체 패키지
KR101096330B1 (ko) 반도체 장치용 패키지
KR101227078B1 (ko) 반도체 패키지 및 그 형성방법
US20130277835A1 (en) Semiconductor device
US7180185B2 (en) Semiconductor device with connections for bump electrodes
KR20070095502A (ko) 볼 그리드 어레이 유형의 적층 패키지
TWI613771B (zh) 半導體封裝
JP2004128290A (ja) 半導体装置
US11557540B2 (en) Semiconductor device
TWI728438B (zh) 半導體裝置
US20220148955A1 (en) Semiconductor package
JP4523425B2 (ja) 半導体素子搭載用基板