TW202017134A - 積體電路封裝以及用於製造積體電路封裝的方法 - Google Patents

積體電路封裝以及用於製造積體電路封裝的方法 Download PDF

Info

Publication number
TW202017134A
TW202017134A TW107143793A TW107143793A TW202017134A TW 202017134 A TW202017134 A TW 202017134A TW 107143793 A TW107143793 A TW 107143793A TW 107143793 A TW107143793 A TW 107143793A TW 202017134 A TW202017134 A TW 202017134A
Authority
TW
Taiwan
Prior art keywords
package
marking
main surface
plastic structure
chips
Prior art date
Application number
TW107143793A
Other languages
English (en)
Other versions
TWI754785B (zh
Inventor
周厚德
陳鵬
Original Assignee
大陸商長江存儲科技有限責任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 大陸商長江存儲科技有限責任公司 filed Critical 大陸商長江存儲科技有限責任公司
Publication of TW202017134A publication Critical patent/TW202017134A/zh
Application granted granted Critical
Publication of TWI754785B publication Critical patent/TWI754785B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92165—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laser Beam Processing (AREA)

Abstract

本公開的各個方面提供了一種積體電路（IC）封裝。所述IC封裝包括封裝基底、一個或複數個IC晶片、標記板和塑膠結構。所述一個或複數個IC晶片與所述封裝基底互連。所述標記板具有第一主表面和第二主表面。將所述標記板疊置在所述一個或複數個IC晶片上使得所述第一主表面面向所述一個或複數個IC晶片。所述塑膠結構被配置為包封所述一個或複數個IC晶片和所述標記板，其中所述標記板的第二主表面是所述IC封裝的外表面的部分。

Description

積體電路封裝以及用於製造積體電路封裝的方法
本公開係關於半導體器件以及其製造方法。
在半導體製造當中，積體電路（IC）封裝是在半導體器件製造中將積體電路的一個或複數個半導體晶粒（又稱為IC晶片）包封到用於防止物理損傷、腐蝕等的支撐殼體當中的步驟。具有經包封的半導體晶粒的支撐殼體被稱為IC封裝。可以對IC封裝進行雷射標記，以便於識別和溯源。
本公開的各個方面提供了一種積體電路（IC）封裝。所述IC封裝包括封裝基底、一個或複數個IC晶片、標記板以及塑膠結構。所述一個或複數個IC晶片與所述封裝基底互連。所述標記板具有第一主表面和第二主表面。所述標記板疊置在所述一個或複數個IC晶片上，其中所述第一主表面面向所述一個或複數個IC晶片。所述塑膠結構被配置為包封所述一個或複數個IC晶片和所述標記板，其中所述標記板的第二主表面是所述IC封裝的外表面的部分。
在一些示例中，所述標記板由半導體材料、陶瓷材料、金屬材料和金屬合金材料中的至少其中之一形成。在示例中，所述標記板被配置為具有階梯結構，並且所述第一主表面具有不同於（例如，小於）所述第二主表面的表面積。在另一示例中，所述標記板被配置為具有長方體形狀，其中所述第一主表面和所述第二主表面具有相同的表面積。
在實施例中，所述IC封裝包括被配置為對所述一個或複數個IC晶片與所述封裝基底進行互連的多條接合線。所述塑膠結構被配置為包封所述多條接合線。
應注意，所述IC封裝是球柵陣列（BGA）封裝、四邊扁平封裝（QFP）、四邊扁平無引線（QFN）封裝、平面網格陣列陣列（LGA）封裝和引腳柵格陣列（PGA）之一。
在一些實施例中，使相鄰IC晶片錯開，並且所述IC封裝中的複數個IC晶片是按照之字形圖案疊置的。
根據本公開的一個方面，所述標記板具有比所述塑膠結構更好的抗雷射穿透特性。例如，所述標記板中的雷射穿透深度短於所述塑膠結構中的雷射穿透深度。在一些示例中，所述標記板具有比所述塑膠結構更高的剛度。根據本公開的另一方面，所述標記板具有與所述一個或複數個IC晶片基本相等的熱膨脹係數（CTE）。根據本公開的另一方面，所述標記板具有比所述塑膠結構更好的熱導率。因此，所述標記板能夠將IC晶片在操作過程中生成的熱傳導至IC封裝的外表面。
本公開的各個方面提供了一種用於製造積體電路（IC）封裝的方法。所述方法包括在封裝基底上疊置一個或複數個IC晶片；在所述一個或複數個IC晶片上疊置具有面向所述一個或複數個IC晶片的第一主表面的標記板；以及形成包封所述一個或複數個IC晶片以及所述標記板的塑膠結構，其中所述標記板的第二主表面是所述IC封裝的外表面的部分。
在示例中，所述方法包括將所述標記板和所述一個或複數個IC晶片包封到所述塑膠結構中，並且對所述塑膠結構進行研磨，以暴露所述標記板的第二主表面。此外，所述方法還包括在所述標記板的第二主表面上進行雷射標記。
下文的公開內容提供了用於實施所提供的主題的不同特徵的很多不同實施例或示例。下文描述了部件和佈置的具體示例以簡化本公開。當然，這些只是示例，並非意在構成限制。例如，下文的描述當中出現的在第二特徵上或之上形成第一特徵可以包括將所述第一特徵和第二特徵形成為直接接觸的實施例，還可以包括可以在所述第一特徵和第二特徵之間形成額外的特徵從而使得所述第一特徵和第二特徵可能不直接接觸的實施例。此外，本公開可以在各個示例中重複使用作為附圖標記的數位或/及字母。這種重複的目的是為了簡化和清楚的目的，其本身並不指示所討論的各種實施例或/及配置之間的關係。
此外，文中為了便於說明可以採用空間相對術語，例如，“下面”、“之下”、“下方”、“之上”、“上方”等，以描述一個元件或特徵與其他元件或特徵的如圖所示的關係。空間相對術語意在包含除了附圖所示的取向之外的處於使用或操作中的裝置的不同取向。所述設備可以具有其他取向（旋轉90度或者處於其他取向上），並可以照樣相應地解釋文中採用的空間相對描述詞。
本公開的各個方面提供了一種具有嵌入到塑膠結構當中的標記板的積體電路（IC）封裝。所述標記板具有比所述塑膠結構的模制材料更高的剛度，並且具有比模制材料更好的抗雷射穿透特性。因為更高的剛度的原因，能夠降低由於高溫處理（例如，焊接過程）導致的IC封裝變形。此外，由於更好的抗雷射穿透特性，允許標記板相對更薄。因而，所述IC封裝可以具有相對更小的厚度或者能夠包封更多的IC晶片而不增大封裝厚度。
第1圖示出了根據一些實施例的積體電路（IC）封裝100的截面圖。IC封裝100包括封裝基底110、複數個IC晶片120（例如，包括第1圖示例中的IC晶片120A-120H）和標記板150。IC晶片120疊置在封裝基底110上並且被包封到塑膠結構140內。標記板150疊置在IC晶片120上並且嵌入到塑膠結構140內。標記板150的表面155是IC封裝100的外表面的部分，並且可以用雷射對表面155進行標記，以便於識別和溯源。
封裝基底110是由（例如）適當的絕緣材料（又稱為介電材料）構成的，例如，基於環氧樹脂的層壓基底、基於樹脂的雙馬來醯亞胺三嗪（BT）基底等。封裝基底110相對呈剛性，從而為IC晶片120提供機械支撐。封裝基底110具有第一表面111和第二表面112。IC晶片120設置在表面上，例如，設置在封裝基底110的第二表面112上。
封裝基底110還為IC晶片120提供電氣支撐。在一些示例中，封裝基底110包括多層金屬走線（例如，銅線等），其中絕緣材料位於金屬走線其間。不同層上的金屬走線可以通過通孔連接。此外，接觸結構既形成於第一表面111上又形成於第二表面112上，從而將IC封裝100中的IC晶片120電性連接至IC封裝100外的部件。
IC晶片120可以是任何適當的晶片。IC晶片120包括用於提供儲存功能、計算功能或/及處理功能的各種電路。
封裝基底110提供從IC晶片120的輸入/輸出到形成於IC封裝100的第一表面111和第二表面112上的接觸結構的互連。在示例中，IC晶片120包括電性連接至形成於IC晶片120上的內部電路的輸入/輸出（I/O）焊盤（未示出）。接合用以連接IC晶片120上的I/O焊盤以及封裝基底110的第二表面112上的接觸結構的接合線130（例如，鋁線、銅線、銀線、金線等），從而在IC晶片120和封裝基底110之間形成電性連接。在第1圖的示例中，使IC晶片120中的相鄰IC晶片錯開佈置，以提供允許將接合線130接合到I/O焊盤上並且避免短路的接合空間。此外，各IC晶片120是按照之字形圖案疊置的，從而為接合線130提供空間。
封裝基底110還包括位於第一表面111上的適當的接觸結構160。在第1圖的示例中，IC封裝100是球柵陣列（BGA）封裝，並且接觸結構160中的每一個包括焊盤以及設置在焊盤上的焊球。注意，在一些示例中，不在封裝基底110上形成焊球。在示例中，IC封裝是四邊扁平（QFP）封裝。在另一示例中，IC封裝100是四邊扁平無引線（QFN）封裝。在另一個示例中，IC封裝100是平面網格陣列陣列（LGA）封裝，並且接觸結構中的每一個包括焊盤。在另一個示例中，IC封裝100是引腳柵格陣列（PGA）封裝，並且接觸結構中的每一個包括引腳。
在第1圖的示例中，封裝基底110、塑膠結構140和標記板150形成了IC封裝100的將IC晶片120包封在內的外側部分。具體而言，標記板150疊置在IC晶片120上。之後，通過塑膠結構140包封封裝基底110的第二表面112、IC晶片120和接合線130。標記板150被嵌入到塑膠結構140內，其表面155露出以便於用雷射做標記。
塑膠結構140由任何適當材料形成，例如，矽氧化物填充物和樹脂等。在示例中，塑膠結構140包括環氧樹脂模制化合物（EMC）。塑膠結構140和IC晶片120具有不同的熱膨脹係數（CTE）（又稱為CTE失配）並且具有不同熱導率。
根據本公開的一個方面，標記板150由剛度高於塑膠結構140的材料形成。在第1圖的示例中，IC封裝100從上表面（例如，標記板150的表面155）到底表面（例如，封裝基底110的第一表面111）包括標記板150、IC晶片120和封裝基底110。與塑膠結構140相比，標記板150、IC晶片和封裝基底110具有相對較高的剛度。在常規示例中，相關IC封裝的上部也由EMC構成，並且用於進行雷射標記。與常規示例相比，IC封裝100具有更低的體積百分比的EMC，因而與常規示例相比具有更高的封裝剛度。
根據本公開的另一方面，標記板150具有與IC晶片120大致相同的CTE（即，匹配的CTE）。因而，IC封裝100在熱處理期間具有降低的翹曲。例如，CTE失配可能在模制之後的熱處理期間引起封裝翹曲。例如，可以使用表面安裝製程將所述IC封裝安裝到印刷電路板（PCB）上。所述表面安裝製程包括焊料回流步驟，其使得處理溫度升高到（例如）200ºC以上。在處理溫度返回到示例性的室溫時，由於從上表面到底表面的匹配CTE的原因，IC封裝100與常規示例相比具有降低的翹曲。
此外，根據本公開的一個方面，標記板150具有比塑膠結構140更好的抗雷射穿透特性，以防止雷射穿透。例如，標記板150中的雷射穿透深度短於塑膠結構140中的雷射穿透深度。因而，IC封裝100具有降低的厚度，或者可以包括更多的IC晶片120。例如，在常規示例中，由於是在EMC上進行雷射標記，為了防止對IC晶片120上的電路或者對接合線130造成雷射損傷，因而所述塑膠結構的處於IC晶片之上的頂部必須相對較厚，例如，約為150µm。標記板150具有比塑膠結構140更好的抗雷射穿透特性，並且30µm的厚度就足以防止對IC晶片120上的電路和接合線130造成雷射損傷。
根據本公開的另一方面，標記板150具有比塑膠結構140更好的熱導率。例如，與塑膠結構140相比，標記板150可以更快地將IC晶片在操作過程中生成的熱傳導至IC封裝100的外表面。快速的熱傳遞能夠為IC晶片120提供合適的熱環境，降低操作期間的晶片溫度，並且允許IC晶片120在操作器件正確工作。
在實施例中，標記板150是由矽（例如，純矽）形成的，因而在示例中被稱為鏡面晶粒（由於光亮的表面155的原因）。因而，標記板150具有與IC晶片120大致相同的CTE（例如，匹配CTE），並且與塑膠結構140相比具有更高的剛度和更優的抗雷射穿透特性。
應注意，其他適當的材料，例如，陶瓷、金屬、金屬合金也可以用於形成標記板150。在示例中，標記板150由陶瓷材料形成。在另一示例中，標記板150由金屬合金形成。對標記板150進行適當處理，從而使標記板150的面對IC晶片120的底表面是不導電的，從而避免與接合線130短路。
在第1圖的示例中，標記板150被配置為在截面圖當中具有階梯形狀。因而，標記板150的面對IC晶片120H的表面157小於標記板150的表面155。較小的表面157在IC晶片120H上提供了更多的用於引線接合的空間。較大的表面155允許有更多的面積進行雷射標記。
應注意，儘管在第1圖的示例中IC晶片120被示為具有相同的晶片尺寸，但是在其他示例中，IC晶片120可以具有不同的晶片尺寸。
還要注意，在疊置IC晶片120和標記板150時，可以在IC晶片120和標記板150之間採用中間層170（例如，黏合膜、聚合物膜和間隔體膜等）。
第2圖示出了根據一些實施例的另一IC封裝200的截面圖。與IC封裝100類似，IC封裝200包括封裝基底210、複數個IC晶片220（例如，包括第2圖示例中的IC晶片220A-220H）和標記板250。IC晶片220疊置在封裝基底210上並且被包封到塑膠結構240中。標記板250疊置在IC晶片220上並且嵌入到塑膠結構240內。標記板250的表面255是IC封裝200的外表面的部分，並且可以對表面255進行雷射標記，以用於識別和溯源。
IC封裝200採用某些與IC封裝100中採用的等同、等價或類似的部件。例如，IC晶片220與IC晶片120等價或類似。接合線230與接合線130等價或類似。塑膠結構240與塑膠結構140等價或類似。封裝基底210與封裝基底110等價或類似。上文已經提供了對這些部件的描述，這裡為了清楚起見將省略這樣的描述。
在第2圖的示例中，標記板250被配置為具有長方體形狀，並且從截面圖來看具有矩形形狀，因而面對IC晶片220H的表面257與作為IC封裝200的外表面的部分的表面255具有相同的表面積。
此外，在第2圖的示例中，IC封裝200可以是沒有焊球的LGA封裝。封裝基底210包括第一表面211上的平接觸結構。
第3圖示出了概況根據本公開的一些實施例的製造過程300的流程圖。在示例中，製造過程300用於製造IC封裝，例如，IC封裝100、IC封裝200等。
第4圖至第6圖示出了根據一些實施例處於製造過程300的各個中間階段的IC封裝100的各個截面圖。應注意，對於其他IC封裝（例如，IC封裝200）而言，可以對第4圖至第6圖做出適當修改。
參考第3圖和第4圖，所述過程開始於操作S301，並且進行至操作S310。
在操作S310中，將IC晶片疊置到封裝基底上。如第4圖所示，複數個IC晶片120被疊置到封裝基底110上。IC晶片120是按照錯開的方式疊置的，從而為引線接合提供更多的空間。例如，使IC晶片120中的相鄰IC晶片錯開，從而為引線接合提供空間。各IC晶片120可以是按照之字形圖案疊置的。使用接合線130進行接合，從而使IC晶片120與封裝基底110互連。在第4圖的示例中，在相鄰的IC晶片120之間使用中間層170（例如黏合膜）。
在操作S320中，將初始標記板疊置到IC晶片上。如第4圖所示，初始標記板450疊置在IC晶片120上。應注意，初始標記板450比IC封裝100中的標記板150更厚。在第4圖的示例中，在初始標記板450和IC晶片120的頂部之間使用中間層170（例如黏合膜）。
在操作S330中，初始標記板和IC晶片被包封到初始塑膠結構當中。如第5圖所示，對諸如EMC等的塑膠材料進行模制，以形成包封IC晶片120和初始標記板450的初始塑膠結構540。
在操作S340中，對初始塑膠結構進行研磨。如第5圖所示，對初始塑膠結構540進行研磨，以露出初始標記板450，並且對其做進一步研磨，以形成塑膠結構140和標記板150。第6圖示出了所述研磨過程之後的IC封裝。
在操作S350中，在所述標記板上對所述IC封裝進行雷射標記。例如，可以在標記板150上執行雷射標記，以用於識別和溯源。
在操作S360中，可以對IC封裝執行進一步的處理。在示例中，將諸如焊球的接觸結構160附接到封裝基底110上。在示例中，以封裝矩陣陣列的形式執行IC封裝操作。可以對封裝的矩陣陣列劃片，以形成各個IC封裝。之後，對單獨的IC封裝進行測試和分類。之後，過程進行至操作S399並結束。
前文概述了幾個實施例的特徵，從而使本領域技術人員可以更好地理解本公開的各個方面。本領域技術人員應當認識到他們可以容易地使用本公開作為基礎來設計或者修改其他的製程過程或結構，以達到與文中介紹的實施例相同的目的或/及實現與之相同的優點。本領域技術人員還應當認識到這樣的等價設計不脫離本公開的實質和範圍，而且在這裡可以對它們做出各種變化、替換和更改，而不脫離本公開的實質和範圍。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:積體電路封裝110:封裝基底111:第一表面112:第二表面120:IC晶片120A:IC晶片120B:IC晶片120C:IC晶片120D:IC晶片120E:IC晶片120F:IC晶片120G:IC晶片120H:IC晶片130:接合線140:塑膠結構150:標記板155:表面157:表面160:接觸結構170:中間層200:IC封裝210:封裝基底211:第一表面220:IC晶片220A:IC晶片220B:IC晶片220C:IC晶片220D:IC晶片220E:IC晶片220F:IC晶片220G:IC晶片220H:IC晶片230:接合線240:塑膠結構250:標記板255:表面257:表面300:製造過程450:初始標記板540:初始塑膠結構S301:操作S310:操作S320:操作S330:操作S340:操作S350:操作S360:操作S399:操作
當結合附圖閱讀下述詳細描述時，本公開的各個方面將得到最佳的理解。應當指出，根據本行業的慣例，各種特徵並非是按比例繪製的。實際上，為了討論的清楚起見，可以任意增大或者縮小各種特徵的尺寸。 第1圖示出了根據一些實施例的積體電路（IC）封裝100的截面圖。 第2圖示出了根據一些實施例的另一IC封裝200的截面圖。 第3圖示出了概括根據本公開的實施例的示例的製造過程300的流程圖。 第4圖至第6圖示出了根據一些實施例的處於製造過程當中的IC封裝100的截面圖。
100:積體電路封裝
110:封裝基底
111:第一表面
112:第二表面
120:IC晶片
120A:IC晶片
120B:IC晶片
120C:IC晶片
120D:IC晶片
120E:IC晶片
120F:IC晶片
120G:IC晶片
120H:IC晶片
130:接合線
140:塑膠結構
150:標記板
155:表面
157:表面
160:接觸結構
170:中間層

Claims (20)

  1. 一種積體電路（IC）封裝，包括： 封裝基底； 一個或複數個IC晶片，該一個或複數個IC晶片與該封裝基底互連； 標記板，該標記板具有第一主表面和第二主表面，該標記板疊置在該一個或複數個IC晶片上，其中該第一主表面面向該一個或複數個IC晶片；以及 塑膠結構，該塑膠結構被配置為包封該一個或複數個IC晶片和該標記板，其中該標記板的該第二主表面是該IC封裝的外表面的部分。
  2. 如請求項1所述的IC封裝，其中： 該標記板由半導體材料、陶瓷材料、金屬材料和金屬合金材料中的至少一種形成。
  3. 如請求項1所述的IC封裝，其中該標記板被配置為具有階梯結構，並且該第一主表面具有不同於該第二主表面的表面積。
  4. 如請求項1所述的IC封裝，其中： 多條接合線被配置為對該一個或複數個IC晶片與該封裝基底進行互連；並且 該塑膠結構被配置為包封該多條接合線。
  5. 如請求項1所述的IC封裝，其中： 該IC封裝是球柵陣列（BGA）封裝、四邊扁平封裝（QFP）、四邊扁平無引線（QFN）封裝、平面網格陣列（LGA）封裝和引腳柵格陣列（PGA）中的一種。
  6. 如請求項1所述的IC封裝，其中： 使該一個或複數個IC晶片中的相鄰IC晶片錯開，從而為接合線提供空間。
  7. 如請求項1所述的IC封裝，其中： 該標記板被配置為具有長方體形狀，使得該第一主表面和該第二主表面具有基本相同的表面積。
  8. 如請求項7所述的IC封裝，其中： 該標記板中的雷射穿透深度短於該塑膠結構中的雷射穿透深度。
  9. 如請求項1所述的IC封裝，其中： 該標記板具有比該塑膠結構更高的剛度。
  10. 如請求項1所述的IC封裝，其中： 該標記板具有與該一個或複數個IC晶片基本相等的熱膨脹係數（CTE）。
  11. 一種用於製造積體電路（IC）封裝的方法，包括： 在封裝基底上疊置一個或複數個IC晶片； 在該一個或複數個IC晶片上形成具有面向該一個或複數個IC晶片的第一主表面的標記板；以及 形成包封該一個或複數個IC晶片以及該標記板的塑膠結構，其中該標記板的第二主表面是該IC封裝的外表面的部分。
  12. 如請求項11所述的方法，其中形成該標記板和該塑膠結構進一步包括： 將初始標記板和該一個或複數個IC晶片包封到初始塑膠結構中；以及 對該初始塑膠結構和該初始標記板進行研磨，以露出該標記板的該第二主表面。
  13. 如請求項11所述的方法，進一步包括： 在該標記板的該第二主表面上進行雷射標記。
  14. 如請求項11所述的方法，其中在該一個或複數個IC晶片上形成該標記板進一步包括： 將該標記板形成為具有小於該第二主表面且面向該一個或複數個IC晶片的該第一主表面。
  15. 如請求項11所述的方法，進一步包括： 接合用於將該一個或複數個IC晶片與該封裝基底互連的線；以及 形成包封所接合的線的該塑膠結構。
  16. 如請求項11所述的方法，其中在該封裝基底上疊置該一個或複數個IC晶片進一步包括： 使該一個或複數個IC晶片中的相鄰IC晶片錯開，從而為接合線提供空間。
  17. 如請求項11所述的方法，其中在該一個或複數個IC晶片上形成該標記板進一步包括： 將該標記板形成為具有長方體形狀，使得該第一主表面和該第二主表面具有基本相同的表面積。
  18. 如請求項17所述的方法，其中： 該標記板中的雷射穿透深度短於該塑膠結構中的雷射穿透深度。
  19. 如請求項11所述的方法，其中： 該標記板具有比該塑膠結構更高的剛度。
  20. 如請求項11所述的方法，其中： 該標記板具有與該一個或複數個IC晶片基本相等的熱膨脹係數（CTE）。
TW107143793A 2018-10-30 2018-12-06 積體電路封裝以及用於製造積體電路封裝的方法 TWI754785B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/112567 WO2020087253A1 (en) 2018-10-30 2018-10-30 Ic package
WOPCT/CN2018/112567 2018-10-30

Publications (2)

Publication Number Publication Date
TW202017134A true TW202017134A (zh) 2020-05-01
TWI754785B TWI754785B (zh) 2022-02-11

Family

ID=65872658

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107143793A TWI754785B (zh) 2018-10-30 2018-12-06 積體電路封裝以及用於製造積體電路封裝的方法

Country Status (7)

Country Link
US (2) US20200135656A1 (zh)
EP (1) EP3834227B1 (zh)
JP (1) JP7303294B2 (zh)
KR (1) KR20210033010A (zh)
CN (1) CN109564905A (zh)
TW (1) TWI754785B (zh)
WO (1) WO2020087253A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210019226A (ko) * 2019-08-12 2021-02-22 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20220070877A (ko) 2020-11-23 2022-05-31 삼성전자주식회사 반도체 패키지
CN114361115B (zh) * 2021-12-31 2022-08-23 中山市木林森微电子有限公司 一种多芯片埋入式封装模块结构
EP4270476A1 (en) * 2022-04-29 2023-11-01 Infineon Technologies Austria AG Semiconductor package and method for marking a semiconductor package

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788627A (en) * 1986-06-06 1988-11-29 Tektronix, Inc. Heat sink device using composite metal alloy
JPH0563113A (ja) * 1991-09-04 1993-03-12 Sony Corp 樹脂封止型半導体装置
US5461257A (en) * 1994-03-31 1995-10-24 Sgs-Thomson Microelectronics, Inc. Integrated circuit package with flat-topped heat sink
US6238954B1 (en) * 1999-09-28 2001-05-29 Intel Corporation COF packaged semiconductor
TW452956B (en) * 2000-01-04 2001-09-01 Siliconware Precision Industries Co Ltd Heat dissipation structure of BGA semiconductor package
US6559525B2 (en) * 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
JP2001217340A (ja) * 2000-02-01 2001-08-10 Nec Corp 半導体装置及びその製造方法
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
JP3904934B2 (ja) 2002-01-29 2007-04-11 京セラ株式会社 半導体装置
TW563212B (en) * 2002-10-24 2003-11-21 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
JP2005117009A (ja) * 2003-09-17 2005-04-28 Denso Corp 半導体装置およびその製造方法
TWI235473B (en) * 2004-04-22 2005-07-01 Advanced Semiconductor Eng Ball grid array package structure, heat slug structure, and laser mark rework method
DE102004025911B4 (de) * 2004-05-27 2008-07-31 Infineon Technologies Ag Kontaktbehaftete Chipkarte, Verfahren zur Herstellung einer solchen
US7361986B2 (en) 2004-12-01 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Heat stud for stacked chip package
TW200636954A (en) * 2005-04-15 2006-10-16 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package and fabrication method thereof
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
EP2111636B1 (en) 2006-12-21 2021-08-04 Bell Semiconductor, LLC High thermal performance packaging for circuit dies
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
JP2009141147A (ja) * 2007-12-06 2009-06-25 Nec Electronics Corp 半導体装置の製造方法
JP4995764B2 (ja) 2008-04-25 2012-08-08 力成科技股▲分▼有限公司 リード支持型半導体パッケージ
WO2010044783A1 (en) * 2008-10-15 2010-04-22 Texas Instruments Incorporated Semiconductor package having marking layer
TWM357702U (en) * 2009-01-15 2009-05-21 Domintech Co Ltd Chip package with colored pattern
JP5115594B2 (ja) 2010-06-23 2013-01-09 株式会社デンソー 半導体モジュール
CN102004940B (zh) * 2010-11-30 2013-01-09 天水华天科技股份有限公司 一种高密度sim卡封装件的生产方法
JP5740995B2 (ja) 2011-01-17 2015-07-01 富士通株式会社 半導体装置及びその製造方法
JP2013211407A (ja) * 2012-03-30 2013-10-10 J Devices:Kk 半導体モジュール
JP5959097B2 (ja) * 2012-07-03 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置
KR20140009732A (ko) * 2012-07-12 2014-01-23 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
JP5918664B2 (ja) 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
US9159643B2 (en) * 2012-09-14 2015-10-13 Freescale Semiconductor, Inc. Matrix lid heatspreader for flip chip package
WO2014129351A1 (ja) * 2013-02-21 2014-08-28 ピーエスフォー ルクスコ エスエイアールエル 半導体装置とその製造方法
JP5779227B2 (ja) * 2013-03-22 2015-09-16 株式会社東芝 半導体装置の製造方法
WO2014181766A1 (ja) * 2013-05-07 2014-11-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及び半導体装置の製造方法
US9508653B2 (en) * 2013-09-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Die-tracing in integrated circuit manufacturing and packaging
US9318450B1 (en) * 2014-11-24 2016-04-19 Raytheon Company Patterned conductive epoxy heat-sink attachment in a monolithic microwave integrated circuit (MMIC)
KR102506703B1 (ko) * 2014-12-16 2023-03-03 데카 테크놀로지 유에스에이 인코포레이티드 반도체 패키지를 마킹하는 방법
US9412722B1 (en) * 2015-02-12 2016-08-09 Dawning Leading Technology Inc. Multichip stacking package structure and method for manufacturing the same
US9779940B2 (en) * 2015-07-01 2017-10-03 Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
JP6524003B2 (ja) 2016-03-17 2019-06-05 東芝メモリ株式会社 半導体装置
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
US10418341B2 (en) * 2016-08-31 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant
GB2574160B (en) 2017-03-13 2022-04-27 Mitsubishi Electric Corp Microwave device and antenna
JP2018160521A (ja) * 2017-03-22 2018-10-11 東芝メモリ株式会社 半導体装置

Also Published As

Publication number Publication date
KR20210033010A (ko) 2021-03-25
US20220013471A1 (en) 2022-01-13
JP2022505927A (ja) 2022-01-14
WO2020087253A1 (en) 2020-05-07
TWI754785B (zh) 2022-02-11
CN109564905A (zh) 2019-04-02
US20200135656A1 (en) 2020-04-30
EP3834227A4 (en) 2022-03-30
EP3834227A1 (en) 2021-06-16
JP7303294B2 (ja) 2023-07-04
EP3834227B1 (en) 2024-09-04

Similar Documents

Publication Publication Date Title
US10566320B2 (en) Method for fabricating electronic package
US6323066B2 (en) Heat-dissipating structure for integrated circuit package
US9040361B2 (en) Chip scale package with electronic component received in encapsulant, and fabrication method thereof
TWI754785B (zh) 積體電路封裝以及用於製造積體電路封裝的方法
TWI811383B (zh) 半導體封裝
US6781242B1 (en) Thin ball grid array package
TWI618206B (zh) 半導體封裝結構及其製作方法
US20170092510A1 (en) Wafer level fan-out package and method for manufacturing the same
TW201537719A (zh) 堆疊型半導體封裝
US7859118B2 (en) Multi-substrate region-based package and method for fabricating the same
US20190259689A1 (en) Re-Routable Clip for Leadframe Based Product
US20070052082A1 (en) Multi-chip package structure
US20130181351A1 (en) Semiconductor Device Package with Slanting Structures
TWI237363B (en) Semiconductor package
US11848256B2 (en) Semiconductor package having die pad with cooling fins
TWI746939B (zh) 積體電路封裝結構及其製造方法
JP2004260051A (ja) 半導体装置の製造方法および半導体装置
TW201804588A (zh) 半導體裝置及製造方法
US20160104652A1 (en) Package structure and method of fabricating the same
US20180315678A1 (en) Package structure and method of fabricating the same
KR100444175B1 (ko) 볼그리드 어레이 적층칩 패키지
TW408459B (en) Lead finger used in improving the wiring line connection
CN117790329A (zh) 电子封装件的制法
TW200425433A (en) Multi-chip module and the manufacturing method thereof
TW200419736A (en) Multi-chip module