JP7303294B2 - Icパッケージ - Google Patents
Icパッケージ Download PDFInfo
- Publication number
- JP7303294B2 JP7303294B2 JP2021523013A JP2021523013A JP7303294B2 JP 7303294 B2 JP7303294 B2 JP 7303294B2 JP 2021523013 A JP2021523013 A JP 2021523013A JP 2021523013 A JP2021523013 A JP 2021523013A JP 7303294 B2 JP7303294 B2 JP 7303294B2
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- Prior art keywords
- package
- chips
- marking plate
- major surface
- plastic structure
- Prior art date
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- 238000000034 method Methods 0.000 claims description 27
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- 239000000463 material Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010330 laser marking Methods 0.000 claims description 5
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
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- 229910000679 solder Inorganic materials 0.000 description 9
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
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- 229920005989 resin Polymers 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Laser Beam Processing (AREA)
Description
Claims (18)
- 集積回路(IC)パッケージであって、
パッケージ基板と、
前記パッケージ基板と相互接続された1つまたは複数のICチップと、
第1の主表面および第2の主表面を有するマーキングプレートであって、前記第1の主表面を前記1つまたは複数のICチップに向けて、前記1つまたは複数のICチップ上に積み重ねられ、結合ワイヤにより支持されていないマーキングプレートと、
前記マーキングプレートの前記第2の主表面が前記ICパッケージの外面の一部になる状態で、前記1つまたは複数のICチップおよび前記マーキングプレートをカプセル化するように構成されたプラスチック構造とを備え、
前記マーキングプレート内のレーザ透過深さが、前記プラスチック構造内のレーザ透過深さよりも短い、集積回路(IC)パッケージ。 - 前記マーキングプレートが、半導体材料、セラミック材料、金属材料、および金属合金材料の少なくとも1つで形成される、請求項1に記載のICパッケージ。
- 前記マーキングプレートが、階段構造を有するように構成され、前記第1の主表面が、前記第2の主表面とは異なる表面積を有する、請求項1に記載のICパッケージ。
- 複数の前記結合ワイヤが、前記1つまたは複数のICチップを前記パッケージ基板に相互接続するように構成され、
前記プラスチック構造が、前記複数の結合ワイヤをカプセル化するように構成される、請求項1に記載のICパッケージ。 - 前記ICパッケージが、ボールグリッドアレイ(BGA)パッケージ、クアッドフラットパッケージ(QFP)、クアッドフラットノンリード(QFN)パッケージ、ランドグリッドアレイ(LGA)パッケージ、およびピングリッドアレイ(PGA)の1つである、請求項1に記載のICパッケージ。
- 前記1つまたは複数のICチップは、複数のICチップであって、
前記複数のICチップ内の隣接するICチップが、結合ワイヤ用のスペースを提供するためにずらされる、請求項1に記載のICパッケージ。 - 前記マーキングプレートが、前記第1の主表面および前記第2の主表面が実質的に同じ表面積を有する矩形の直方体形状を有するように構成される、請求項1に記載のICパッケージ。
- 前記マーキングプレートが、前記プラスチック構造より高い剛性を有する、請求項1に記載のICパッケージ。
- 前記マーキングプレートが、前記1つまたは複数のICチップと実質的に等しい熱膨張係数(CTE)を有する、請求項1に記載のICパッケージ。
- 集積回路(IC)パッケージを製造するための方法であって、
パッケージ基板上に1つまたは複数のICチップを積み重ねることと、
マーキングプレートを、ワイヤにより支持されないように、第1の主表面を前記1つまたは複数のICチップに向けて前記1つまたは複数のICチップ上に形成することと、
前記マーキングプレートの第2の主表面が前記ICパッケージの外面の一部になる状態で、前記1つまたは複数のICチップおよび前記マーキングプレートをカプセル化するプラスチック構造を形成することとを含み、
前記マーキングプレート内のレーザ透過深さが、前記プラスチック構造内のレーザ透過深さよりも短い、方法。 - 前記マーキングプレートおよび前記プラスチック構造を形成することが、
初期マーキングプレートおよび前記1つまたは複数のICチップを初期プラスチック構造内にカプセル化することと、
前記初期プラスチック構造および前記初期マーキングプレートを研削して、前記マーキングプレートの前記第2の主表面を露出させることとをさらに含む、請求項10に記載の方法。 - 前記マーキングプレートの前記第2の主表面上にレーザマーキングすることをさらに含む、請求項10に記載の方法。
- 前記1つまたは複数のICチップ上に前記マーキングプレートを形成することが、
前記第2の主表面より小さい前記第1の主表面を有する前記マーキングプレートを、前記1つまたは複数のICチップに向けて形成することをさらに含む、請求項10に記載の方法。 - 前記ワイヤを結合して前記1つまたは複数のICチップを前記パッケージ基板に相互接続することと、
前記結合されたワイヤをカプセル化する前記プラスチック構造を形成することとをさらに含む、請求項10に記載の方法。 - 前記1つまたは複数のICチップは、複数のICチップであって、
前記パッケージ基板上に前記複数のICチップを積み重ねることが、
前記複数のICチップ内の隣接するICチップをずらして、結合ワイヤ用のスペースを提供することをさらに含む、請求項10に記載の方法。 - 前記1つまたは複数のICチップ上に前記マーキングプレートを形成することが、
前記第1の主表面および前記第2の主表面が実質的に同じ表面積を有する矩形の直方体形状を有する前記マーキングプレートを形成することをさらに含む、請求項10に記載の方法。 - 前記マーキングプレートが、前記プラスチック構造より高い剛性を有する、請求項10に記載の方法。
- 前記マーキングプレートが、前記1つまたは複数のICチップと実質的に等しい熱膨張係数(CTE)を有する、請求項10に記載の方法。
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KR20220070877A (ko) | 2020-11-23 | 2022-05-31 | 삼성전자주식회사 | 반도체 패키지 |
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EP4270476A1 (en) * | 2022-04-29 | 2023-11-01 | Infineon Technologies Austria AG | Semiconductor package and method for marking a semiconductor package |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003224234A (ja) | 2002-01-29 | 2003-08-08 | Kyocera Corp | 半導体装置 |
JP2009267154A (ja) | 2008-04-25 | 2009-11-12 | Powertech Technology Inc | リードオンパドル型半導体パッケージ |
JP2010514208A (ja) | 2006-12-21 | 2010-04-30 | アギア システムズ インコーポレーテッド | 回路ダイの熱的性能の高いパッケージング |
JP2012009568A (ja) | 2010-06-23 | 2012-01-12 | Denso Corp | 半導体モジュール |
JP2012151172A (ja) | 2011-01-17 | 2012-08-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2014053538A (ja) | 2012-09-10 | 2014-03-20 | Toshiba Corp | 積層型半導体装置とその製造方法 |
JP2017168701A (ja) | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置 |
WO2018168391A1 (ja) | 2017-03-13 | 2018-09-20 | 三菱電機株式会社 | マイクロ波デバイス及び空中線 |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4788627A (en) * | 1986-06-06 | 1988-11-29 | Tektronix, Inc. | Heat sink device using composite metal alloy |
JPH0563113A (ja) * | 1991-09-04 | 1993-03-12 | Sony Corp | 樹脂封止型半導体装置 |
US5461257A (en) * | 1994-03-31 | 1995-10-24 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit package with flat-topped heat sink |
US6238954B1 (en) * | 1999-09-28 | 2001-05-29 | Intel Corporation | COF packaged semiconductor |
TW452956B (en) * | 2000-01-04 | 2001-09-01 | Siliconware Precision Industries Co Ltd | Heat dissipation structure of BGA semiconductor package |
US6559525B2 (en) * | 2000-01-13 | 2003-05-06 | Siliconware Precision Industries Co., Ltd. | Semiconductor package having heat sink at the outer surface |
JP2001217340A (ja) * | 2000-02-01 | 2001-08-10 | Nec Corp | 半導体装置及びその製造方法 |
US6906414B2 (en) * | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
TW563212B (en) * | 2002-10-24 | 2003-11-21 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
JP2005117009A (ja) * | 2003-09-17 | 2005-04-28 | Denso Corp | 半導体装置およびその製造方法 |
TWI235473B (en) * | 2004-04-22 | 2005-07-01 | Advanced Semiconductor Eng | Ball grid array package structure, heat slug structure, and laser mark rework method |
DE102004025911B4 (de) * | 2004-05-27 | 2008-07-31 | Infineon Technologies Ag | Kontaktbehaftete Chipkarte, Verfahren zur Herstellung einer solchen |
US7361986B2 (en) | 2004-12-01 | 2008-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat stud for stacked chip package |
TW200636954A (en) * | 2005-04-15 | 2006-10-16 | Siliconware Precision Industries Co Ltd | Thermally enhanced semiconductor package and fabrication method thereof |
JP4726640B2 (ja) * | 2006-01-20 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20080157342A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Package with a marking structure and method of the same |
JP2009141147A (ja) * | 2007-12-06 | 2009-06-25 | Nec Electronics Corp | 半導体装置の製造方法 |
WO2010044783A1 (en) * | 2008-10-15 | 2010-04-22 | Texas Instruments Incorporated | Semiconductor package having marking layer |
TWM357702U (en) * | 2009-01-15 | 2009-05-21 | Domintech Co Ltd | Chip package with colored pattern |
CN102004940B (zh) * | 2010-11-30 | 2013-01-09 | 天水华天科技股份有限公司 | 一种高密度sim卡封装件的生产方法 |
JP2013211407A (ja) * | 2012-03-30 | 2013-10-10 | J Devices:Kk | 半導体モジュール |
JP5959097B2 (ja) * | 2012-07-03 | 2016-08-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR20140009732A (ko) * | 2012-07-12 | 2014-01-23 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
US9159643B2 (en) * | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
WO2014129351A1 (ja) * | 2013-02-21 | 2014-08-28 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置とその製造方法 |
JP5779227B2 (ja) * | 2013-03-22 | 2015-09-16 | 株式会社東芝 | 半導体装置の製造方法 |
WO2014181766A1 (ja) * | 2013-05-07 | 2014-11-13 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及び半導体装置の製造方法 |
US9508653B2 (en) * | 2013-09-18 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die-tracing in integrated circuit manufacturing and packaging |
US9318450B1 (en) * | 2014-11-24 | 2016-04-19 | Raytheon Company | Patterned conductive epoxy heat-sink attachment in a monolithic microwave integrated circuit (MMIC) |
KR102506703B1 (ko) * | 2014-12-16 | 2023-03-03 | 데카 테크놀로지 유에스에이 인코포레이티드 | 반도체 패키지를 마킹하는 방법 |
US9412722B1 (en) * | 2015-02-12 | 2016-08-09 | Dawning Leading Technology Inc. | Multichip stacking package structure and method for manufacturing the same |
US9779940B2 (en) * | 2015-07-01 | 2017-10-03 | Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Chip package |
TWI567897B (zh) * | 2016-06-02 | 2017-01-21 | 力成科技股份有限公司 | 薄型扇出式多晶片堆疊封裝構造與製造方法 |
US10418341B2 (en) * | 2016-08-31 | 2019-09-17 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant |
JP2018160521A (ja) * | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | 半導体装置 |
-
2018
- 2018-10-30 WO PCT/CN2018/112567 patent/WO2020087253A1/en unknown
- 2018-10-30 CN CN201880002334.9A patent/CN109564905A/zh active Pending
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-
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-
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- 2021-09-24 US US17/448,821 patent/US20220013471A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003224234A (ja) | 2002-01-29 | 2003-08-08 | Kyocera Corp | 半導体装置 |
JP2010514208A (ja) | 2006-12-21 | 2010-04-30 | アギア システムズ インコーポレーテッド | 回路ダイの熱的性能の高いパッケージング |
JP2009267154A (ja) | 2008-04-25 | 2009-11-12 | Powertech Technology Inc | リードオンパドル型半導体パッケージ |
JP2012009568A (ja) | 2010-06-23 | 2012-01-12 | Denso Corp | 半導体モジュール |
JP2012151172A (ja) | 2011-01-17 | 2012-08-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2014053538A (ja) | 2012-09-10 | 2014-03-20 | Toshiba Corp | 積層型半導体装置とその製造方法 |
JP2017168701A (ja) | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | 半導体装置 |
WO2018168391A1 (ja) | 2017-03-13 | 2018-09-20 | 三菱電機株式会社 | マイクロ波デバイス及び空中線 |
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US20220013471A1 (en) | 2022-01-13 |
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US20200135656A1 (en) | 2020-04-30 |
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