JP2017168701A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017168701A JP2017168701A JP2016053319A JP2016053319A JP2017168701A JP 2017168701 A JP2017168701 A JP 2017168701A JP 2016053319 A JP2016053319 A JP 2016053319A JP 2016053319 A JP2016053319 A JP 2016053319A JP 2017168701 A JP2017168701 A JP 2017168701A
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- Prior art keywords
- semiconductor device
- resin layer
- sealing resin
- film
- metal
- Prior art date
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
【解決手段】実施形態の半導体装置1は、基板2と、基板2上に実装された半導体チップ3、4と、半導体チップ3、4を封止する封止樹脂層5と、封止樹脂層5の少なくとも上面を覆うように設けられ、亜鉛、アルミニウム、およびマンガンからなる群より選ばれる少なくとも1つの金属、前記金属を含む合金、金属酸化物、金属窒化物、および金属酸窒化物から選ばれる少なくとも1つを含む膜6とを具備する。
【選択図】図1
Description
図1は第1の実施形態による半導体装置の構成を示す断面図である。図1に示す半導体装置1は、基板2と、基板2上に搭載された半導体チップ3、4と、半導体チップ3、4を封止する封止樹脂層5と、封止樹脂層5の上面5aを覆うように設けられた反り調整膜6とを具備している。反り調整膜6は図2に示すように、封止樹脂層5の上面5aのみならず、封止樹脂層5の側面および基板2の側面まで覆うように設けてもよい。ただし、後に詳述するように、反り調整膜6の効果と製造コスト等との関係から、反り調整膜6は封止樹脂層5の上面5aのみを覆うように設けることが好ましい。
図3は第2の実施形態による半導体装置の構成を示す断面図である。図3に示す半導体装置21は、図1に示す半導体装置1の各構成に加えて、反り調整膜6の表面、封止樹脂層5の側面、および基板2の側面を覆うように設けられた導電性シールド層22を具備する。導電性シールド層22は、半導体チップ3、4や配線基板2から放射される不要電磁波の漏洩を防止したり、外部機器から放射される電磁波が半導体チップ3、4に悪影響を及ぼすことを防止する機能を有する。例えば、半導体チップ3が磁気抵抗メモリ(MRAM)素子を有する場合、外部から半導体装置21内に侵入する電磁波を遮断する必要がある。このような半導体装置21では、導電性シールド層22を設けることが有効である。
図4は第3の実施形態による半導体装置の構成を示す断面図である。図4に示す半導体装置31は、図3に示す半導体装置21の各構成に加えて、導電性シールド層22の表面を覆うように設けられた保護層32を具備している。保護層32の形成材料には、例えばステンレスのような耐食性に優れる材料を用いることが好ましい。反り調整膜6や導電性シールド層22を有する半導体装置の表面を保護層32で覆うことによって、大気中の水分等による反り調整膜6や導電性シールド層22の機能低下を抑制することができる。ここでは、保護層32を導電性シールド層22上に設けた例を説明したが、導電性シールド層22が不要な場合には反り調整膜6上に保護層32を設けてもよい。
Claims (5)
- 基板と、
前記基板上に実装された半導体チップと、
前記半導体チップを封止する封止樹脂層と、
前記封止樹脂層の少なくとも上面を覆うように設けられ、亜鉛、アルミニウム、およびマンガンからなる群より選ばれる少なくとも1つの金属、前記金属を含む合金、金属酸化物、金属窒化物、および金属酸窒化物から選ばれる少なくとも1つを含む膜と
を具備する半導体装置。 - 前記膜は、30GPaを超えるヤング率および16.2×10−6℃を超える熱膨張係数を有する、請求項1に記載の半導体装置。
- 前記膜は0.5μm以上5μm以下の厚さを有する、請求項1または請求項2に記載の半導体装置。
- 前記半導体チップ上における前記封止樹脂層の厚さが300μm以下である、請求項1ないし請求項3のいずれか1項に記載の半導体装置。
- 前記膜は、前記封止樹脂層の上面のみを覆うように設けられており、
さらに、前記膜の表面、前記封止樹脂層の側面、および前記基板の側面を覆うように設けられた、導電性シールド層および保護層から選ばれる少なくなくとも1つを具備する、請求項1ないし請求項4のいずれか1項に記載の半導体装置。
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TW106103789A TWI660467B (zh) | 2016-03-17 | 2017-02-06 | 半導體裝置及形成其之方法 |
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