JP2018113414A - 半導体装置とその製造方法 - Google Patents
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Abstract
Description
本実施形態に係る半導体装置について、その製造工程を追いながら説明する。
図13は、第1例に係る樹脂層40の平面レイアウトについて示す平面図である。
図14は、第2例に係る樹脂層40の平面レイアウトについて示す平面図である。
図15は、第3例に係る樹脂層40の平面レイアウトについて示す平面図である。
図16は、第4例に係る樹脂層40の平面レイアウトについて示す平面図である。
第1実施形態では、図7(b)に示したように、リフローによりはんだバンプ13を溶融し、回路基板1と各半導体素子11、12とを接続した。
第2実施形態では、図19(b)〜図20(b)に示したように、TCB法で回路基板1に各半導体素子11、12を搭載した後に、回路基板1と各半導体素子11、12との間にアンダーフィル樹脂41を充填した。
Claims (10)
- 無機材料の基板と、前記基板の上に形成された樹脂絶縁層とを備えた回路基板と、
前記回路基板の主面にバンプを介して搭載された半導体素子と、
前記半導体素子の横の前記主面に形成され、前記回路基板の縁と対角線の少なくとも一方に沿って延び、かつ前記基板よりも熱膨張率が大きな樹脂層と、
を有することを特徴とする半導体装置。 - 前記樹脂層は、平面視において、前記回路基板の四辺の縁に沿って延びるリング状であることを特徴とする請求項1に記載の半導体装置。
- 前記樹脂層は、平面視において、前記回路基板の相対する二辺に沿って帯状に延びることを特徴とする請求項1に記載の半導体装置。
- 前記樹脂層の端部に、前記二辺とは異なる前記回路基板の残りの二辺に沿って延びる延長部を設けたことを特徴とする請求項3に記載の半導体装置。
- 前記樹脂層の上面の高さは、前記半導体素子の上面の高さよりも低いことを特徴とする請求項1に記載の半導体装置。
- 前記樹脂層は、前記樹脂絶縁層よりも厚いことを特徴とする請求項1に記載の半導体装置。
- 無機材料の基板と、前記基板の上に形成された樹脂絶縁層とを備えた回路基板の主面に、前記回路基板の縁と対角線の少なくとも一方に沿って延びる樹脂層を形成する工程と、
前記回路基板の前記主面に、バンプを備えた半導体素子を搭載する工程と、
前記樹脂層を形成する工程の後に、前記バンプを加熱して溶融することにより、前記バンプを介して前記回路基板と前記半導体素子とを接続する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記樹脂層の材料として熱硬化性樹脂を採用すると共に、
前記バンプを加熱する工程において前記樹脂層を熱硬化させることを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記回路基板の前記主面と前記半導体素子との間にアンダーフィル樹脂を充填する工程を更に有し、
前記樹脂層を形成する工程において、前記アンダーフィル樹脂よりも粘度が高い樹脂を前記樹脂層の材料として使用することを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記樹脂層の材料として熱硬化性樹脂を採用すると共に、
前記回路基板の前記主面にアンダーフィル樹脂を塗布する工程を更に有し、
前記回路基板の前記主面に前記半導体素子を搭載する工程において、前記主面と前記半導体素子との間に前記アンダーフィル樹脂を介在させ、
前記バンプを加熱する工程において、前記樹脂層と前記アンダーフィル樹脂とを同時に熱硬化させることを特徴とする請求項7に記載の半導体装置の製造方法。
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JP2017004445A JP2018113414A (ja) | 2017-01-13 | 2017-01-13 | 半導体装置とその製造方法 |
US15/866,725 US20180204807A1 (en) | 2017-01-13 | 2018-01-10 | Semiconductor device |
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JP2017004445A JP2018113414A (ja) | 2017-01-13 | 2017-01-13 | 半導体装置とその製造方法 |
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JP2018113414A true JP2018113414A (ja) | 2018-07-19 |
JP2018113414A5 JP2018113414A5 (ja) | 2019-10-10 |
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US11387176B2 (en) * | 2017-03-14 | 2022-07-12 | Mediatek Inc. | Semiconductor package structure |
US10784211B2 (en) | 2017-03-14 | 2020-09-22 | Mediatek Inc. | Semiconductor package structure |
US11171113B2 (en) | 2017-03-14 | 2021-11-09 | Mediatek Inc. | Semiconductor package structure having an annular frame with truncated corners |
US11264337B2 (en) | 2017-03-14 | 2022-03-01 | Mediatek Inc. | Semiconductor package structure |
US11362044B2 (en) | 2017-03-14 | 2022-06-14 | Mediatek Inc. | Semiconductor package structure |
EP3671831B1 (en) * | 2018-12-18 | 2024-09-18 | MediaTek Inc. | Semiconductor package structure |
JP7069082B2 (ja) * | 2019-05-08 | 2022-05-17 | 三菱電機株式会社 | 電力用半導体装置およびその製造方法 |
US11570903B2 (en) * | 2019-10-16 | 2023-01-31 | Advanced Micro Devices, Inc. | Process for conformal coating of multi-row surface-mount components in a lidless BGA package and product made thereby |
KR20220029987A (ko) * | 2020-09-02 | 2022-03-10 | 에스케이하이닉스 주식회사 | 3차원 구조의 반도체 장치 |
US11538760B2 (en) | 2020-12-17 | 2022-12-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11694941B2 (en) * | 2021-05-12 | 2023-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die package with multi-lid structures and method for forming the same |
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2017
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