CN107204297A - 半导体装置及形成半导体装置的方法 - Google Patents

半导体装置及形成半导体装置的方法 Download PDF

Info

Publication number
CN107204297A
CN107204297A CN201710117299.2A CN201710117299A CN107204297A CN 107204297 A CN107204297 A CN 107204297A CN 201710117299 A CN201710117299 A CN 201710117299A CN 107204297 A CN107204297 A CN 107204297A
Authority
CN
China
Prior art keywords
semiconductor device
film
sealing resin
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710117299.2A
Other languages
English (en)
Inventor
岩本正次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN107204297A publication Critical patent/CN107204297A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及半导体装置及形成半导体装置的方法。根据一个实施例，半导体装置包含衬底、安装于所述衬底上的半导体芯片、密封所述半导体芯片的密封树脂层及覆盖所述密封树脂层的至少一上表面的膜，所述膜由选自由锌、铝、锰、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组的材料制成。

Description

半导体装置及形成半导体装置的方法
相关申请案的交叉参考
本申请案是基于并主张来自2016年3月17日申请的第2016-53319号日本专利申请案的优先权的权益，所述日本专利申请案的全部内容以引用方式并入本文中。
技术领域
本文所描述的实施例大体上涉及一种半导体装置及一种形成半导体装置的方法。
背景技术
在具有内建存储器芯片的半导体存储器装置(例如，NAND类型快闪存储器)中，微型化及高容量已快速发展。在半导体存储器装置中，为了实现微型化与高容量两者，多个存储器芯片被循序堆叠于布线衬底上，且这些半导体芯片由树脂层密封。为了减小此半导体装置的厚度，将最小化半导体芯片上的密封树脂层的厚度。此微型化可能在热处理(例如，焊接回流过程)期间致使翘曲。
树脂层通常翘曲，使得树脂层的上表面在室温下呈凸面且在高温下呈凹面。减小树脂层的厚度，尤其是在高温下，会增加翘曲。可通过调整密封树脂的性质、衬底材料的性质或衬底的厚度来抑制翘曲。然而，此类调整会增加材料成本或衬底成本。另外，在一些情况中，所需的仅仅通过调整衬底的材料性质或厚度的翘曲抑制在容差内是不可用的。因此，需要一种可抑制半导体装置的翘曲的具成本效益的技术。
发明内容
一般来说，根据一个实施例，一种半导体装置包含：衬底；一或多个半导体芯片，其安装于所述衬底上；密封树脂层，其密封所述一或多个半导体芯片；及膜，其覆盖所述密封树脂层的至少一上表面，所述膜由选自由锌、铝、锰、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组的材料制成。
根据实施例，有可能以低成本获得优异的翘曲抑制效果。
附图说明
图1是说明根据第一实施例的半导体装置的横截面图。
图2是根据第一实施例的半导体装置的修改的横截面图。
图3是说明根据第二实施例的半导体装置的横截面图。
图4是说明根据第三实施例的半导体装置的横截面图。
具体实施方式
本文所描述的实施例提供一种可抑制高温下的翘曲的半导体装置。
在下文中，将参考图式描述根据实施例的半导体装置。在每一实施例中，相同元件符号将给予给相同或类似部件，且在一些情况中，将不重复其描述。图式是示意性的，且在一些情况中，各种尺寸、厚度及尺寸的比率可能会根据实施例的不同而不同。说明书中指示方向的术语，例如上及下，指示相对于基本的方向，且可能不对应于重力方向。
(第一实施例)
图1是说明根据第一实施例的半导体装置1的横截面图。图1中所说明的半导体装置1包含衬底2、安装于衬底2上的半导体芯片3与4、密封半导体芯片3及4的密封树脂层5、及覆盖密封树脂层5的上表面5a的翘曲调整膜6。如图2中所说明，可提供翘曲调整膜6，以便不仅覆盖密封树脂层5的上表面5a，而且覆盖密封树脂层5的侧表面及衬底2的侧表面。下文详细描述的实施例具有仅覆盖密封树脂层5的上表面5a的翘曲调整膜6。相对于图2的实施例，此实施例减小制造成本。
衬底2是布线网络(未说明)被提供于绝缘树脂衬底的表面上或内的布线衬底。一个实例是使用玻璃纤维环氧树脂或BT树脂(双马来酰亚胺三嗪树脂)的印刷布线板(多堆叠的印刷板)。印刷布线板的布线衬底2通常包含作为布线网络的铜(Cu)层7。布线衬底2包含第一表面2a(其为形成表面的外部端子)及第二表面2b(其为其上安装半导体芯片3及4的表面)。布线衬底2的第一表面2a包含外部电极8。
外部端子(未说明)形成于布线衬底2的外部电极8上。在其中半导体装置1被用作BGA封装的情况中，外部端子是使用焊接球或焊接镀层的突出端子。在其中半导体装置1被用作LGA封装的情况中，使用金(Au)镀层的金属平台作为外部端子。布线衬底2的第二表面2b(其为其上安装半导体芯片3及4的表面)包含内部电极9。内部电极9的至少一部分通过布线衬底2或外部电极8的布线网络被电连接到外部端子。
第一半导体芯片3被安装于布线衬底2的第二表面2b上。第一半导体芯片3可包含以逐步方式堆叠使得电极垫中的每一者可暴露的多个层。第一半导体芯片3的具体实例包含存储器芯片，例如NAND类型快闪存储器，但不限于其。图1说明第一半导体芯片3具有在第一方向上以逐步方式偏移而堆叠的四个层及其上所布置的在与第一方向相反的方向上以逐步方式偏移而堆叠的另外四个层。然而，被安装于布线衬底2上的第一半导体芯片3中的层的数目或安装结构并不限于上文所描述的数目或安装结构。第一半导体芯片3中的层的数目可为一个或多个。
在图1中所展示的第一半导体芯片3的多个层中，使用粘附层(未说明)将第一层粘附到布线衬底2的第二表面2b。也可使用粘附层将每一随后层粘附到先前层。通过分别使所堆叠的层偏移而使第一半导体芯片3的第一到第四层的电极垫朝上暴露，且所述电极垫通过接合线10被电连接到布线衬底2的内部电极9。第一半导体芯片3的第五到第八层在与第一方向相反的方向上被堆叠于第四层上，使得电极垫被暴露。第一半导体芯片3的第五到第八层的电极垫通过接合线10被电连接到内部电极9。
第二半导体芯片4(在图1中仅展示一个芯片)进一步被安装于布线衬底2的第二表面2b上。第二半导体芯片4的电极垫通过接合线11被电连接到布线衬底2的内部电极9。第二半导体芯片4的实例包含控制器芯片，在其中半导体装置1是存储器装置、系统LSI芯片(例如，接口芯片、逻辑芯片及RF芯片)的情况中，所述控制器芯片在第一半导体芯片3与外部装置之间发射并接收数字信号。第二半导体芯片4可被掩埋或被附接到将第一半导体芯片3粘附到布线衬底2的第二表面2b的粘附层。第二半导体芯片4可被布置于第一半导体芯片3上。然而，通过将第二半导体芯片4安装于布线衬底2的第二表面2b上，有可能减小从第二半导体芯片4(例如，系统LSI芯片)到布线衬底2的布线长度。因此，有可能使半导体装置1的响应加速。
含有绝缘树脂(例如，环氧树脂)的密封树脂层5(例如)被模制于布线衬底2的第二表面2b上，使得第一半导体芯片3及第二半导体芯片4与接合线10及11被密封在一起。第一半导体芯片3上的密封树脂层5的厚度并非特别受限，但为使半导体装置1的厚度最小化，其可等于或小于300μm。可具有嵌入为第一半导体芯片3的存储器芯片(例如，NAND类型快闪存储器)的半导体装置1的厚度通常被最小化以用于移动电子装置中。对于此类使用，半导体芯片3上的树脂的厚度通常等于或小于150μm。为了提供良好的第一半导体芯片3的密封与用于激光标记的充足的雕刻深度，半导体芯片3上的树脂的厚度通常等于或大于50μm。
在密封树脂层5的上表面5a上提供用于抑制尤其是在高温下的半导体装置1的翘曲的翘曲调整膜6。使用(例如)溅镀方法或气相沉积方法在密封树脂层5上形成翘曲调整膜6。用于形成翘曲调整膜6的材料可选自由由锌(Zn)、铝(Al)及锰(Mn)、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组。也可使用上述材料的组合。在本本文，形成密封树脂层5的树脂材料的弹性模量较低。举例来说，典型的环氧树脂的杨氏模量为大约30GPa。相比之下，上文所描述的金属(Zn、Al及Mn)的杨氏模量中的任何者都超过30GPa。
通过使用具有高于密封树脂层5的弹性模量的弹性模量的材料在密封树脂层5上形成翘曲调整膜6，在(例如)半导体装置1从室温(25℃)被加热到二次安装温度(例如，250℃)时，密封树脂层5的膨胀被抑制。因此，半导体装置1的翘曲在高温下被抑制。如上所述，翘曲调整膜6的杨氏模量通常超过30GPa，且其可等于或高于50GPa。因为上述金属(Zn、Al及Mn)的合金具有类似于金属本身的弹性模量，所以上述材料中的任何者的合金膜可用于翘曲调整膜6。
此外，代替上文所描述的金属膜或合金膜，金属化合物膜(例如，金属氧化物膜、金属氮化物膜及/或金属氮氧化物膜)可被用作翘曲调整膜6。金属化合物膜具有等于或高于上文所描述的金属膜或合金膜的弹性模量的弹性模量以及将抑制高温下的翘曲的高硬度。可用于翘曲调整膜6中的金属化合物的实例并不特别受限，且可包含金属氧化物(例如，氧化铝(Al2O3)、氧化硅(SiO2)、氧化钛(TiO2)及氧化锆(ZrO2))、金属氮化物(例如，氮化硅(Si3N4)、氮化铝(AlN)及氮化钛(TiN))及金属氮氧化物(例如，氮氧化硅(SiON)及塞隆或硅铝氮氧化物(SiAlON))。
用于形成翘曲调整膜6的更多有用材料具有高于Cu的热膨胀系数的热膨胀系数(16.2×10-6℃)。如上文所描述，一般来说，布线衬底2具有作为布线网络的Cu层7。在半导体装置1中，Cu布线层7在加热期间促成布线衬底2的膨胀。因此，在较薄类型的半导体装置1的实施例中，翘曲增加。就此而言，通过使用具有高于Cu层7的热膨胀系数的热膨胀系数的材料在密封树脂层5上形成翘曲调整膜6，有可能抑制由Cu层7的热膨胀所致使或增强的半导体装置1的翘曲。
具有高于Cu的热膨胀系数的热膨胀系数(α)的材料的实例包含金属Zn(α＝30.2×10-6℃)、Al(α＝23.7×10-6℃)及Mn(α＝21.6×10-6℃)或这些金属中的任何者的合金。在标1中列出可用于形成翘曲调整膜6的各种材料的杨氏模量及热膨胀系数。用于形成翘曲调整膜6的多数材料具有高于16.2×10-6℃的热膨胀系数(α)，且一些等于或高于20×10-6℃。
表1
翘曲调整膜6的厚度可等于或大于0.5μm且等于或小于5μm。当翘曲调整膜6的厚度小于0.5μm时，高温下的密封树脂层5的翘曲抑制可能是不充分的。当翘曲调整膜6的厚度超过5μm时，翘曲调整膜6到密封树脂层5的粘附在翘曲调整膜6是通过溅镀或其它气相沉积方法形成时趋向于恶化，从而减小翘曲抑制的有效性。在此情况中，在布线衬底2(特定来说，Cu层7)的加热或膨胀时由密封树脂层5的膨胀致使的密封树脂层5的变形仍为过度。此外，当翘曲调整膜6的厚度增加时，用于形成膜的成本增加，且变得难以使半导体装置1的厚度最小化。翘曲调整膜6的厚度可等于或大于1μm且等于或小于3μm。
如上文所描述，有可能在加热时通过使用具有高于形成密封树脂层5的材料的弹性模量的弹性模量的材料在密封树脂层5上形成翘曲调整膜6来抑制密封树脂层5的膨胀。此外，通过使用由满足上述弹性模量且具有高于Cu层7的热膨胀系数的热膨胀系数的材料制成的翘曲调整膜6，有可能抑制在加热期间由Cu层7的热膨胀致使的密封树脂层5的膨胀。以此方式，第一半导体芯片3上的树脂的厚度可被减小，且因此，有可能减小加热期间半导体装置1的翘曲量，尤其是其中密封树脂层5的上表面5a变形成凹面形状的翘曲。此外，因为半导体装置1的翘曲由翘曲调整膜6抑制，所以有可能将半导体装置1的制造成本保持为低。因此，有可能以低成本提供具有较少翘曲的较薄类型的半导体装置1。
可通过测量半导体装置中不具有翘曲调整膜6的翘曲并比较半导体装置1的翘曲来确认使用翘曲调整膜6的翘曲抑制。此类测量通常返回表示凸面翘曲的正值及表示凹面翘曲的负值。半导体装置(例如，半导体装置1，但不具有翘曲调整膜6)在室温下翘曲成凸面形状(正值)，且在被加热时变形成凹面形状(负值)，如通过如上文所描述的测量所确认。
如上文所描述，在加热期间不包含翘曲调整膜6的半导体装置的翘曲量较大且可能超过半导体装置中的可允许翘曲容限。相反，在包含翘曲调整膜6的半导体装置的情况中，已确认半导体装置1在室温下具有凸面形状(正值)，且在加热期间变形，但所述变形较小，且加热期间的翘曲量具有正值。
可提供翘曲调整膜6以便仅覆盖如上文所描述的密封树脂层5的上表面5a，或可提供翘曲调整膜6以便覆盖密封树脂层5的侧表面及衬底2的侧表面。当施加翘曲调整膜6以便覆盖全部密封树脂层5或衬底2的侧表面时，翘曲调整膜6在将半导体装置1从制造衬底上的相邻装置分开之后被施加。然而，当提供翘曲调整膜6以便仅覆盖密封树脂层5的上表面5a时，可在将晶片划分到个别装置中之前的晶片工艺期间形成翘曲调整膜6，所以形成翘曲调整膜6的成本得以减小。通过提供翘曲调整膜6以便仅覆盖密封树脂层5的上表面5a，有可能以低成本获得优异的翘曲抑制效果。
(第二实施例)
图3是说明根据第二实施例的半导体装置21的配置的横截面图。图3中所说明的半导体装置21包含导电屏蔽层22，其经提供以便覆盖除图1中所说明的半导体装置1的配置外的翘曲调整膜6的前表面、密封树脂层5的侧表面及衬底2的侧表面。导电屏蔽层22防止来自第一半导体芯片3及第二半导体芯片4及布线衬底2的外来电磁波的发射，且从而防止来自外部装置的电磁干扰影响第一半导体芯片3及第二半导体芯片4。举例来说，当半导体芯片3包含磁阻存储器(MRAM)元件时，通常有必要屏蔽来自外部电磁波的MRAM元件。在半导体装置21中，导电屏蔽层22提供此屏蔽。
导电屏蔽层22被电连接到布线衬底2中的接地。为了将导电屏蔽层22电连接到接地，接地的部分被暴露在布线衬底2的侧表面处。导电屏蔽层22被电连接到布线衬底2的侧表面处暴露的接地的部分。通过在划切之后在半导体装置21的前表面上溅镀金属材料(例如，铜、银或镍)形成导电屏蔽层22。可能有用的是基于导电屏蔽层22的电阻率选择其厚度。举例来说，导电屏蔽层22的厚度可经选择使得薄膜电阻值(按厚度划分的导电屏蔽层22的电阻率)变成等于或低于0.5欧姆(Ω)。以此方式，有可能可重复地抑制来自半导体装置21的外来电磁波的发射或来自外部电磁波的干扰。
翘曲调整膜6及导电屏蔽层22不限于以图中所展示的顺序形成于上述密封树脂层5上。导电屏蔽层22可直接形成于密封树脂层5上，且翘曲调整膜6可形成于导电屏蔽层22上。在此类情况中，在划切之后执行翘曲调整膜6，这是因为划切在形成导电屏蔽层22之前。为了利用在整个制造衬底上方形成翘曲调整膜6的效率，翘曲调整膜6可形成于整个衬底上方，所述衬底可被划切到个别装置中，且接着，导电屏蔽层22可经形成以覆盖翘曲调整膜6及布线衬底2的侧表面。此外，通过在密封树脂层5上直接形成翘曲调整膜6，翘曲调整膜6的粘附得以改进。
(第三实施例)
图4是说明根据第三实施例的半导体装置31的配置的横截面图。图4中所说明的半导体装置31包含覆盖除图3中所说明的半导体装置21的配置外的导电屏蔽层22的保护层32。保护层32的更有用材料在防腐方面是优异的。不锈钢是一个实例。通过覆盖包含翘曲调整膜6及具有保护层32的导电屏蔽层22的半导体装置的前表面，有可能抑制翘曲调整膜6及导电屏蔽层22的功能归因于空气中的湿度或类似物的恶化。在本文中，描述在导电屏蔽层22上提供保护层32的实例。然而，当导电屏蔽层22不必要时，可在翘曲调整膜6正上方直接提供保护层32。
虽然已描述某些实施例，但这些实施例仅已通过实例提出，且不希望限制本发明的范围。事实上，本文所描述的新型实施例可以多种其它形式体现；此外，可在不背离本发明的精神的情况下，进行呈本文所描述的实施例的形式的各种省略、替代及改变。所附权利要求书及其等效物希望涵盖如将落于本发明的范围及精神内的此类形式或修改。

Claims (20)

1.一种半导体装置，其包括：
衬底；
半导体芯片，其安装于所述衬底上；
密封树脂层，其密封所述半导体芯片；及
膜，其覆盖所述密封树脂层的至少一上表面，所述膜由选自由锌、铝、锰、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组的材料制成。
2.根据权利要求1所述的半导体装置，
其中所述膜具有超过30GPa的杨氏模量及超过16.2×10-6℃的热膨胀系数。
3.根据权利要求2所述的半导体装置，
其中所述膜具有等于或大于0.5μm且等于或小于5μm的厚度。
4.根据权利要求3所述的半导体装置，
其中所述半导体芯片上的所述密封树脂层的厚度等于或小于300μm。
5.根据权利要求4所述的半导体装置，
其中所述膜仅覆盖所述密封树脂层的所述上表面，且所述装置进一步包括覆盖所述膜的前表面、所述密封树脂层的侧表面及所述衬底的侧表面的导电屏蔽层及保护层中的至少一者。
6.根据权利要求1所述的半导体装置，其中所述膜由金属化合物制成。
7.根据权利要求6所述的半导体装置，其进一步包括导电屏蔽层及保护层中的至少一者。
8.根据权利要求7所述的半导体装置，其中所述导电屏蔽层覆盖所述膜的前表面、所述密封树脂层的侧表面及所述衬底的侧表面。
9.根据权利要求8所述的半导体装置，其中所述保护层是防腐的。
10.一种半导体装置，其包括：
衬底；
半导体芯片，其安装于所述衬底上；
密封树脂层，其密封所述半导体芯片；及
膜，其覆盖所述密封树脂层的至少一上表面，所述膜具有等于或大于0.5μm且等于或小于5μm的厚度，其中所述膜由选自由锌、铝、锰、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组的材料制成。
11.根据权利要求10所述的半导体装置，其中所述膜仅覆盖所述密封树脂层的所述上表面。
12.根据权利要求11所述的半导体装置，其进一步包括导电屏蔽层及保护层中的至少一者。
13.根据权利要求12所述的半导体装置，其中所述导电屏蔽层覆盖所述膜的前表面、所述密封树脂层的侧表面及所述衬底的侧表面。
14.根据权利要求13所述的半导体装置，其中所述膜由具有等于或高于50GPa的杨氏模量的材料制成。
15.根据权利要求14所述的半导体装置，其中所述导电屏蔽层连接到所述衬底的所述侧表面处的接地线。
16.根据权利要求15所述的半导体装置，其中所述保护层是防腐的。
17.一种形成半导体装置的方法，其包括：
将多个半导体芯片粘附到布线衬底；
将所述半导体芯片电连接到所述布线衬底；
在所述衬底上方施加密封树脂；
在所述密封树脂的上表面上形成翘曲调整层，所述翘曲调整层由选自由锌、铝、锰、其合金、金属氧化物、金属氮化物及金属氮氧化物组成的群组的材料制成；及
将所述衬底分离到多个半导体装置中。
18.根据权利要求17所述的形成所述半导体装置的方法，其中所述翘曲调整膜具有超过30GPa的杨氏模量及超过16.2×10-6℃的热膨胀系数。
19.根据权利要求17所述的形成所述半导体装置的方法，其进一步包括在所述半导体装置中的每一者上形成导电屏蔽层，所述导电屏蔽层覆盖所述翘曲调整膜的所述前表面且连接到所述布线衬底中的暴露的接地线。
20.根据权利要求19所述的形成所述半导体装置的方法，其进一步包括在所述导电屏蔽层上方形成防腐的保护层。
CN201710117299.2A 2016-03-17 2017-03-01 半导体装置及形成半导体装置的方法 Pending CN107204297A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-053319 2016-03-17
JP2016053319A JP6524003B2 (ja) 2016-03-17 2016-03-17 半導体装置

Publications (1)

Publication Number Publication Date
CN107204297A true CN107204297A (zh) 2017-09-26

Family

ID=59847053

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710117299.2A Pending CN107204297A (zh) 2016-03-17 2017-03-01 半导体装置及形成半导体装置的方法

Country Status (4)

Country Link
US (1) US10062627B2 (zh)
JP (1) JP6524003B2 (zh)
CN (1) CN107204297A (zh)
TW (1) TWI660467B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768313A (zh) * 2017-10-24 2018-03-06 南京矽邦半导体有限公司 一种半导体装置及其制作方法
CN110718544A (zh) * 2018-07-12 2020-01-21 东芝存储器株式会社 半导体装置
CN111716848A (zh) * 2019-03-19 2020-09-29 日东电工株式会社 密封用片

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018113414A (ja) * 2017-01-13 2018-07-19 新光電気工業株式会社 半導体装置とその製造方法
KR20210033010A (ko) * 2018-10-30 2021-03-25 양쯔 메모리 테크놀로지스 씨오., 엘티디. Ic 패키지
BR112021007364B1 (pt) 2018-12-07 2024-01-30 Yangtze Memory Technologies Co., Ltd Dispositivo de memória
JP2020150145A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
US11508668B2 (en) * 2020-12-03 2022-11-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP2023096595A (ja) * 2021-12-27 2023-07-07 キオクシア株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247604A (zh) * 2012-02-01 2013-08-14 三美电机株式会社 电子模块及其制造方法
CN103681640A (zh) * 2012-09-10 2014-03-26 株式会社东芝 叠层型半导体装置及其制造方法
CN104022117A (zh) * 2013-02-28 2014-09-03 株式会社东芝 半导体装置及其制造方法
JP2015207603A (ja) * 2014-04-17 2015-11-19 株式会社デンソー 半導体装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58199543A (ja) * 1982-05-17 1983-11-19 Toshiba Corp 半導体装置のパツケ−ジ
JP2001127212A (ja) 1999-10-26 2001-05-11 Hitachi Ltd 半導体装置および半導体装置の製造方法
WO2002061827A1 (fr) 2001-01-31 2002-08-08 Sony Corporation DISPOSITIF à SEMI-CONDUCTEUR ET SON PROCEDE DE FABRICATION
JP2002359345A (ja) 2001-03-30 2002-12-13 Toshiba Corp 半導体装置及びその製造方法
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7064426B2 (en) 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
JP2004128063A (ja) 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US7187060B2 (en) * 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
KR100517075B1 (ko) 2003-08-11 2005-09-26 삼성전자주식회사 반도체 소자 제조 방법
US7180173B2 (en) * 2003-11-20 2007-02-20 Taiwan Semiconductor Manufacturing Co. Ltd. Heat spreader ball grid array (HSBGA) design for low-k integrated circuits (IC)
JP2006019425A (ja) 2004-06-30 2006-01-19 Sony Corp 回路モジュール体及びその製造方法
JP4815905B2 (ja) 2005-07-11 2011-11-16 株式会社デンソー 半導体装置およびその製造方法
JP2007242888A (ja) 2006-03-08 2007-09-20 Sony Corp 半導体パッケージ製造方法
US7928538B2 (en) * 2006-10-04 2011-04-19 Texas Instruments Incorporated Package-level electromagnetic interference shielding
KR101057368B1 (ko) 2007-01-31 2011-08-18 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
JP2008305948A (ja) 2007-06-07 2008-12-18 Denso Corp 半導体装置およびその製造方法
US7923846B2 (en) * 2007-11-16 2011-04-12 Stats Chippac Ltd. Integrated circuit package-in-package system with wire-in-film encapsulant
JP4977183B2 (ja) 2009-09-30 2012-07-18 株式会社東芝 半導体装置
JP2011146486A (ja) 2010-01-13 2011-07-28 Panasonic Corp 光学デバイスおよびその製造方法ならびに電子機器
JP2013062328A (ja) 2011-09-12 2013-04-04 Toshiba Corp 半導体装置
JP5936968B2 (ja) 2011-09-22 2016-06-22 株式会社東芝 半導体装置とその製造方法
US8704341B2 (en) * 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
US9484313B2 (en) * 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
CN103400825B (zh) * 2013-07-31 2016-05-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247604A (zh) * 2012-02-01 2013-08-14 三美电机株式会社 电子模块及其制造方法
CN103681640A (zh) * 2012-09-10 2014-03-26 株式会社东芝 叠层型半导体装置及其制造方法
CN104022117A (zh) * 2013-02-28 2014-09-03 株式会社东芝 半导体装置及其制造方法
JP2015207603A (ja) * 2014-04-17 2015-11-19 株式会社デンソー 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768313A (zh) * 2017-10-24 2018-03-06 南京矽邦半导体有限公司 一种半导体装置及其制作方法
CN110718544A (zh) * 2018-07-12 2020-01-21 东芝存储器株式会社 半导体装置
CN110718544B (zh) * 2018-07-12 2024-01-12 铠侠股份有限公司 半导体装置
CN111716848A (zh) * 2019-03-19 2020-09-29 日东电工株式会社 密封用片

Also Published As

Publication number Publication date
US20170271231A1 (en) 2017-09-21
TWI660467B (zh) 2019-05-21
JP6524003B2 (ja) 2019-06-05
TW201810552A (zh) 2018-03-16
JP2017168701A (ja) 2017-09-21
US10062627B2 (en) 2018-08-28

Similar Documents

Publication Publication Date Title
CN107204297A (zh) 半导体装置及形成半导体装置的方法
US7476975B2 (en) Semiconductor device and resin structure therefor
US7288728B2 (en) Electronic package and packaging method
US8729710B1 (en) Semiconductor package with patterning layer and method of making same
US8302277B2 (en) Module and manufacturing method thereof
US6781849B2 (en) Multi-chip package having improved heat spread characteristics and method for manufacturing the same
US7202554B1 (en) Semiconductor package and its manufacturing method
US6242283B1 (en) Wafer level packaging process of semiconductor
US7473989B2 (en) Flip-chip package
US8766463B2 (en) Package carrier
US20120133056A1 (en) Semiconductor device, electronic apparatus and semiconductor device fabricating method
TWI707434B (zh) 半導體封裝及其製造方法
US20210111109A1 (en) Flat no-lead package with surface mounted structure
CN113224037B (zh) 半导体封装体及其制造方法
US11804449B2 (en) Semiconductor device and manufacturing method thereof
US20040004277A1 (en) Semiconductor package with reinforced substrate and fabrication method of the substrate
TWI830314B (zh) 半導體裝置
US10985153B2 (en) Semiconductor device
US20230411239A1 (en) Semiconductor device and method of manufacturing semiconductor device
TW421836B (en) Package structure of semiconductor chip on substrate
US20040207066A1 (en) Lead on chip package and leadframe thereof
JPH0774305A (ja) 半導体メモリ装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170926

RJ01 Rejection of invention patent application after publication