TW434762B - Flexible substrate based ball grid array package structure - Google Patents
Flexible substrate based ball grid array package structure Download PDFInfo
- Publication number
- TW434762B TW434762B TW88117906A TW88117906A TW434762B TW 434762 B TW434762 B TW 434762B TW 88117906 A TW88117906 A TW 88117906A TW 88117906 A TW88117906 A TW 88117906A TW 434762 B TW434762 B TW 434762B
- Authority
- TW
- Taiwan
- Prior art keywords
- flexible sheet
- substrate
- flexible
- wafer
- patent application
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
434762 __案號88117f)0fi_ 年月 日 |丨 五、發明卿（〇 —^ ---- 【發明領域】 本發明係有關於一種可撓性基板球格陣列（f丨ex i b i e substrate based BGA)封裝構造，其特別有關一種用以形 成該可撓性基板球格陣列封裝構造之可撓性薄片基板 (flexible film substrate)及其製造方法。 【先前技術】 習用之可撓性基板球格陣列（flexible substrate based BGA)封裝構造100 (參照第一圖）一般係利用一可 撓性薄片基板（flexible film substrate)ll◦(參照第二 圊）來承載一半導體晶片120。該可撓性薄片基板11〇具有 複數個晶片連接墊1 1 0 a，設於該半導體晶片1 2 〇之周圍。 該半導體晶片1 2 0係利用一不導電膠層1 22 (例如一環氧樹 脂）固著於該可撓性薄片基板並且經由複數條連接線 1 3 0電性連接至該複數個晶片連接墊丨丨0a。該複數個晶 連接塾110a係經由導電線路（conductive traces) 11 (參照第二圖）電性連接至相對應之錫球銲墊1 1 〇 b。該可: 撓性薄片基板110具有複數個孔11 〇c對應於該複數個錫球 銲墊11 Ob設置使得該每一個錫球銲墊11 〇b係有部份裸露於 該孔110c用以設置一錫球140。該可撓性薄片基板11〇、半 導體晶片120以及複數條連接線1 30係包覆於一封膠體 1 5 0 6該封膠體1 5 0係以絕緣材料例如環氧樹脂（e p 〇 χ y )製 成。該可撓性基板球格陣列（flexible substrate based BGA)封裝構造1 0 0係利用該複數個錫球1 40安裝於一基板 (未示於圖_)’例如一印刷電路板β - 該複數個晶片連接墊1 1 0a以及複數個錫球銲墊11 〇b之表434762 __Case No. 88117f) 0fi_ Year, month and date | 丨 Fifth, invention (0— ^ ---- [Field of invention] The present invention relates to a flexible substrate ball grid array (f 丨 ex ibie substrate based BGA ) Packaging structure, in particular, relates to a flexible film substrate for forming the flexible substrate ball grid array package structure and a method for manufacturing the same. [Prior Art] Conventional flexible substrate ball grid array (Flexible substrate based BGA) package structure 100 (refer to the first figure) generally uses a flexible film substrate (refer to the second frame) to carry a semiconductor wafer 120. The flexible sheet substrate 110 has a plurality of wafer connection pads 110a, and is arranged around the semiconductor wafer 120. The semiconductor wafer 120 is fixed to the semiconductor wafer by a non-conductive adhesive layer 12 (such as an epoxy resin). The flexible sheet substrate is electrically connected to the plurality of chip connection pads via a plurality of connection lines 130. The plurality of crystal connections 110a are connected via conductive traces 11 (refer to Figure) Electrically connected to the corresponding solder ball pads 1 1 0b. This can: The flexible sheet substrate 110 has a plurality of holes 11 0c corresponding to the plurality of solder ball pads 11 Ob so that each of the tin The ball pad 11 〇b is partially exposed in the hole 110c for setting a solder ball 140. The flexible sheet substrate 110, the semiconductor wafer 120, and a plurality of connecting wires 1 30 are covered with a piece of colloid 1 5 0 6 The sealing compound 150 is made of an insulating material such as epoxy resin (ep 〇χ y). The flexible substrate ball grid array (flexible substrate based BGA) package structure 1 0 0 uses the plurality of The solder ball 1 40 is mounted on a substrate (not shown in the figure). For example, a printed circuit board β-the plurality of wafer connection pads 1 1 0a and the plurality of solder ball pads 11 0b.
P99-052,ptc 第5頁 434762P99-052, ptc p. 5 434762
面般係鍍上一層與習用連接線（bond i ng wi re )材料結人 广及導電性較佳之金屬，例如金（g〇ld)。然而，由於‘二 該不導電膠層1 2 2之附著力不佳，因此該可撓性薄片基板 Π〇之晶片設置區域160的中央區域一般係不設錫球銲塾 11 〇b ’藉此增加該可撓性薄片基板丨丨〇與不導電膠層間之 附著力’而使該半導體晶片12〇更牢固地黏在該可撓性薄 然而’由於該錫球銲墊11 〇b未均勻的分佈在該可撓性薄 片基板110之晶片設置區域160，因此造成該晶片設置區域 160的中央區域容易因其與其他部分熱膨脹係數不一致 (CTE mismatch)所產生之應力而產生變形，其最後可能導 致晶片破裂（d i e c rack)或在晶片與基板間產生層裂 (delamination)。 【發明概要】 > 本發明之主要目的係提供一種可撓性基板球格陣列^1' (flexible substrate based BGA)封裝構造，其包含^^ 挽性薄片基板具有一晶片設置區域用以承載一半導體晶 片’其中可撓性薄片基板設有至少一虛整（dummy pad)， 其大致位於該晶片設置區域之中央，藉此改善晶片破裂或 層裂的問題。 本發明之次要目的係提供一種可撓性基板球格陣列 (flexible substrate based BGA)封裝構造，其包含一半 導體晶片利用一不導電膠層固著於一可撓性薄片基板之晶_ 片設置區域，該可撓性薄片基板設有至少一虛墊，其大致 位於該晶片設置區域之中央，其中該虛墊具有一氧化The surface is generally plated with a layer of metal that is bonded to a conventional connection wire (bond ng wi re) and has a better conductivity, such as gold (goll). However, due to the poor adhesion of the non-conductive adhesive layer 1 2 2, the central region of the wafer setting region 160 of the flexible sheet substrate 11 is generally not provided with a solder ball 11 0 b. Increasing the adhesion between the flexible sheet substrate and the non-conductive adhesive layer 'to make the semiconductor wafer 120 more firmly adhere to the flexible thin film. However,' because the solder ball pads 11 and 0b are not uniform. The wafer setting area 160 of the flexible sheet substrate 110 is distributed, so that the central area of the wafer setting area 160 is liable to be deformed due to the stress generated by the CTE mismatch with other parts, which may eventually cause A die rack or delamination occurs between the wafer and the substrate. [Summary of the invention] > The main object of the present invention is to provide a flexible substrate ball grid array ^ 1 '(flexible substrate based BGA) package structure, which includes a ^^ flexible sheet substrate with a wafer setting area for carrying a A semiconductor wafer 'in which the flexible sheet substrate is provided with at least one dummy pad, which is located approximately in the center of the region where the wafer is disposed, thereby improving the problem of wafer cracking or delamination. A secondary object of the present invention is to provide a flexible substrate based BGA package structure, which includes a semiconductor wafer fixed to a flexible thin-film substrate by a non-conductive adhesive layer. Area, the flexible sheet substrate is provided with at least one dummy pad, which is located approximately in the center of the wafer setting area, wherein the dummy pad has an oxide
P99-052.ptc 第6頁 434762 __案號88117906 _年月日 修正__. 五、發明說明（3) (cupric oxide)覆蓋層用以增加其與該不導電膠層間之附 著力。 根據本發明較佳實施例之可撓性基板球格陣列封裝構 造，其主要係包含一半導體晶片利用一不導電膠層固著於 一可撓性薄片基板。該可撓性薄片基板包含一可撓性薄片 具有一晶片設置區域用以承載該半導體晶片。該可撓性薄 片之上表面設有複數個晶片連接墊、複數個錫球銲墊以及 至少一虛墊（dummy pad)大致位於該晶片設置區域之中 央。該虛塾之表面較佳.具有一氧化銅（CUpric oxide)覆蓋 層用以增加其與該不導電膠層間之附著力。該複數個晶片 連接墊係設於該晶片設置區域之週圍，用以電性連接至該 半導體晶片。該複數個錫球銲墊係環繞該虛墊並且電性連 接至相對應的晶片連接墊。該可撓性薄片具有複數個孔對 應於該複數個錫球銲墊設置使得該每一個錫球銲墊係有部 份裸露於該孔用以設置一錫球。該半導體晶片以及該可| 性薄片基板之上表面係為一封膠體包覆。 ^ 根據本發明之可撓性基板球格陣列（f 1 ex i b 1 e substrate based BGA)封裝構造’由於在該可撓性薄片基 板之晶片設置區域之中央設有至少一虛墊使得該晶片設置 區域之中央具有較佳之剛性（rigidity)以抵抗外力，藉此 改善晶片破裂或層裂的問題《此外，該虛墊表面之氧化銅 覆蓋層係呈現粗糙狀，所以在氧化銅覆蓋層/不導電膠層 介面之粘著機構除了化學鍵結外而尚有機械互鎖機構，所- 以可以增加虛墊與不導電膠層間之附著力以降低剝離之機 率。P99-052.ptc Page 6 434762 __Case No. 88117906 _ Year Month Day Amendment __. V. Description of the Invention (3) (cupric oxide) The cover layer is used to increase the adhesion between the cupric oxide and the non-conductive adhesive layer. A flexible substrate ball grid array package structure according to a preferred embodiment of the present invention mainly includes a semiconductor wafer fixed to a flexible thin-film substrate with a non-conductive adhesive layer. The flexible sheet substrate includes a flexible sheet having a wafer setting area for carrying the semiconductor wafer. A plurality of chip connection pads, a plurality of solder ball pads, and at least one dummy pad are disposed on an upper surface of the flexible sheet, and are located substantially at the center of the chip installation area. The surface of the virtual plutonium is better. It has a copper oxide (CUpric oxide) cover layer to increase its adhesion to the non-conductive adhesive layer. The plurality of wafer connection pads are arranged around the wafer setting area for electrically connecting to the semiconductor wafer. The plurality of solder ball pads surround the dummy pad and are electrically connected to the corresponding chip connection pads. The flexible sheet has a plurality of holes corresponding to the plurality of solder ball pads, so that each of the solder ball pads is partially exposed in the holes for providing a solder ball. The upper surface of the semiconductor wafer and the flexible sheet substrate is covered with a colloid. ^ The flexible substrate ball grid array (f 1 ex ib 1 e substrate based BGA) package structure according to the present invention, 'because at least one dummy pad is provided in the center of the wafer setting area of the flexible sheet substrate, the wafer is set. The center of the area has better rigidity to resist external forces, thereby improving the problem of chip cracking or delamination. In addition, the copper oxide coating on the surface of the dummy pad is rough, so the copper oxide coating / non-conductive In addition to the chemical bonding, the adhesive mechanism of the adhesive layer interface has a mechanical interlocking mechanism, so the adhesion between the dummy pad and the non-conductive adhesive layer can be increased to reduce the probability of peeling.
P99-052.ptc 第7頁 434762 _案號88117906_年月日 修正_ 五、發明說明（4) 本發明另提供一種製造該可撓性薄片基板之方法，其包 含下列步驟：（A)提供一可撓性薄片，具有上表面及下表 面，該可撓性薄片之上表面具有一晶片設置區域用以承載 一半導體晶片；（B)在該可撓性薄片形成複數個孔； (C)層壓（laminating) —金屬層於該可挽性薄片之上表 面；（D)蝕刻該金屬層而形成複數個錫球銲墊、晶片連 接整、導電線路（conductive traces)以及至少一虛塾， 其中該錫球銲墊係對應於該複數個洞設置且經由該導電線 路而電性連接至該晶片連接墊，並且該虛塾（dummy pad) 係大致位於該晶片設置區域之中央。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵’下文特舉本發明較佳實施例，並配合所附圖示， 作詳細說明如下。 【發明說明】 第三圖係為根據本發明一較佳實施例之可撓性基板格 陣列封裝構造200，其主要係包含一半導體晶片210利^^- 不導電膠層（例如環氧樹脂）2 1 2固著於一可撓性薄片基— 板220之上表面。 請參照第三圖以及第七圖，該可撓性薄片基板22 0主要 係包含一可撓性薄片22〇a，其具有一晶片設置區域220 b用 以承載該半導體晶片21〇。該可撓性薄片22〇a之上表面設 有複數個晶片連接墊220 c經由設在該可撓性薄片22 0a上表 面的導電線路（conductive trace) 220e電性連接至相對 應之錫球銲墊22 〇d。該複數個晶片連接墊220c係位於該晶. # # £區域2 2之周圍並且經由複數條連接線（bondingP99-052.ptc Page 7 434762 _Case No. 88117906_ Year, Month, and Day Amendment_ V. Description of the Invention (4) The present invention further provides a method for manufacturing the flexible sheet substrate, which includes the following steps: (A) Provide A flexible sheet having an upper surface and a lower surface, the upper surface of the flexible sheet having a wafer setting area for carrying a semiconductor wafer; (B) forming a plurality of holes in the flexible sheet; (C) Laminating-a metal layer on the top surface of the releasable sheet; (D) etching the metal layer to form a plurality of solder ball pads, chip connections, conductive traces, and at least one dummy, Wherein, the solder ball bonding pad is disposed corresponding to the plurality of holes and is electrically connected to the chip connection pad via the conductive line, and the dummy pad is located approximately in the center of the chip installation area. In order to make the above and other objects, features, and advantages of the present invention more apparent, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. [Explanation of the Invention] The third diagram is a flexible substrate grid array package structure 200 according to a preferred embodiment of the present invention, which mainly includes a semiconductor wafer 210 and a non-conductive adhesive layer (such as epoxy resin). 2 1 2 is fixed on the upper surface of a flexible sheet base-plate 220. Referring to the third and seventh figures, the flexible sheet substrate 22 0 mainly includes a flexible sheet 22a, which has a wafer setting area 220b for carrying the semiconductor wafer 21o. A plurality of wafer connection pads 220c are provided on the upper surface of the flexible sheet 22a, and are electrically connected to corresponding solder balls via a conductive trace 220e provided on the upper surface of the flexible sheet 22a. Pad 22 〇d. The plurality of chip connection pads 220c are located on the crystal. # # £ Area 2 2 and via a plurality of connection lines (bonding
P99-052.ptc 第8頁 434762 _案號88117906_年月 日 傣_____ 五、發明說明（5) wires) 230電性連接至該半導體晶片210。該可撓性薄片 220a具有複數個孔對應於該複數個錫球銲墊220d設置，使 得該每一個錫球銲墊2 2 0 d至少有部份裸露於該孔用以設置 —錫球222。該半導體晶片210以及該可撓性薄片基板2 20 . 之上表面係包覆於一封膠體240。該複數個錫球係形成於 該可撓性薄片基板220之下表面用以與外界電性溝通。 本發明之特徵在於該可撓性薄片基板220設有至少一虛 墊（dummy pad)220f於該可撓性薄片之上表面並且大致位 於該晶片設置區域之中央。該虛墊2 2 0 f較佳係形成一不連 績之樣式並且大致遍佈該晶片設置區域之中央（如第七、 八、九圖所示），藉此不會妨礙該不導電膠之流動並且可 以得到最佳加強效果。可以理解的是，根據本發明之虛墊 220ί之數目及形狀並不受限於第七、八、九圖所示之實施 例°根據本發明之虛墊2 2 0 f可以是長條形、橢圓形或^形 (如第七、八、九圖所示），只要其不會妨礙該不導 之流動並且可以使該可撓性薄片基板之晶片設置區域^'中 央得到最佳加強效果即可。 第四圖至第六圖係用以說明製造根據本發明之可撓性薄 片基板之方法。 請參照第四圖，複數個孔形成在該可撓性薄片22 〇a上， 其可利用S知的衝孔技術（pUnching technique)或雷射鑽 孔（laser dr 1 1 1 ing)。該複數個孔之位置係對應於該封裝 構造20 0底部之複數個錫球銲墊22〇d (參照第三圖）。 該可挽性薄片22 0a，其較佳係以聚醯亞胺（p〇iyimide) 製成，使其完全符合各項信賴性測試。P99-052.ptc Page 8 434762 _Case No. 88117906_Year Date _____ V. Description of the invention (5) wires) 230 is electrically connected to the semiconductor chip 210. The flexible sheet 220a has a plurality of holes corresponding to the plurality of solder ball pads 220d, so that each of the solder ball pads 2 2 0 d is at least partially exposed in the hole for providing the solder balls 222. The upper surface of the semiconductor wafer 210 and the flexible sheet substrate 2 20. Is covered with a piece of colloid 240. The plurality of solder balls are formed on the lower surface of the flexible sheet substrate 220 to electrically communicate with the outside. The present invention is characterized in that the flexible sheet substrate 220 is provided with at least one dummy pad 220f on the upper surface of the flexible sheet and is located approximately at the center of the wafer setting area. The dummy pad 2 2 0 f is preferably formed in a non-continuous pattern and is approximately distributed in the center of the chip setting area (as shown in Figures 7, 8, and 9), thereby not hindering the flow of the non-conductive adhesive. And can get the best strengthening effect. It can be understood that the number and shape of the virtual pads 220 ′ according to the present invention are not limited to the embodiments shown in the seventh, eighth and ninth figures. The virtual pads 2 2 0 f according to the present invention may be long, Elliptical or ^ -shaped (as shown in Figures 7, 8, and 9), as long as it does not hinder the non-conductive flow and can provide the best reinforcement effect at the center of the wafer setting area of the flexible sheet substrate. can. The fourth to sixth figures are for explaining a method of manufacturing a flexible thin substrate according to the present invention. Referring to the fourth figure, a plurality of holes are formed in the flexible sheet 22a, which can use a pUnching technique or laser dr 1 1 1 ing. The positions of the plurality of holes correspond to the plurality of solder ball pads 22 d at the bottom of the package structure 200 (refer to the third figure). The reversible sheet 22 0a is preferably made of polyimide, so that it completely meets various reliability tests.
434762 _塞號88117906_年月日 #正___ 五、發明說明（6) 請參照第五圖，該金屬層（例如一銅箔2 2 1 )係以習用 之方法（例如熱壓合法）層壓（1 a m i n a t i n g)於該可撓性薄 片220a上。 請參照第六圖，該複數個晶片連接墊22〇c、複數個錫球 銲墊220d、導電線路2 2 0 e (未示於第六圖中）以及虛墊 2 2 0 f 係以微影（photolithography)以及蝕刻（etching)的 方式形成’其包含下列步驟：（A)塗佈一光阻層於該金屬 層之表面上，（B)以微影進行圖案轉移（參照第七圖）， (C)利用姓刻將金屬層未被光阻保護的部分除去而形成相 對應之晶片連接塾220c、錫球銲整220d、導電線路220e以 及虛塾220f ’（D)除去該光阻層。該複數個晶片連接墊 220c、複數個錫球銲墊2 20d以及導電線路220e較佳具有一 金屬覆蓋層形成在其沒有可撓性薄片22 〇a覆蓋之表面。該 金屬覆蓋層可以習用之電鍍方法形成於其上，其較佳先鍍 上一層錄（Ni) ’再鑛上一層金（Au)。由於該金屬覆 塗覆在用以電性連接至一半導體晶片的複數個連接 因此其必須選用與習用連接線（b〇nding wire)材料結人力 及導電性較佳者。 u ΰ 該虛墊220 f之表面較佳具有一氧化銅覆蓋層用以增加其 與該不導電膠層2 1 2間之附著力。該虛墊2 2 0 f之氧化9銅覆 蓋層較佳以陽極氧化（an〇dic oxidation)法塗佈：（A)將 該可撓性薄片基板表面不要有氧化銅覆蓋層之區域（例如 該複數個晶片連接墊2 2 0 c、複數個錫球銲墊220 d以及導電 線路22 0e )以膠帶黏貼保護；（B)將已貼上保護膠 挽性薄片基板竹主眼杯：4 Α κι .jt / , ^ .434762 _ 塞 号 88117906_ 年月 日 # 正 ___ V. Description of the invention (6) Please refer to the fifth figure. The metal layer (for example, a copper foil 2 2 1) is a layer using a conventional method (for example, hot pressing). 1 aminating on the flexible sheet 220a. Please refer to the sixth figure. The plurality of chip connection pads 22oc, the plurality of solder ball pads 220d, the conductive circuit 2 2 0 e (not shown in the sixth figure), and the dummy pad 2 2 0 f are lithography. (Photolithography) and etching (formation) are formed, which includes the following steps: (A) coating a photoresist layer on the surface of the metal layer, (B) pattern transfer by lithography (refer to the seventh figure), (C) Remove the photoresist-protected part of the metal layer using the last name to form the corresponding wafer connection 塾 220c, solder ball 220d, conductive line 220e, and virtual 塾 220f '(D) to remove the photoresist layer. The plurality of wafer connection pads 220c, the plurality of solder ball pads 2 20d, and the conductive circuit 220e preferably have a metal coating layer formed on a surface thereof not covered by the flexible sheet 22a. The metal cover layer can be formed thereon by a conventional electroplating method, and it is preferably plated with a layer of (Ni) 'and then a layer of gold (Au). Since the metal coating is applied to a plurality of connections for electrically connecting to a semiconductor wafer, it must be selected with a bond wire material that has a better labor and conductivity. u 较佳 The surface of the dummy pad 220 f preferably has a copper oxide covering layer to increase the adhesion between the dummy pad 220 f and the non-conductive adhesive layer 2 12. The 9-oxide copper cover layer of the dummy pad 2 2 0 f is preferably coated by anodic oxidation: (A) an area where the surface of the flexible sheet substrate does not have a copper oxide cover layer (for example, the The plurality of wafer connection pads 2 2 0 c, the plurality of solder ball pads 220 d, and the conductive circuit 22 0e) are protected by adhesive tape; (B) the protective main body cup with bamboo sheet is attached: 4 Α κι. jt /, ^.
43478¾ __案號88117906_年月 日 搞· i_ 五、發明說明（7) 解液）中加以電解，藉此形成一氧化銅覆蓋層於該可撓性 薄片基板沒有膠帶保護之表面。該氧化銅覆蓋層的主要結 晶構造為高密度群集之黑色、典狀結晶。因此，該氧化銅覆_ 蓋層之表面係呈現黑色粗糙狀。該虛墊22〇f之氧化銅覆蓋， 層亦可以化學氧化（chemical oxidation)法塗佈：步驟 (A)同前；（B’）將已貼上保護膠帶之可撓性薄片基板浸於 一化學氧化液（例如3%氣化鈉+ 1%氫氧化鈉+ 1%磷酸鈉） 中，加熱至8 5 °C。 根據本發明之可撓性基板球格陣列（Π ex i b 1 e substrate based BGA)封裝構造，由於在該可撓性薄片基 板之晶片設置區域之中央設有至少一虛墊使得該晶片設置 區域之中央具有較佳之剛性（r i g i d i t y)以抵抗外力。此 外’由於根據本發明之虛墊係大致佈滿該可撓性薄片基板 之晶片設置區域之中央，使得該晶片設置區域之中央之 膨脹係數與其他部份大致相當，藉此減低因熱膨脹係數；^ 一致（CTE mismatch)所產生之應力。因此，根據本發明之 可撓性薄片基板可有效改善晶片破裂或層裂的問題。 根據本發明之另一方面，該虛墊表面係具有一氧化銅覆 蓋層。由於該氧化鋼覆蓋層係由高密度群集之黑色針狀結 a曰組成’所以當该封裝構造進行黏晶（die attaching)製 程時’該黑色針狀結晶之間的縫隙係可供該不導電膠（例 如環氧樹脂）填入’藉此當該不導電膠固化後可以提供機 械互鎖（mechanical interlock)之功能而增加在氧化銅覆‘ 蓋層/不導電膠層介面的附著力，因而降低該可撓性薄片 基板與木導電膠層間層裂之機率。43478¾ __Case No. 88117906_ Month, Day, and i_ V. Invention Description (7) Solution) Electrolysis is performed to form a copper oxide coating on the surface of the flexible sheet substrate without tape protection. The main crystal structure of the copper oxide coating is a black, classic crystal with high density clusters. Therefore, the surface of the copper oxide coating is black and rough. The dummy pad 22f is covered with copper oxide, and the layer can also be coated by chemical oxidation: step (A) is the same as before; (B ') the flexible sheet substrate with the protective tape is immersed in a In a chemical oxidizing solution (eg 3% sodium gasification + 1% sodium hydroxide + 1% sodium phosphate), heat to 8 5 ° C. According to the flexible substrate ball grid array (Π ex ib 1 e substrate based BGA) package structure of the present invention, since at least one dummy pad is provided in the center of the wafer setting area of the flexible sheet substrate, the The center has better rigidity to resist external forces. In addition, 'the virtual pad according to the present invention substantially covers the center of the wafer setting area of the flexible sheet substrate, so that the expansion coefficient of the center of the wafer setting area is approximately equal to other parts, thereby reducing the thermal expansion coefficient; ^ Stress caused by CTE mismatch. Therefore, the flexible sheet substrate according to the present invention can effectively improve the problem of wafer cracking or delamination. According to another aspect of the present invention, the dummy pad surface has a copper oxide covering layer. Since the oxide steel cover layer is composed of high-density black needle-like knots, so when the package structure is subjected to a die attaching process, the gap between the black needle-like crystals is available for the non-conductive Glue (such as epoxy resin) is filled with 'This can provide a mechanical interlock function when the non-conductive glue is cured and increase the adhesion on the copper oxide coating' cover / non-conductive glue layer interface, so Reduce the probability of delamination between the flexible sheet substrate and the wood conductive adhesive layer.
P99-052.ptc 第11頁 434762 _案號88117906_年月曰 條正_ 五、發明說明（8) 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。P99-052.ptc Page 11 434762 _ Case No. 88117906_ Years and Months of the Year _ V. Description of the Invention (8) Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention, any familiarity Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.
P99-052.ptc 第12頁 434762P99-052.ptc Page 12 434762
e -—案號 8?ni7Qnft_年月日_修正— 圖式簡單說明 【圖示說明】 第1圖：習用可撓性基板球格陣列（f 1 ex i b 1 substrate based BGA)封裝構造之剖面圖； 第2圖：使用於第1圖之可撓性基板球格陣列 、 之可撓性薄片基板之上視圖； 、構造 第3圖：根據本發明一較佳實施例之可撓性基板球袼陣 列（flexible substrate based BGA)封裝構造之剖面圖； 第4圖至第6囷：其揭示一種根據本發明之製造一可 性薄片基板之方法； 第7圊.根據本發明第一較佳實施例之可撓性薄片基 之上視圖； 第8圖：根據本發明第二較佳實施例之可撓性薄片基板 之上視圖；及 第9圖.根據本發明第三較佳實施例之可撓性薄片基板 之上視圓。e -—Case No. 8? ni7Qnft_ 年月 日 _ 修 —— Brief description of the drawings [Illustration] Figure 1: Cross-section of a conventional flexible substrate ball grid array (f 1 ex ib 1 substrate based BGA) package structure Figure 2: Figure: Top view of flexible substrate ball grid array used in Figure 1, flexible sheet substrate; Figure 3: Flexible substrate ball according to a preferred embodiment of the present invention袼 A sectional view of a flexible substrate based BGA package structure; Figures 4 to 6 囷: It discloses a method for manufacturing a flexible thin substrate according to the present invention; Section 7 第. The first preferred implementation according to the present invention Top view of a flexible sheet substrate according to an example; FIG. 8: top view of a flexible sheet substrate according to a second preferred embodiment of the present invention; and FIG. 9 according to a third preferred embodiment of the present invention Seen round on the flexible sheet substrate.
【圖號說明】 10 0可撓性基板球格陣列封裝構造 no薄片基板110a晶片連接墊 11 0 c 孔 11 Ob錫球銲墊 110 120140160 200210 半導體晶片122不導電膠層130 踢球 15 G封膠體 晶片設置區域 可挽性基板球格陣列封裝造 m日日V 212不導電膠層220 導電線路 連接線[Illustration of drawing number] 10 0 flexible substrate ball grid array package structure no sheet substrate 110a wafer connection pad 11 0 c hole 11 Ob solder ball pad 110 120 140 160 200210 semiconductor wafer 122 non-conductive adhesive layer 130 kick ball 15 G sealing gel Chip set area, reversible substrate, ball grid array package, m-day V 212, non-conductive adhesive layer 220, conductive line connecting line
薄片基板Sheet substrate
434762 案號 88117906 Λ：_Κ. 曰 修正 圖式簡單說明 220a可撓性薄片 220c晶片連接墊 虛墊 230 連接線 2 2 0b晶片設置區域 2 2 0d 錫球銲墊 220 221 銅猪 222 24 0 封膠體 導電線路 錫球 n434762 Case No. 88117906 Λ: _K. Brief description of correction diagram 220a Flexible sheet 220c Chip connection pad dummy pad 230 Connection line 2 2 0b Chip setting area 2 2 0d Solder ball pad 220 221 Copper pig 222 24 0 Sealing gel Conductive circuit solder ball n
P99-052.ptc 第14頁P99-052.ptc Page 14
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW88117906A TW434762B (en) | 1999-10-14 | 1999-10-14 | Flexible substrate based ball grid array package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW88117906A TW434762B (en) | 1999-10-14 | 1999-10-14 | Flexible substrate based ball grid array package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW434762B true TW434762B (en) | 2001-05-16 |
Family
ID=21642644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW88117906A TW434762B (en) | 1999-10-14 | 1999-10-14 | Flexible substrate based ball grid array package structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW434762B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106684003A (en) * | 2016-12-29 | 2017-05-17 | 清华大学 | Fan-out type packaging structure and manufacture method thereof |
-
1999
- 1999-10-14 TW TW88117906A patent/TW434762B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106684003A (en) * | 2016-12-29 | 2017-05-17 | 清华大学 | Fan-out type packaging structure and manufacture method thereof |
| CN106684003B (en) * | 2016-12-29 | 2019-03-29 | 清华大学 | Fan-out package structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5739588A (en) | Semiconductor device | |
| US6380002B2 (en) | Method for fabricating a flexible substrate based ball grid array (BGA) package | |
| US20070013038A1 (en) | Semiconductor package having pre-plated leads and method of manufacturing the same | |
| JP2001520460A (en) | Method and structure for improving heat dissipation characteristics of package for microelectronic device | |
| TWI226092B (en) | Method for making a circuit device | |
| JPH10340973A (en) | Metal base semiconductor circuit board | |
| TW200532823A (en) | Circuit device | |
| JP4070470B2 (en) | Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device | |
| JP2501953B2 (en) | Semiconductor device | |
| TW434762B (en) | Flexible substrate based ball grid array package structure | |
| JPH0445985B2 (en) | ||
| JP4045985B2 (en) | Resin-sealed electronic device | |
| JP2740977B2 (en) | Semiconductor device | |
| JPH0846084A (en) | Surface mounting type semiconductor package, method of manufacture and semiconductor device | |
| JP3789688B2 (en) | Hybrid integrated circuit device | |
| JPS61150253A (en) | Semiconductor lead frame | |
| JPH11224912A (en) | Chip carrier substrate for semiconductor package and semiconductor package | |
| TWI299886B (en) | Method for Producing the Wiring Board | |
| TWI235473B (en) | Ball grid array package structure, heat slug structure, and laser mark rework method | |
| TW200945527A (en) | Package structure | |
| TWI401777B (en) | Window-type semiconductor stacked structure and the forming method thereof | |
| WO1999034435A1 (en) | Circuit board, manufacture thereof, and electronic device using circuit board | |
| JP2970595B2 (en) | BGA type semiconductor device | |
| JP3599142B2 (en) | Manufacturing method of semiconductor package | |
| JPH011262A (en) | Electronic device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MK4A | Expiration of patent term of an invention patent |