TW421836B - Package structure of semiconductor chip on substrate - Google Patents

Package structure of semiconductor chip on substrate Download PDF

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Publication number
TW421836B
TW421836B TW88113139A TW88113139A TW421836B TW 421836 B TW421836 B TW 421836B TW 88113139 A TW88113139 A TW 88113139A TW 88113139 A TW88113139 A TW 88113139A TW 421836 B TW421836 B TW 421836B
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Taiwan
Prior art keywords
substrate
production
dielectric layer
wafer
solder ball
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Application number
TW88113139A
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Chinese (zh)
Inventor
Mark Chung
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Chipmos Technologies Inc
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Priority to TW88113139A priority Critical patent/TW421836B/en
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Publication of TW421836B publication Critical patent/TW421836B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

There is disclosed a package structure of semiconductor chip. The substrate has a dielectric layer. The top surface of the dielectric layer has a plurality of chip connection pads for electrically connecting to the semiconductor chip. A plurality of chip connection pads are electrically connected to a plurality of solder ball pads on the bottom surface of the dielectric layer. A protection layer is arranged on the surface of the substrate, wherein the plurality of the solder ball pads and the top surface of the dielectric layer are exposed out of the protection layer. The surface of the substrate, arranged with the semiconductor chip, and the semiconductor chip is covered by an encapsulation body, and each solder ball pad has a solder ball.

Description

^21836 五、發明說明（1) 發明領域： 本發明係有關於一種半導體晶片封裝構造，特別有關於· 一種在基板上的半導體晶片封裝構造（substrate-based packaged semiconductor chip)。 先前技術： 隨著更輕更複雜半導體晶片需求的日趨強烈，晶片的速 度及複雜性相對越來越高，而越複雜之晶片其所需之電性 連接也越多，於是半導體晶片封裝業界發展出球格陣列 (Ball Grid array(BGA))封裝技術，以符合其需求。 第一圖係為一習知的球格陣列封裝構造1 0 0 ，其包含一 晶片101設於一基板102。該基板102具有一介電層l〇2a * 該晶片1 0 1表面之晶片銲墊（未示於圖中）係以導線 (bonding wires)103連接至設於該介電層102a之上表面 102b的導電線路（conductive traces)102c或導電區域 (未示於囷中）。該介電層l〇2a之下表面102d設有複數個 錫球銲墊102f電性連接至該導電線路102c或導電區域。該 每一錫球銲墊1 〇 2 f係設有一錫球1 0 4用以與外界電性溝 通。 一封膠體1 0 5包覆該晶片1 01、導線1 0 3以及該基板1 0 2之 —部份（包括大部分的導電線路102b及導電區域）。一般 而言，該基板102之表面設有一保護層107，其中該導電線 路102b用以供導線（bonding Wires)103連接的區域以及該 複數個錫球銲墊I 〇 2 f係裸露於該保護層1 〇 7 > 該基板102之介電層1〇2 —般係以玻璃纖維強化 iHii mm^ 21836 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor wafer package structure, and more particularly, to a substrate-based packaged semiconductor chip on a substrate. Previous technology: With the increasing demand for lighter and more complex semiconductor wafers, the speed and complexity of wafers are relatively higher and higher, and the more complicated wafers require more electrical connections, so the semiconductor wafer packaging industry has developed Ball Grid Array (BGA) packaging technology to meet its needs. The first diagram is a conventional ball grid array package structure 100, which includes a wafer 101 disposed on a substrate 102. The substrate 102 has a dielectric layer 102a. The wafer pads (not shown) on the surface of the wafer 101 are connected with bonding wires 103 to a surface 102b provided on the dielectric layer 102a. Conductive traces 102c or conductive areas (not shown in the figure). A plurality of solder ball pads 102f on the lower surface 102d of the dielectric layer 102a are electrically connected to the conductive line 102c or the conductive area. Each solder ball pad 102f is provided with a solder ball 104 for electrical communication with the outside. A piece of colloid 105 covers the wafer 101, the wires 103, and a part of the substrate 102 (including most of the conductive lines 102b and conductive areas). Generally speaking, a protective layer 107 is provided on the surface of the substrate 102, wherein the conductive line 102b is used for the area where the bonding wires 103 are connected, and the plurality of solder ball pads 〇2 f are exposed on the protective layer. 1 〇7 > The dielectric layer 102 of the substrate 102 is generally reinforced with glass fiber iHii mm

第4頁 ^21836 五、發明說明（2) BT(bismaleimide-triazine)樹脂或FR-4玻璃纖維強化環 氧樹脂（fiberglass reinforced epoxy resin)製成，然. 而由於其表面必須塗佈一保護層以防止水分進入，因此增 加其厚度。 該基板102之介電層1〇2亦可以聚醢亞胺（polyimide)製 成，由於其不需以玻璃纖維增加製得基板之剛性 (rigidity)，所以其表面不須塗佈一保護層，因此其製得 之基板厚度較薄，然而其缺點為成本高。 —般而言’在基板上的半導體晶片封裝構造，例如該習 知的球格陣列封裝構造100，其基板佔其全部封裝成本百 分之六十，因此若可以採用價格低之基板，將可大幅幾少 全部之封裝成本。 此外，封裝構造最怕封膠體與基板間的吸附力不足 (adhesion fail)，若未及時發現繼續大量生產將造成很 大的損失。事實上，習知的球格陣列封裝構造在壓力鍋試 驗（pressure cook test, PCT)時極易產生射膠艘剝落 (peeling)的現象。由於封膠體與基板表面之保護層的接 觸面大致上相當平坦，因此封勝體與保護層間的粘著機構 (bonding mechanism)幾乎僅為化學鍵結而沒有機械互鎖 (mechanic interlock)的機構，所以在高溫高壓高濕的環 境下（例如壓力鋼試驗），封膠體與保護層間的介面易受 水之侵Ί4而水解形成巨觀上封膠體與保護層胡之脫層 (delamination) ° 發明概要：Page 4 ^ 21836 V. Description of the invention (2) BT (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin (fiberglass reinforced epoxy resin), but because its surface must be coated with a protective layer To prevent moisture from entering, therefore increase its thickness. The dielectric layer 102 of the substrate 102 can also be made of polyimide. Since it does not need to increase the rigidity of the substrate made of glass fiber, the surface does not need to be coated with a protective layer. Therefore, the thickness of the substrate is relatively thin, but the disadvantage is high cost. -Generally speaking, a semiconductor wafer package structure on a substrate, such as the conventional ball grid array package structure 100, has a substrate that accounts for 60% of its total packaging cost. Therefore, if a low-priced substrate can be used, Significantly less overall packaging costs. In addition, the package structure is most afraid of adhesion failure between the sealing compound and the substrate. If it is not found in time, continued mass production will cause great losses. In fact, the conventional ball grid array package structure is extremely susceptible to peeling during pressure cook test (PCT). Since the contact surface between the sealant and the protective layer on the substrate surface is substantially flat, the bonding mechanism between the sealant and the protective layer is almost only a chemical bond without a mechanism of mechanical interlock, so Under high-temperature, high-pressure, high-humidity environments (such as pressure steel tests), the interface between the sealant and the protective layer is susceptible to invasion by water4 and hydrolyzed to form a delamination of the macroscopic upper sealant and the protective layer.

第5頁 421836 五、發明說明（3) 本發明之主要目的係提供一種在基板上的半導體晶片封 裝構造，其中該半導體晶片係為一封膠體包覆並且該基板 只有一面有保護層覆蓋，藉此減少該基板之厚度並且增加 該封膠體與基板間之附著力。 根據本發明之在基板上的半導體晶片封裝構造係以一基 板承載一半導體晶片。該基板係包含一介電層。該介電層 之上表面設有複數個晶片連接墊及導電線路。該介電層之 下表面設有複數個錫球銲墊，且該每一錫球銲墊係分別電 性連接至相對應的晶片連接墊或導電線路。該每一錫球銲 墊係設有一錫球，用以與外界電性溝通。該晶片上之晶片 銲墊係電性連接至該介電層上之晶片連接墊或導電線路。 該基板之表面設有一保護層，其中該複數個錫球銲墊以及 該介電層之上表面係裸露於該保護層。該半導體晶片以及 該基板設有該半導體晶片之表面係為一封膠體包覆。 根據本發明之在基板上的半導體晶片封裝構造，其介電 層之上表面係裸露於該保護層，所以該保護層僅覆蓋該基 板之一面，藉此該基板之厚度可以降低。由於該介電層表 面沒有形成導電線路或導電區域的部分係呈現粗糙狀，所 以在該介電層表面/封膠體介面之粘著機構除了化學鍵結 外而尚有機械互鎖機構，由於機械互鎖機構具有抗化學溶 劑（例如水）之特性，所以可以使根據本發明之在基板上 的半導體晶片封裝構造在高溫高壓高濕的環境下（例如壓 力鍋試驗）仍有極佳之可靠性。 圖示說明： II 1Η 42183 6 五、發明說明（4) 為/了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵，下文特舉本發明較佳實施例，並配合所附圖示’ 作詳細說明如下。 第1圖：習用球格陣列封裝構造之剖面围； 第2圖：本發明第一較佳實施例之剖面圊； 第3圖：本發明1第二較佳實施例之剖面圊；及 第4圖：根據本發明實施例之設在一基板條上的複數個 基板之上視圖6 圖號說明： 100 球 格 陣列 封 裝 構造 101 晶 片 102 基 板 102a 介 電 層 102b 上 表 面 102c 導電線路 102d 下 表 面 102f 錯 球 銲墊 103 導 線 104 錫 球 105 封 膠 體 107 保 護 層 200 球 格 陣列 封 裝 構造 201 晶 片 202 基 板 2 0 2a 介 電 層 20 2b 上 表 面 202c 晶 片 連接墊 2 0 2d 下 表 面 203 導 線 204 錫 球 205 封 膠 體 207 保 護 層 301 晶 片 302 基 板 303 膠 捲 式自 動 黏 著膠帶 400 基 板 條 401 基 板 402 基 板 403 基 板 404 基 板 405 基 板 406 基 板 407 基 板 408 裁 切 孔Page 5 421836 V. Description of the invention (3) The main object of the present invention is to provide a semiconductor wafer package structure on a substrate, wherein the semiconductor wafer is covered with a colloid and only one side of the substrate is covered with a protective layer. This reduces the thickness of the substrate and increases the adhesion between the sealant and the substrate. A semiconductor wafer package structure on a substrate according to the present invention carries a semiconductor wafer on a substrate. The substrate includes a dielectric layer. The upper surface of the dielectric layer is provided with a plurality of chip connection pads and conductive lines. A plurality of solder ball pads are provided on the lower surface of the dielectric layer, and each solder ball pad is electrically connected to a corresponding chip connection pad or a conductive line, respectively. Each solder ball pad is provided with a solder ball for electrically communicating with the outside world. The wafer pads on the wafer are electrically connected to the wafer connection pads or conductive lines on the dielectric layer. A protective layer is provided on the surface of the substrate, wherein the plurality of solder ball pads and the upper surface of the dielectric layer are exposed on the protective layer. The semiconductor wafer and the surface of the substrate provided with the semiconductor wafer are covered with a colloid. According to the semiconductor wafer package structure on a substrate of the present invention, the upper surface of the dielectric layer is exposed to the protective layer, so the protective layer covers only one side of the substrate, thereby reducing the thickness of the substrate. Since the part of the surface of the dielectric layer where no conductive lines or conductive areas are formed is rough, the adhesion mechanism on the surface of the dielectric layer / sealing gel interface has a mechanical interlocking mechanism in addition to chemical bonding. The lock mechanism is resistant to chemical solvents (such as water), so that the semiconductor chip package structure on a substrate according to the present invention can still have excellent reliability under high temperature, high pressure, and high humidity environments (such as a pressure cooker test). Illustrations: II 1Η 42183 6 V. Description of the invention (4) In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention with the accompanying The illustration 'is explained in detail below. Figure 1: Cross section of a conventional ball grid array package structure; Figure 2: Section 圊 of a first preferred embodiment of the present invention; Figure 3: Section 圊 of a second preferred embodiment of the present invention; and Figure 4 Figure: Top view of a plurality of substrates provided on a substrate strip according to an embodiment of the present invention 6 Explanation of drawing numbers: 100 ball grid array package structure 101 wafer 102 substrate 102a dielectric layer 102b upper surface 102c conductive line 102d lower surface 102f Wrong pad 103 lead 104 solder ball 105 sealant 107 protective layer 200 ball grid array package structure 201 wafer 202 substrate 2 0 2a dielectric layer 20 2b upper surface 202c wafer connection pad 2 0 2d lower surface 203 wire 204 solder ball 205 Sealant 207 Protective layer 301 Wafer 302 Substrate 303 Film-type automatic adhesive tape 400 Substrate strip 401 Substrate 402 Substrate 403 Substrate 404 Substrate 405 Substrate 406 Substrate 407 Substrate 408 Cutting hole

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五、發明説明（5) 409 對正孔 416 槽縫 發明説明： 第二圖係為根據本發明第一較佳實施例之一球格陣列封 震構造200 ，其包含一晶片201設於一基板2〇2。該曰曰片201 較佳以不導電膠例如環氧樹脂（epoxy )固設於該基板2〇2 ° 該基板202具有一介電層202a。該晶片201表面之晶片銲墊 (未示於圖中）係以導線（bonding wires)203連接至設於 該介電層202a之上表面202b的晶片連接墊2〇2c。該介電層 202a之下表面202d設有複數個錫球銲墊2〇2f電性連接έ晶 片連接整>202c或導.電線路。該每一踢球銲塾2〇2f係、有一 錫球2 04用以與外界電性溝通。 ” ” 該基板2 0 2之表面設有一保護層2 0 7 ’其中該複數個錫球 鲜塾202f以及該介電廣202a之上表面2〇2b (包括兮·複數個 晶片連接塾202c及導電線路）係裸露於該保護層，亦即只 有該基板202之下表面202d係為該保镬得2〇7覆蓋—封膠 體205包覆該晶片201以及該基板202之上| 工畏面202b (包祜 該複數個晶片連接墊2 0 2c以及導電線路）。 可以理解的是，該晶片亦可以利用膠捲式自動 (Tape Automated Bonding，TAB)膠帶電 請參照第三圊，晶片3 0 1表面之晶片銲塾（) 係以膠捲式自動黏著膠帶303連接至一基拉扣 3〇2之構造與第二圖之基板20 2相同。“30 2。該基板 :夕卜2晶片亦可以利用覆晶⑴ip chip)的方式電性 迷接生暴板。5. Description of the invention (5) 409 Alignment hole 416 Slot invention description: The second figure is a ball grid array seismic isolation structure 200 according to one of the first preferred embodiments of the present invention, which includes a wafer 201 provided on a substrate 2〇2. The sheet 201 is preferably fixed on the substrate 202 with a non-conductive adhesive such as epoxy, and the substrate 202 has a dielectric layer 202a. The wafer pads (not shown) on the surface of the wafer 201 are connected to the wafer connection pads 202c provided on the upper surface 202b of the dielectric layer 202a with bonding wires 203. The lower surface 202d of the dielectric layer 202a is provided with a plurality of solder ball pads 202f electrically connected to the chip connection 202c or conductive lines. Each kick ball is soldered with 202f, and a solder ball 204 is used for electrical communication with the outside world. ”” The surface of the substrate 202 is provided with a protective layer 207 ', wherein the plurality of solder balls 202f and the dielectric 202a upper surface 202b (including Xi · Chip connection 202c and conductive) The circuit) is exposed on the protective layer, that is, only the lower surface 202d of the substrate 202 is covered by the protective film 207—the sealing compound 205 covers the wafer 201 and the substrate 202 | Gongfang 202b ( Including the plurality of chip connection pads 2 0 2c and conductive lines). It can be understood that the wafer can also use Tape Automated Bonding (TAB) tape. Please refer to the third step. The wafer soldering pad () on the surface of the wafer 301 is connected to a wafer-type automatic adhesive tape 303. The structure of the base fastener 302 is the same as the base plate 202 of the second figure. "30 2. The substrate: Xibu 2 chip can also be used to electrically overwhelm the board.

421836 五、發明說明（6) 根據本發明實施例之基板，其製造方法如下： (A )將一經過表面粗糙化的導電金屬層（例如銅箔）以習 用之方法（例如熱壓合法）層壓（laminating)於一介電層 (適合之介電材質如玻璃纖維強化 BT(bismaleimide-triazine)樹脂或FR-4玻璃纖維強化環 氧樹脂（fiberglass reinforced epoxy resin))之兩面。 一般係在介電層成形但尚未固化（curing)前，將經過表面 粗糙化的導電金屬層，熱壓合於介電層之兩面，以増加該 介電層與導電金屬層間之附著力。因此若將該導電^屬^ 除去，則介電層表面將呈現粗糙狀。 (B)在該介電層上形成介層洞（Via)或通孔 (through-hole)，其可以任何習知的方法形成，例如機械 鑽孔或雷射鑽孔。並且以習知的方法如無電極電錢 (electroless plating)在該介層洞或通孔塗覆一層導電 金屬例如銅。 CC)以微影（photo 1 i thography)以及蝕刻（etching)的方 式在該介電層上導電金屬層中形成所要之導電線路或導電 區域°其係先於該基板上導電金屬層之表面上一層光阻， 再以微影進行電路佈局之圖案轉移，並且利用蝕刻將該介 電層上導電金屬層未被光阻保護的部分除去而形成相對應 之導電線路或導電區域’最後再將光阻去除。因此該介電 層表面沒有形成導電線路或導電區域的部分係呈現粗糙 狀。 (D)將一保護層例如一可光顯像的綠漆（ph〇t〇imagable421836 V. Description of the invention (6) The manufacturing method of the substrate according to the embodiment of the present invention is as follows: (A) A conductive metal layer (such as copper foil) with a roughened surface is layered by a conventional method (such as hot pressing) Laminating on both sides of a dielectric layer (suitable dielectric materials such as glass fiber reinforced BT (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin). Generally, before the dielectric layer is formed but not cured, the surface-roughened conductive metal layer is thermally bonded to both sides of the dielectric layer to increase the adhesion between the dielectric layer and the conductive metal layer. Therefore, if the conductive material is removed, the surface of the dielectric layer will appear rough. (B) A via or a through-hole is formed on the dielectric layer, which can be formed by any conventional method, such as mechanical drilling or laser drilling. Also, the vias or vias are coated with a conductive metal such as copper by conventional methods such as electrodeless plating. CC) Photolithography (etching) and etching are used to form the desired conductive lines or conductive areas in the conductive metal layer on the dielectric layer. This is before the surface of the conductive metal layer on the substrate. A layer of photoresist is used to transfer the pattern of the circuit layout by lithography, and the portion of the conductive metal layer on the dielectric layer that is not protected by the photoresist is removed by etching to form a corresponding conductive line or conductive area. Resistance removal. Therefore, the portion of the surface of the dielectric layer where no conductive line or conductive area is formed is rough. (D) a protective layer such as a green paint (ph〇t〇imagable

421836 五、發明說明（7) solder mask)覆蓋於該基板之安裝面（即錫球設置面）， 轉移所要之圖案，然後顯影使得該複數個錫球銲墊未被綠-漆覆蓋。值得注意的是，該基板之半導體晶片設置面係完 全沒有被綠漆覆蓋。 (E) 將一光阻層覆蓋於該基板之半導體晶片設置面，轉 移所要之圖案，然後顯影使得用以電性連接至半導體晶片 的導電線路内端（即前述之晶片連接墊）係未被該光阻$ 覆蓋。 (F) 將與習用連接線（bonding wire)材料結合力佳的金 屬（例如金）以習用之方法電鍍在該導電線路内端未被光 阻層覆蓋的區域’以形成用以電性連接至半導體晶片的複 數個晶片連接墊。 第四囷係為根據本發明實施例之設在一基板條 (strip)400上的複數個基板401-407 (為了簡潔，第四圖 中並未顯示每一基板之細節）。可以理解的是該基板條 400雖只包含七個基板401-407，但使用於本發明之基板條 可包含任何數目之基板，只要其可與封裝製程所用機器相 容即可。該基板條400具有對正孔（alignment hole)409 (為了簡潔，第四圊中只有兩對正孔被標上數字409)， 用以將該基板條400定位在機器上。該基板條4〇〇在每一基 板4 01-407的角落設有裁切孔（punching hole)408 (為了 簡潔，第四圖中只有兩裁切孔被標上數字408)。該基板 條400另包含槽縫416 (為了簡潔，第四囷中只有—槽縫被 標上數字416)，其係用以提供應力釋放，以幫助控制可421836 V. Description of the invention (7) Solder mask) covers the mounting surface of the substrate (ie, the solder ball setting surface), transfers the desired pattern, and develops so that the solder ball pads are not covered by green-lacquer. It is worth noting that the semiconductor wafer setting surface of the substrate is not completely covered with green paint. (E) A photoresist layer is covered on the semiconductor wafer setting surface of the substrate, the desired pattern is transferred, and then developed so that the inner end of the conductive circuit for electrically connecting to the semiconductor wafer (that is, the aforementioned wafer connection pad) is not The photoresistor $ is covered. (F) Electroplating a metal (such as gold) with a good bonding strength with a conventional bonding wire material on the inner end of the conductive line that is not covered by the photoresist layer to form an electrical connection to A plurality of wafer connection pads of a semiconductor wafer. The fourth line is a plurality of substrates 401-407 provided on a substrate strip 400 according to an embodiment of the present invention (for the sake of simplicity, details of each substrate are not shown in the fourth figure). It can be understood that although the substrate strip 400 includes only seven substrates 401-407, the substrate strip used in the present invention may include any number of substrates as long as it is compatible with the machine used in the packaging process. The substrate strip 400 has an alignment hole 409 (for brevity, only two pairs of alignment holes in the fourth frame are labeled with the number 409) for positioning the substrate strip 400 on the machine. The substrate strip 400 is provided with a punching hole 408 at the corner of each of the substrates 4 01-407 (for the sake of simplicity, only two cutting holes are marked with the number 408 in the fourth figure). The substrate strip 400 also includes a slot 416 (for the sake of brevity, only the fourth slot is marked with the number 416), which is used to provide stress relief to help control

421836 五、發明說明（8) 能的基板條400的弯紐（warping)。 根據本發明之在基板上的半導體晶片封裝構造’ 層之上表面係裸露於該保護層，所以該保護層僅 ' 女 基板之安裝面（即錫球設置面），藉此該基板之厚= 降低。由於該基板之介電層之上表面係為一封膠體2 藉此可以防止水分經由裸露於該保護層之介電層上表面入 侵該基板。因此’根據本發明之在基板上的半導體晶片封 裝構造’其基板之介電層可以利用價格較低廉之玻璃織維 強化BT(bismaleimide-triazine)樹脂或fr_4玻璃纖維強 化環氧樹脂（fiberglass reinforced epoxy resin))製 成。 此外，根據本發明之在基板上的半導體晶片封裝構造’ 由於該介電層表面沒有形成導電線路或導電區域的部分係 呈現粗糙狀，所以在該介電層表面/封膠體介面之粘著機 構除了化學鍵結外而尚有機械互鎖機構（因為其介面係至 現粗糙狀），由於機械互鎖機構具有抗化學溶劑（例如水 )之特性，所以在高溫高壓高濕的環境下，該介電層表面 /封膠體介面仍不易受水之侵蝕而水解；因此根據本發明 之在基板上的半導體晶片封裝構造在高溫高壓高濕的環境 下（例如壓力鍋試驗）不易因封膠體剝落而降低其玎靠 性。 雖然本發明已以前述較佳實施例揭示，然其並胙用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範421836 V. Description of the invention (8) Warping of the capable substrate strip 400. According to the present invention, the upper surface of the layer of the semiconductor wafer package structure on the substrate is exposed to the protective layer, so the protective layer is only the mounting surface of the female substrate (that is, the solder ball setting surface), whereby the thickness of the substrate = reduce. Since the upper surface of the dielectric layer of the substrate is a piece of colloid 2, moisture can be prevented from invading the substrate through the upper surface of the dielectric layer exposed on the protective layer. Therefore, the dielectric layer of the substrate of the "semiconductor wafer package structure on a substrate" according to the present invention can use a relatively inexpensive glass-woven reinforced BT (bismaleimide-triazine) resin or fr_4 glass fiber reinforced epoxy. resin)). In addition, according to the semiconductor chip packaging structure on the substrate according to the present invention, since the portion of the surface of the dielectric layer where no conductive lines or conductive areas are formed is rough, the adhesion mechanism on the surface of the dielectric layer / the sealant interface In addition to chemical bonding, there is also a mechanical interlocking mechanism (because its interface is now rough). Because the mechanical interlocking mechanism is resistant to chemical solvents (such as water), under high temperature, high pressure, and high humidity, the interface The surface of the electrical layer / colloid interface is still not easily hydrolyzed and hydrolyzed; therefore, the semiconductor chip package structure on the substrate according to the present invention is not easy to be lowered by the exfoliation of the encapsulant under high temperature, high pressure and high humidity environment (such as pressure cooker test). Reliance. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Protection of invention

421836 五、發明說明（9) 圍當視後附之申請專利範圍所界定者為準。 Ι··1Ι 第12頁421836 V. Description of the invention (9) The definition in the scope of the attached patent shall prevail. Ι ·· ΙΙ Page 12

Claims (1)

8 Y年/D月/^^日修正/更/補充 ^-2J8 3-S A 號 88113139_年月曰_ί±£._ 六、申^專利範圍 1 、一種在基板上的半導體晶片封裝構造，其係包含： 一基板，其具有： 一介電層，具有上表面及下表面； 複數個晶片連接墊及導電線路，設於該介電層之 上表面； 複數個錫球銲墊，設於該介電層之下表面，該每 一個錫球銲墊係分別電性連接至相對應的晶片連接墊或導 電線路；及 一保護層設在該基板之表面，其中該複數個錫球 銲墊以及該介電層之上表面包括該複數個晶片連接墊及導 電線路係裸露於該保護層； 複數個錫球，設於該基板之複數個錫球銲墊，用以與 外界電性溝通； 一半導體晶片固設於該基板，該晶片具有複數個晶片 銲墊，該每一晶片銲墊係分別電性連接至相對應的晶片連 接墊或導電線路；及 一封膠體，其包覆該半導體晶片以及該基板設有該半 導體晶片之表面。8 Year Y / D Month / ^^ Day Correction / More / Supplement ^ -2J8 3-SA No. 88113139_Year Month _ί £ ._ VI. Application for Patent Scope 1. A semiconductor chip package structure on a substrate , Which comprises: a substrate having: a dielectric layer having an upper surface and a lower surface; a plurality of wafer connection pads and conductive lines provided on the upper surface of the dielectric layer; a plurality of solder ball pads, provided On the lower surface of the dielectric layer, each of the solder ball pads is electrically connected to a corresponding chip connection pad or a conductive circuit, respectively; and a protective layer is provided on the surface of the substrate, wherein the plurality of solder ball pads are The pad and the upper surface of the dielectric layer include the plurality of chip connection pads and the conductive lines exposed on the protective layer; a plurality of solder balls, a plurality of solder ball pads provided on the substrate, for electrically communicating with the outside world A semiconductor wafer is fixed on the substrate, the wafer has a plurality of wafer pads, each of which is electrically connected to a corresponding wafer connection pad or a conductive line, respectively; and a piece of gel, which covers the A semiconductor wafer and the substrate are provided with the The surface of the semiconductor wafer. 裝。 裝 封成 封製 片製 片脂 晶脂 晶樹 禮樹 體ΒΤ 導化 導化 半強 半強 P99-009.ptc 第13頁 2000.10.16.014 8 3 6 ^號 88113139 Λ_Ά 曰 修正 六、申請專利範圍 成。 4 、依申請專利範圍第2項之在基板上的半導體晶片封裝 構造，其中該基板之介電層係以FR-4玻璃纖維強化環氧樹 脂製成》 5 、一種用以形成一在基板上的半導體晶片封裝構造之基 板，其中該基板之上表面係用以封裝一半導體晶片，並且 該半導體晶片係為一封膠體包覆，該基板係包含： 一介電層，具有上表面及下表面； 複數個晶片連接墊及導電線路，設於該介電層之上表 面； 複數個錫球銲墊，設於該介電層之下表面，該每一個 錫球銲墊係分別電性連接至相對應的晶片連接墊或導電線 路；及 一保護層設在該基板之表面，其中該複數個錫球銲墊 以及該介電層之上表面包括該複數個晶片連接垫及導電線 路係裸露於該保護層。 pit* ^ ^ 6 、依申請專利範圍第5項之基板，其中該介電層係以R 璃纖維強化樹腊製成。 7 、依申請專利範圍第6項之基板，其中該介電層係以玻 璃纖維強化BT樹脂製成。Installed. Encapsulation, encapsulation, production, production, production, production, production, production, production, production, production, production, production, production, production, production, production, production, production, production, etc. . 4. The semiconductor chip package structure on the substrate according to item 2 of the scope of the patent application, wherein the dielectric layer of the substrate is made of FR-4 glass fiber reinforced epoxy resin. 5. A method for forming a substrate on the substrate. A semiconductor wafer package structure substrate, wherein the upper surface of the substrate is used to encapsulate a semiconductor wafer, and the semiconductor wafer is a colloidal coating, the substrate system includes: a dielectric layer having an upper surface and a lower surface ; A plurality of chip connection pads and conductive lines are provided on the upper surface of the dielectric layer; a plurality of solder ball pads are provided on the lower surface of the dielectric layer, and each of the solder ball pads is electrically connected to The corresponding wafer connection pads or conductive lines; and a protective layer disposed on the surface of the substrate, wherein the plurality of solder ball pads and the upper surface of the dielectric layer include the plurality of wafer connection pads and the conductive lines are exposed on The protective layer. pit * ^ ^ 6. The substrate according to item 5 of the scope of patent application, wherein the dielectric layer is made of R glass fiber reinforced wax. 7. The substrate according to item 6 of the scope of patent application, wherein the dielectric layer is made of glass fiber reinforced BT resin. ΪΗ P99-009.ptc 第14頁 2000.10.16.015 42Ϊ836案號 88113139_年月日__ 六、申請專利範圍 8 、依申請專利範圍第6項之基板，其中該介電層係以 FR-4玻璃纖維強化環氧樹脂製成。 9 、依申請專利範圍第5項之基板，其中該基板係為設在 一條狀構造上的複數個基板之一，該條狀構造係用以形成 複數個在基板上的半導體晶片封裝。ΪΗ P99-009.ptc Page 14 2000.10.16.015 42Ϊ836 Case No. 88113139_Year_Month__ VI. The scope of patent application 8, the substrate according to item 6 of the scope of patent application, where the dielectric layer is made of FR-4 glass Made of fiber reinforced epoxy resin. 9. The substrate according to item 5 of the scope of patent application, wherein the substrate is one of a plurality of substrates provided on a stripe structure, and the stripe structure is used to form a plurality of semiconductor wafer packages on the substrate. P99-009.ptc 第15頁 2000.10.16.016P99-009.ptc Page 15 2000.10.16.016
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