JPH11163051A - Mounting structure of semiconductor chip and semiconductor device - Google Patents

Mounting structure of semiconductor chip and semiconductor device

Info

Publication number
JPH11163051A
JPH11163051A JP9331597A JP33159797A JPH11163051A JP H11163051 A JPH11163051 A JP H11163051A JP 9331597 A JP9331597 A JP 9331597A JP 33159797 A JP33159797 A JP 33159797A JP H11163051 A JPH11163051 A JP H11163051A
Authority
JP
Japan
Prior art keywords
chip
layer
semiconductor chip
conductive
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9331597A
Other languages
Japanese (ja)
Other versions
JP3326553B2 (en
Inventor
Kazutaka Shibata
和孝 柴田
Tsunemori Yamaguchi
恒守 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP33159797A priority Critical patent/JP3326553B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to KR10-1998-0707403A priority patent/KR100522223B1/en
Priority to US09/155,134 priority patent/US6133637A/en
Priority to EP98900725A priority patent/EP0890989A4/en
Priority to KR10-2004-7000090A priority patent/KR100467946B1/en
Priority to PCT/JP1998/000281 priority patent/WO1998033217A1/en
Publication of JPH11163051A publication Critical patent/JPH11163051A/en
Priority to US09/612,480 priority patent/US6458609B1/en
Application granted granted Critical
Publication of JP3326553B2 publication Critical patent/JP3326553B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract

PROBLEM TO BE SOLVED: To provide a COC structured laminated chip with an anisotropically conductive film for preventing electrode pads from corroding, and a semiconductor device having this laminate chip. SOLUTION: A first and a second semiconductor chips 1, 2 are laminated through an anisotropically conductive film ACF 3. Electrode pads 11A of bonding terminals to the second chip 2 and electrode pads 12A for wire bonding are formed on the surface of the first chip 1. Electrode pads 21A of bonding terminals to the first chip 1 are formed on the surface of the second chip 2. Conductive protective layers 11, 21, 12 are formed on the surfaces of the electrode pads 11A, 21A, 12A.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本願発明は、複数の半導体チ
ップをそれらの厚み方向に積み重ねたいわゆるチップ・
オン・チップと称される実装構造の積層チップ、および
その積層チップを有する半導体装置に関する。The present invention relates to a so-called chip in which a plurality of semiconductor chips are stacked in their thickness direction.
The present invention relates to a laminated chip having a mounting structure called on-chip and a semiconductor device having the laminated chip.

【０００２】[0002]

【従来の技術】従来、ＩＣやＬＳＩといった半導体チッ
プは、テープキャリアや樹脂基板上にベアチップ状態で
実装されるのが一般的である。その実装形態として、テ
ープ・オートメイテッド・ボンディング（ＴＡＢ）方式
やチップ・オン・ボード（ＣＯＢ）方式といった形態が
あり、様々な要因を勘案して最適な実装形態が選定され
ている。2. Description of the Related Art Conventionally, semiconductor chips such as ICs and LSIs are generally mounted in a bare chip state on a tape carrier or a resin substrate. Examples of the mounting form include a tape automated bonding (TAB) method and a chip-on-board (COB) method, and an optimum mounting form is selected in consideration of various factors.

【０００３】このような実装形態の半導体チップに対し
て、チップ上に他のベアチップを積層するようにして接
合する、いわゆるチップ・オン・チップ方式（以下、Ｃ
ＯＣとする）という実装形態がある。このＣＯＣ実装形
態によれば高密度実装化を容易に達成できることから、
ＣＯＣ実装形態による積層チップが小型電子機器や薄型
の携帯端末、あるいはＩＣカードといった各種のものに
採用されることが考えられる。[0003] A so-called chip-on-chip method (hereinafter referred to as C) in which a semiconductor chip having such a mounting form is joined by stacking another bare chip on the chip.
OC). According to this COC mounting form, high-density mounting can be easily achieved.
It is conceivable that the laminated chip by the COC mounting form is adopted for various kinds of small electronic devices, thin portable terminals, and IC cards.

【０００４】ＣＯＣ実装形態の積層チップは、図６に示
されるように、第１のチップ１と第２のチップとが、異
方性導電性膜３を介して積層されたものである。第１の
チップ１および第２のチップ２は、積層面にそれぞれ電
極パッド１１Ａ，２１Ａを有している。さらに、第１の
チップ１は、上記電極パッド１１Ａとは別の電極パッド
１２Ａを有している。電極パッド１２Ａは、ワイヤボン
ディングされ、ワイヤＷを介してフィルム基板等のリー
ド端子へ電気的に接続されることになる。第１のチップ
１と第２のチップ２とは、異方性導電膜３を介してパッ
ド１１Ａ，２１Ａによって接続される。異方性導電膜３
自体は絶縁性であるが、導電性粒子３ｂを含んでいる。
この導電性粒子３ｂによってパッド１１Ａ，２１Ａ間の
電気的接合が図られる。通常、電極パッド１１Ａ，１２
Ａ，２１Ａにはアルミニウムパッド、電極パッド１１
Ａ，２１Ａを覆う異方性導電膜３にはエポキシ樹脂から
なる異方性導電フィルム（以下、ＡＣＦとする）が用い
られている。As shown in FIG. 6, a laminated chip in a COC mounting mode is a laminated chip in which a first chip 1 and a second chip are laminated via an anisotropic conductive film 3. The first chip 1 and the second chip 2 have electrode pads 11A and 21A respectively on the lamination surface. Furthermore, the first chip 1 has an electrode pad 12A different from the electrode pad 11A. The electrode pad 12A is wire-bonded and electrically connected to a lead terminal such as a film substrate via the wire W. The first chip 1 and the second chip 2 are connected by pads 11A and 21A via the anisotropic conductive film 3. Anisotropic conductive film 3
Although itself is insulative, it contains conductive particles 3b.
Electrical connection between the pads 11A and 21A is achieved by the conductive particles 3b. Usually, the electrode pads 11A, 12
A and 21A have aluminum pads and electrode pads 11
An anisotropic conductive film (hereinafter, referred to as ACF) made of an epoxy resin is used for the anisotropic conductive film 3 covering A and 21A.

【０００５】この積層チップＡをワイヤＷによりフィル
ム基板等と電気的に接続して半導体装置中間品とし、こ
の半導体装置中間品をモールド樹脂で覆って成形するこ
とによって、半導体装置が得られる。A semiconductor device is obtained by electrically connecting the laminated chip A to a film substrate or the like via a wire W to form a semiconductor device intermediate product, and covering the semiconductor device intermediate product with a mold resin and molding.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、上記Ｃ
ＯＣ構造の積層チップＡを有する半導体装置では、ＡＣ
Ｆ３に覆われたアルミニウムパッド１１Ａ，２１Ａが腐
食することがあった。ＡＣＦ３の主成分であるエポキシ
樹脂がアルミニウムパッド１１Ａ，２１Ａを腐食させる
と推察されている。さらにはＡＣＦ３に覆われていない
アルミニウムパッド１２Ａにも腐食が見られることがあ
る。半導体装置中間品をモールド樹脂で覆う際の熱でＡ
ＣＦ３が溶融してアルミニウムパッド１２Ａへ流れてし
まい、アルミニウムパッド１２Ａが腐食されるものと推
察されている。However, the above C
In a semiconductor device having the stacked chip A having the OC structure, AC
The aluminum pads 11A and 21A covered with F3 sometimes corroded. It is presumed that the epoxy resin, which is the main component of ACF3, corrodes the aluminum pads 11A and 21A. Further, corrosion may also be observed on the aluminum pad 12A not covered with the ACF3. Heat generated when the semiconductor device intermediate product is covered with mold resin
It is presumed that the CF3 melts and flows to the aluminum pad 12A, and the aluminum pad 12A is corroded.

【０００７】ＡＣＦ３をエポキシ樹脂ではなく、他の熱
硬化性樹脂に置き換えてアルミニウムパッド１１Ａ，２
１，１２Ａの腐食を防ぐことも考慮したが、エポキシ樹
脂は電気絶縁性および接着性に優れているので、ＡＣＦ
３としては最適である。The ACF 3 is replaced with another thermosetting resin instead of an epoxy resin, and the aluminum pads 11A, 2A
Although consideration was given to preventing corrosion of 1,12A, epoxy resin is excellent in electric insulation and adhesiveness.
3 is optimal.

【０００８】本願発明は、このような事情のもとで考え
出されたものであって、ＡＣＦによって、電極パッドが
腐食されないＣＯＣ構造の積層チップ、その積層チップ
を有する半導体装置を提供することを課題としている。The present invention was conceived under such circumstances, and it is an object of the present invention to provide a laminated chip having a COC structure in which an electrode pad is not corroded by an ACF, and a semiconductor device having the laminated chip. It is an issue.

【０００９】[0009]

【発明の開示】上記の課題を解決するため、本願発明で
は、次の技術的手段を講じている。DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

【００１０】本願発明の第１の側面によって提供される
半導体チップの実装構造は、複数の半導体チップがそれ
らの厚み方向に積層されており、上記半導体チップの積
層面に設けられた電極パッドどうしが異方性導電膜を介
して電気的に接合されている半導体チップの実装構造で
あって、上記電極パッドは導電保護層を表面に有してお
り、上記半導体チップは積層面でない領域にワイヤボン
ディング用の電極パッドを有しており、上記ワイヤボン
ディング用の電極パッドも上記導電保護層を表面に有し
ていることに特徴づけられる。In the semiconductor chip mounting structure provided by the first aspect of the present invention, a plurality of semiconductor chips are stacked in their thickness direction, and electrode pads provided on the stacked surface of the semiconductor chips are connected to each other. A mounting structure of a semiconductor chip electrically connected via an anisotropic conductive film, wherein the electrode pad has a conductive protective layer on the surface, and the semiconductor chip is wire-bonded to a region other than the lamination surface. And the electrode pad for wire bonding also has the conductive protective layer on the surface.

【００１１】本願発明では、半導体チップを電気的に接
合させる電極パッドだけではなく、ワイヤボンディング
用の電極パッドにも導電保護層を設けている。導電保護
層は、半導体チップを別の半導体チップやワイヤと電気
的に接合させ、かつ、電極パッドをＡＣＦから保護して
腐食を防止するものである。In the present invention, the conductive protection layer is provided not only on the electrode pads for electrically connecting the semiconductor chips but also on the electrode pads for wire bonding. The conductive protective layer electrically connects the semiconductor chip to another semiconductor chip or wire, and protects the electrode pads from ACF to prevent corrosion.

【００１２】本願発明の実施形態では、上記導電保護層
は、バリアメタル層上に金属層が積層したものであるこ
とが好ましい。バリアメタル層はスパッタ法や真空蒸着
法等の手段によって形成され、金属層は電気メッキ等に
よって形成される。上記方法で形成されたバリアメタル
層や金属層は、電極パッドとの密着性が高く保護層とし
て非常に有効なものとなる。In the embodiment of the present invention, it is preferable that the conductive protective layer is formed by laminating a metal layer on a barrier metal layer. The barrier metal layer is formed by means such as a sputtering method or a vacuum evaporation method, and the metal layer is formed by electroplating or the like. The barrier metal layer or the metal layer formed by the above method has high adhesion to the electrode pad and is very effective as a protective layer.

【００１３】本願発明のさらに好ましい実施形態とし
て、上記バリアメタル層はチタン層に白金層が積層した
ものであり、上記金属層は金からなる電極バンプとする
構成にすることができる。バリアメタル層を構成するチ
タン層および白金層は、薄膜状に形成しやすく、薬剤処
理によって容易に除去が可能である。金属層は半導体チ
ップ接合用の電極パッド上に形成されるので、乳白色の
異方性導電フィルム（ＡＣＦ）や異方性導電樹脂（ＡＣ
Ｒ）によって覆われることになる。この金属層が金であ
れば、上記ＡＣＦやＡＣＲを介してでも目視で容易に認
識される。さらに、金は、ワイヤの材質であるアルミニ
ウムとの接着性が良いので、ワイヤボンディング用の電
極パッドに形成される金属層としても好ましいものであ
る。[0013] In a further preferred embodiment of the present invention, the barrier metal layer is formed by laminating a platinum layer on a titanium layer, and the metal layer may be configured as an electrode bump made of gold. The titanium layer and the platinum layer constituting the barrier metal layer are easily formed into a thin film, and can be easily removed by chemical treatment. Since the metal layer is formed on the electrode pad for bonding the semiconductor chip, a milky white anisotropic conductive film (ACF) or an anisotropic conductive resin (AC
R). If the metal layer is gold, it can be easily recognized visually through the ACF or ACR. Further, gold has good adhesion to aluminum, which is a material of the wire, and is therefore preferable as a metal layer formed on an electrode pad for wire bonding.

【００１４】上記導電保護層は、ポリチアジル、ポリア
セチレン、ポリジアセチレン、ポリピロール、ポリパラ
フェニレン、ポリパラフェニレンスルフィド、ポリパラ
フェニレンビニレンおよびポリチオフェンから選ばれる
少なくとも１種の導電性高分子からなるものとすること
もできる。The conductive protective layer comprises at least one conductive polymer selected from polythiazyl, polyacetylene, polydiacetylene, polypyrrole, polyparaphenylene, polyparaphenylene sulfide, polyparaphenylene vinylene and polythiophene. Can also.

【００１５】ポリチアジルは、極低温で超伝導を示す金
属的導電性高分子である。その他のポリアセチレン等
は、共役２重結合によるπ電子の非局在化により半導体
的な性質を示す高分子半導体である。これらの高分子半
導体は、種々のドナーやアクセプターが添加されること
によって、分子内のπ電子が移動し、導電性が増大した
電荷移動錯体となる。[0015] Polythiazyl is a metallic conductive polymer that exhibits superconductivity at cryogenic temperatures. Other polyacetylenes and the like are polymer semiconductors that exhibit semiconductor properties due to delocalization of π electrons due to conjugated double bonds. By adding various donors and acceptors, these polymer semiconductors become π-electrons in the molecule and become a charge transfer complex with increased conductivity.

【００１６】本願発明では、上記電極パッドはアルミニ
ウムパッドであり、上記異方性導電膜はエポキシ樹脂を
主成分とするフィルムであることが望まれる。In the present invention, it is desired that the electrode pad is an aluminum pad and the anisotropic conductive film is a film containing an epoxy resin as a main component.

【００１７】電極パッドは、スパッタ法や真空蒸着等に
よって半導体チップ上に被膜層を形成し、この被膜層に
エッチング処理を施すことによって形成されるものであ
る。アルミニウムは、半導体チップの材料であるシリコ
ンと密着性が良く、スパッタ法や真空蒸着に適している
ので、電極パッドとしては最適である。The electrode pad is formed by forming a coating layer on a semiconductor chip by a sputtering method, vacuum evaporation, or the like, and performing an etching process on the coating layer. Aluminum has a good adhesion to silicon, which is a material of a semiconductor chip, and is suitable for a sputtering method or a vacuum deposition, so that it is most suitable as an electrode pad.

【００１８】異方性導電膜は、絶縁性樹脂内に金属、炭
素等の導電性粒子が分散されたものである。この導電性
粒子によって、異方性導電膜で接着した複数の半導体チ
ップの電気的接合が図られる。その電気的接合の機構
は、後に説明する。異方性導電膜は、半導体チップを積
層させるためのものなので、接着性が高いことが望まれ
る。エポキシ樹脂は、接着性および絶縁性に優れた樹脂
なので、複数の半導体チップを接着して、半導体チップ
間の電気的接続を図る異方性導電膜としては最適なもの
である。The anisotropic conductive film is obtained by dispersing conductive particles such as metal and carbon in an insulating resin. With the conductive particles, electrical bonding of a plurality of semiconductor chips bonded by the anisotropic conductive film is achieved. The mechanism of the electrical connection will be described later. Since the anisotropic conductive film is for laminating semiconductor chips, it is desired that the anisotropic conductive film has high adhesiveness. Epoxy resin is a resin having excellent adhesiveness and insulating properties, and is most suitable as an anisotropic conductive film for bonding a plurality of semiconductor chips to establish electrical connection between the semiconductor chips.

【００１９】本願発明の第２の側面によって提供される
半導体装置は、上記に記載の半導体チップの実装構造を
有する半導体装置であって、上記半導体チップはモール
ド樹脂でパッケージされていることに特徴づけられる。A semiconductor device provided by the second aspect of the present invention is a semiconductor device having the above-described semiconductor chip mounting structure, wherein the semiconductor chip is packaged with a mold resin. Can be

【００２０】この半導体装置は、異方性導電膜で複数の
半導体チップを積層し、ワイヤを介して半導体チップと
リード基板等とを接続してから、積層チップやワイヤの
ボンディング箇所等をモールド樹脂でパッケージするこ
とによって得られる。モールド樹脂でパッケージする際
に発生する熱によって異方性導電膜が溶融し、ワイヤボ
ンディング用の電極パッドの方へ流れることもあるが、
この電極パッドは、導電保護層を有するので異方性導電
膜によって腐食されることはない。In this semiconductor device, a plurality of semiconductor chips are laminated with an anisotropic conductive film, the semiconductor chip is connected to a lead substrate or the like via wires, and then the bonding portion of the laminated chip or the wire is molded resin. Obtained by packaging with Although the anisotropic conductive film is melted by the heat generated when packaging with mold resin, it may flow toward the electrode pad for wire bonding,
Since the electrode pad has the conductive protective layer, it is not corroded by the anisotropic conductive film.

【００２１】このように、本願発明に係る半導体チップ
の実装構造を有する半導体装置では、導電保護層がワイ
ヤボンディング用の電極パッドを保護しているので、上
記電極パッドが腐食されることはなくなる。従って、本
願発明の半導体装置は、従来の半導体装置よりも電気的
接合が良好なものとなり、導電保護層によってその品質
を長期に渡って維持することができる。As described above, in the semiconductor device having the mounting structure of the semiconductor chip according to the present invention, since the conductive protection layer protects the electrode pads for wire bonding, the electrode pads are not corroded. Therefore, the semiconductor device of the present invention has better electrical bonding than the conventional semiconductor device, and the quality can be maintained for a long time by the conductive protective layer.

【００２２】[0022]

【発明の実施の形態】以下、本発明の実施の形態につい
て、添付図面を参照して説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.

【００２３】図１は、本願発明に係る半導体チップの実
施構造を有する積層チップＡの一実施例を示す要部断面
図である。図２は、図１に示される積層チップＡにおけ
るワイヤボンディング用端子の一部拡大断面図である。FIG. 1 is a sectional view of an essential part showing an embodiment of a laminated chip A having an embodiment of a semiconductor chip according to the present invention. FIG. 2 is a partially enlarged cross-sectional view of a wire bonding terminal in the laminated chip A shown in FIG.

【００２４】図１に示されるように、積層チップＡは、
第１の半導体チップ１と第２の半導体チップ２とが異方
性導電フィルム（ＡＣＦ）３を介して積層されたもので
ある。第１の半導体チップ１の表面には、第２の半導体
チップ２との接合端子である電極パッド１１Ａおよびワ
イヤボンディング用の電極パッド１２Ａが形成されてい
る。第２の半導体チップ２の表面には、半導体チップ１
との接合端子となる電極パッド２１Ａが形成されてい
る。両チップ１，２の表面では、電極パッド１１Ａ，２
１Ａ，１２Ａの形成されていない領域に絶縁膜１５が形
成されている。電極パッド１１Ａ，２１Ａ，１２Ａはア
ルミニウムパッドであり、その表面にはそれぞれ導電性
保護層１１，２１，１２が形成されている。As shown in FIG. 1, the laminated chip A is
The first semiconductor chip 1 and the second semiconductor chip 2 are stacked via an anisotropic conductive film (ACF) 3. On the surface of the first semiconductor chip 1, an electrode pad 11A as a bonding terminal with the second semiconductor chip 2 and an electrode pad 12A for wire bonding are formed. The semiconductor chip 1 is provided on the surface of the second semiconductor chip 2.
An electrode pad 21A serving as a joint terminal with the electrode pad 21A is formed. On the surfaces of both chips 1 and 2, electrode pads 11A and 2
An insulating film 15 is formed in a region where 1A and 12A are not formed. The electrode pads 11A, 21A, and 12A are aluminum pads, and conductive protection layers 11, 21, and 12 are formed on the surfaces thereof.

【００２５】ＡＣＦ３は絶縁性樹脂であるエポキシ樹脂
からなるフィルムであり、導電性粒子３ｂを分散させた
構造をとっている。導電保護層１１，２１に挟まれた導
電性粒子３ｂは、両保護層１１，２１によって圧縮され
る。両保護層１１，２１で挟まれていない導電性粒子３
ｂは、依然としてＡＣＦ３内で分散した状態である。従
って、半導体チップ１，２の両表面における両保護層１
１，２１間のみの電気的接合が図られ、両保護層１１，
２１間以外の絶縁性が維持される。導電性粒子３ｂとし
ては、金属球のほか、樹脂性ボールの表面にニッケルメ
ッキを施したもの、そのニッケルメッキの上にさらに金
メッキを施したもの等が使用される。The ACF 3 is a film made of an epoxy resin, which is an insulating resin, and has a structure in which conductive particles 3b are dispersed. The conductive particles 3b sandwiched between the conductive protective layers 11 and 21 are compressed by the two protective layers 11 and 21. Conductive particles 3 not sandwiched between both protective layers 11 and 21
b is still dispersed in the ACF3. Therefore, both protective layers 1 on both surfaces of the semiconductor chips 1 and 2
Only the electrical connection between the protective layers 11 and 21 is achieved.
Insulation other than between 21 is maintained. As the conductive particles 3b, besides metal spheres, those obtained by plating a resin ball surface with nickel, and those obtained by further plating gold on the nickel plating are used.

【００２６】第１のチップ１の表面に形成されているワ
イヤボンディング用端子の構造は、図２によって詳細に
説明される。電極パッド１２Ａの縁には絶縁膜１５が形
成されており、さらにパッド１２Ａの表面には導電保護
層１２が形成されている。導電保護層１２は、バリアメ
タル層１３ａに金属層１３ｂが積層されたものである。
バリアメタル層１３ａは、チタン層に白金層が積層され
て構成される（図示せず）。金属層１３ｂは、電気メッ
キ等によって形成された金である。ワイヤＷは金属層１
３ｂにボンディングされている。尚、図示はしてはいな
いが、第１のチップ１と第２のチップ２との接合端子で
ある電極パッド１１Ａ，２１Ａ表面にも、同一の構造を
持つ導電保護層１１，２１が形成されている。The structure of the wire bonding terminal formed on the surface of the first chip 1 will be described in detail with reference to FIG. An insulating film 15 is formed on the edge of the electrode pad 12A, and a conductive protection layer 12 is formed on the surface of the pad 12A. The conductive protection layer 12 is formed by laminating a metal layer 13b on a barrier metal layer 13a.
The barrier metal layer 13a is configured by stacking a platinum layer on a titanium layer (not shown). The metal layer 13b is gold formed by electroplating or the like. Wire W is metal layer 1
3b. Although not shown, conductive protection layers 11 and 21 having the same structure are also formed on the surfaces of the electrode pads 11A and 21A, which are connection terminals between the first chip 1 and the second chip 2. ing.

【００２７】上記電極パッド１１Ａ，２１Ａ，１２Ａ
は、それぞれ導電保護層１１，２１，１２によって表面
が保護されているので、エポキシ樹脂であるＡＣＦ３に
よって腐食されることはない。The electrode pads 11A, 21A, 12A
Are protected by the conductive protection layers 11, 21, 12, respectively, so that they are not corroded by the ACF3 which is an epoxy resin.

【００２８】上記導電保護層の形成方法について、図３
を参照しながら簡単に説明する。第１のチップ１に回路
素子（図示せず）を一体的に造り込み、図３（ａ）に示
されるように、この回路素子と導通する電極パッド１１
Ａ，１２Ａを所定の配線パターンとともに形成する。こ
の電極パッド１１Ａ，１２Ａは、例えばスパッタ法ある
いは真空蒸着等の手段によってアルミニウムの金属被膜
層を第１のチップ１に形成した後、この金属被膜層にエ
ッチング処理を施すなどして形成される。FIG. 3 shows a method of forming the conductive protective layer.
This will be briefly described with reference to FIG. A circuit element (not shown) is integrally formed on the first chip 1 and, as shown in FIG. 3A, an electrode pad 11 electrically connected to the circuit element.
A and 12A are formed together with a predetermined wiring pattern. The electrode pads 11A and 12A are formed by forming an aluminum metal coating layer on the first chip 1 by, for example, a sputtering method or vacuum deposition, and then performing an etching process on the metal coating layer.

【００２９】図３（ｂ）に示されるように、回路素子や
配線パターンを保護すべく、電極パッド１１Ａ，１２Ａ
の周辺を覆うようにして、例えばＣＶＤ法等によって絶
縁膜１５、すなわちパシベーション膜を形成する。As shown in FIG. 3B, in order to protect circuit elements and wiring patterns, electrode pads 11A, 12A
An insulating film 15, that is, a passivation film is formed by, for example, a CVD method or the like so as to cover the periphery of.

【００３０】さらに、図３（ｃ）に示されるように、電
極パッド１１Ａ，１２Ａおよび絶縁膜１５を覆うように
してバリアメタル層１３ａを形成する。バリアメタル層
１３ａは、チタン層に白金層が積層されたものであり、
チタン層は２０００Å程度に、白金層は１０００Å程度
に形成される。なお、このバリアメタル層１３ａも、例
えばスパッタ法あるいは真空蒸着の手段によって形成さ
れる。Further, as shown in FIG. 3C, a barrier metal layer 13a is formed so as to cover the electrode pads 11A and 12A and the insulating film 15. The barrier metal layer 13a is formed by stacking a platinum layer on a titanium layer,
The titanium layer is formed at about 2000 ° and the platinum layer is formed at about 1000 °. The barrier metal layer 13a is also formed by, for example, a sputtering method or a vacuum deposition method.

【００３１】続いて、図３（ｄ）に示されるように、電
極パッド１１Ａ，１２Ａ上の導電保護層１１，１２を形
成すべき領域を除いてフォトレジスト層１３ｃを形成す
る。このフォトレジスト層１３ｃは、バリアメタル層１
３ａ上に感光性樹脂層を積層した後に、所定のマスクを
用いて露光し、上記感光性樹脂層を現像処理することに
よって形成される。Subsequently, as shown in FIG. 3D, a photoresist layer 13c is formed on the electrode pads 11A and 12A except for regions where the conductive protection layers 11 and 12 are to be formed. The photoresist layer 13c is formed on the barrier metal layer 1
After laminating a photosensitive resin layer on 3a, it is formed by exposing to light using a predetermined mask and developing the above photosensitive resin layer.

【００３２】次いで、図３（ｅ）に示されるように、フ
ォトレジスト層１３ｃが形成されていない領域、すなわ
ち導電保護層１１，１２を形成すべき領域に、金等の金
属層１３ｂを形成する。この金属層１３ｂは、例えば電
気メッキ等により形成されている。すなわち、電気メッ
キによって金の金属層１３ｂを形成する場合には、フォ
トレジスト層１３ｃが形成された第１のチップ１を金イ
オンが含まれている溶液内に漬け込み、バリアメタル層
１３ａをマイナス電極として通電するすることによって
行われる。この場合、フォトレジスト層１３ｃが形成さ
れていない領域のバリアメタル層１３ａ上に金が成長
し、金属層１３ｂが形成される。Next, as shown in FIG. 3E, a metal layer 13b such as gold is formed in a region where the photoresist layer 13c is not formed, that is, in a region where the conductive protection layers 11 and 12 are to be formed. . This metal layer 13b is formed by, for example, electroplating. That is, when the gold metal layer 13b is formed by electroplating, the first chip 1 on which the photoresist layer 13c is formed is immersed in a solution containing gold ions, and the barrier metal layer 13a is connected to the negative electrode. It is performed by energizing as follows. In this case, gold grows on the barrier metal layer 13a in a region where the photoresist layer 13c is not formed, and the metal layer 13b is formed.

【００３３】さらに、図３（ｆ）に示されるように、フ
ォトレジスト層１３ｃを剥離処理してバリアメタル層１
３ａを露出させ、絶縁膜１５を露出させる。このように
して、金属層１３ｂが電極バンプとして形成される。Further, as shown in FIG. 3 (f), the photoresist layer 13c is peeled off to remove the barrier metal layer 1c.
3a is exposed, and the insulating film 15 is exposed. Thus, the metal layer 13b is formed as an electrode bump.

【００３４】このように導電保護層１１，１２は、バリ
アメタル層１３および金属層１３ｂからなり、電極パッ
ド１１Ａ，１２Ａ上に同時に形成される。なお、導電性
保護層２１も同様の方法で電極パッド２１Ａ上に成形さ
れる。As described above, the conductive protection layers 11 and 12 are composed of the barrier metal layer 13 and the metal layer 13b, and are simultaneously formed on the electrode pads 11A and 12A. The conductive protective layer 21 is formed on the electrode pad 21A in the same manner.

【００３５】上記導電保護層１１，１２を電極パッド１
１Ａ，１２Ａ上に有している半導体チップの実装工程を
図４によって説明する。The conductive protection layers 11 and 12 are used as electrode pads 1.
The mounting process of the semiconductor chip on 1A and 12A will be described with reference to FIG.

【００３６】同図に示されるように、第１のチップ１に
設けられた電極パッド１１Ａおよびパッド１１Ａ上に形
成されている導電保護層１１をＡＣＦ３によって覆う。
その後、第２のチップ２に設けられた電極パッド２１Ａ
上に成形された導電保護層２１と、導電保護層１１とを
目視等によって対面させた状態にする。導電保護層１
１，２１を構成する金属層１３ｂ（図２参照）が金の場
合は、乳白色のＡＣＦ３で覆われても金をはっきり確認
できる。このため、両チップ１，２を接着させる場合に
正確な位置決めを行なうことができる。なお、ＡＣＦ３
は、絶縁性および接着性に優れたエポキシ樹脂を主成分
とするフィルムが好ましい。As shown in FIG. 3, the ACF 3 covers the electrode pads 11A provided on the first chip 1 and the conductive protection layer 11 formed on the pads 11A.
After that, the electrode pads 21A provided on the second chip 2
The conductive protective layer 21 and the conductive protective layer 11 formed above are brought into a state of facing each other by visual observation or the like. Conductive protective layer 1
In the case where the metal layer 13b (see FIG. 2) constituting the first and second layers 21 and 21 is gold, the gold can be clearly confirmed even when covered with the milky white ACF3. Therefore, when the chips 1 and 2 are bonded, accurate positioning can be performed. ACF3
Is preferably a film mainly composed of an epoxy resin having excellent insulating properties and adhesiveness.

【００３７】導電保護層２１と導電保護層１１とを対面
させた後、第２のチップ２を押圧装置４で第１のチップ
１に近づけていく。両チップ１，２の接着直前の位置
は、搬送テーブルＣおよび押圧装置４の微調節によって
決定される。After the conductive protection layer 21 and the conductive protection layer 11 face each other, the second chip 2 is brought closer to the first chip 1 by the pressing device 4. The position immediately before the bonding of the two chips 1 and 2 is determined by fine adjustment of the transport table C and the pressing device 4.

【００３８】第２のチップ２を第１のチップ１に押圧し
たら、搬送テーブルＣ内部に組み込まれていたヒータ
（図示せず）を作動させて、ＡＣＦ３を溶融させて電極
パッド１１Ａ、２１Ａおよび導電保護層１１，２１を覆
う。ＡＣＦ３が薄膜状に介在した状態で両チップ１，２
を接着し、チップ・オン・チップ（ＣＯＣ）実装形態に
よ積層チップが得られる。When the second chip 2 is pressed against the first chip 1, a heater (not shown) incorporated in the transfer table C is operated to melt the ACF 3 and to dispose the electrode pads 11A, 21A and the conductive pads. The protective layers 11 and 21 are covered. With the ACF3 interposed in the form of a thin film, both chips 1, 2
To obtain a laminated chip in a chip-on-chip (COC) mounting mode.

【００３９】実装工程終了後、ワイヤボンディング用の
電極パッド１２Ａに形成された導電保護層１２にワイヤ
をボンディングする。ワイヤのボンディングは、熱圧着
ボンディングや超音波ボンディングで行う。ワイヤをボ
ンディングした後、ワイヤをリード基板等に接続して半
導体装置中間品とし、この半導体装置中間品をモールド
樹脂でパッケージして半導体装置とする。After the completion of the mounting process, a wire is bonded to the conductive protection layer 12 formed on the electrode pad 12A for wire bonding. Wire bonding is performed by thermocompression bonding or ultrasonic bonding. After bonding the wires, the wires are connected to a lead board or the like to obtain a semiconductor device intermediate product, and the semiconductor device intermediate product is packaged with a mold resin to obtain a semiconductor device.

【００４０】図５は、本願発明に係る半導体装置Ｂの一
実施例を示す要部断面図である。同図に示されるよう
に、第１のチップ１と第２のチップ２とは、ＡＣＦ３を
介して接着されている。ＡＣＦ３内には導電性粒子３ｂ
が分散されており、導電保護層１１，２１に挟まれた導
電性粒子３ｂは圧縮され、導電保護層１１，２１に挟ま
れていない導電性粒子３ｂはＡＣＦ３内で分散してい
る。従って、圧縮された導電性粒子３ｂによって両保護
層１１，２１間が電気的に接合され、両保護層１１，２
１間以外は電気的に絶縁されることになる。電極パッド
１２Ａ上には導電保護層１２が形成されており、導電保
護層１２はワイヤＷを介してリード基板３０上の導電配
線部２５に接続されている。両チップ１，２やワイヤＷ
は、モールド樹脂２０によって樹脂パッケージされてい
る。FIG. 5 is a cross-sectional view of a principal part showing one embodiment of a semiconductor device B according to the present invention. As shown in the figure, the first chip 1 and the second chip 2 are bonded via an ACF 3. Conductive particles 3b in ACF3
Are dispersed, the conductive particles 3b sandwiched between the conductive protective layers 11 and 21 are compressed, and the conductive particles 3b not sandwiched between the conductive protective layers 11 and 21 are dispersed in the ACF 3. Therefore, the two protective layers 11 and 21 are electrically joined by the compressed conductive particles 3b, and the two protective layers 11 and 21 are electrically connected.
Except for one, it is electrically insulated. The conductive protection layer 12 is formed on the electrode pad 12A, and the conductive protection layer 12 is connected to the conductive wiring portion 25 on the lead substrate 30 via the wire W. Both chips 1 and 2 and wire W
Are packaged by a mold resin 20.

【００４１】モールド樹脂２０で両チップ１，２をパッ
ケージする際には熱が発生し、この熱によってＡＣＦ３
が溶融し、電極パッド１２Ａの方へ流れる。電極パッド
１２Ａは導電保護層１２によって保護されるので、ＡＣ
Ｆ３によって腐食されることはない。When the two chips 1 and 2 are packaged with the mold resin 20, heat is generated, and the heat generates an ACF3.
Melts and flows toward the electrode pad 12A. Since the electrode pad 12A is protected by the conductive protection layer 12, AC
It is not corroded by F3.

【００４２】以上、本願発明の実施例を説明したが、本
願発明はこれらに限定されずに、以下に述べるように種
々変形することが可能である。Although the embodiments of the present invention have been described above, the present invention is not limited to these, and various modifications can be made as described below.

【００４３】上記実施例では、電極パッド１２Ａ上に金
をメッキして導電保護層１２としているが、導電保護層
１２としてポリアセチレン等の導電性高分子を使用して
も差し支えない。ポリアセチレンに添加するドープ材
（ヨウ素等）の量を調節することで、ポリアセチレンの
電導度を制御することもできる。In the above embodiment, the conductive protection layer 12 is formed by plating gold on the electrode pad 12A. However, a conductive polymer such as polyacetylene may be used as the conductive protection layer 12. By adjusting the amount of the doping material (such as iodine) added to polyacetylene, the conductivity of polyacetylene can be controlled.

【００４４】上記実施例では、第１のチップ１と第２の
チップ２とを接着する場合の位置決めを目視で行ってい
るが、ＣＣＤ撮像装置やマイクロコンピュータによって
導電保護層１１，２１の位置を正確に調節することもで
きる。In the above embodiment, the positioning when the first chip 1 and the second chip 2 are bonded is performed visually, but the positions of the conductive protection layers 11 and 21 are determined by a CCD image pickup device or a microcomputer. It can also be adjusted precisely.

【００４５】上記実施例で使用している異方性導電膜
は、エポキシ樹脂からなる異方性導電フィルム（ＡＣ
Ｆ）であるが、接着製および絶縁性に優れていればその
形態は問題ではない。異方性導電膜として、ＡＣＦでは
なく異方性導電樹脂（ＡＣＲ）を用いることもできる。The anisotropic conductive film used in the above examples is an anisotropic conductive film (AC
F), but its form is not a problem as long as it is excellent in adhesion and insulation. As the anisotropic conductive film, an anisotropic conductive resin (ACR) can be used instead of the ACF.

【００４６】以上に限らず、本願発明は特許請求の範囲
に含まれる範囲内で種々な変形を施すことも可能であ
り、その中には各構成要素を均等物で置換したものも含
まれる。The present invention is not limited to the above, and various modifications can be made within the scope of the claims, including those in which each component is replaced with an equivalent.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本願発明に係る半導体チップの実施構造を有す
る積層チップの一実施例を示す要部断面図である。FIG. 1 is a sectional view of a main part showing an embodiment of a laminated chip having an embodiment of a semiconductor chip according to the present invention.

【図２】図２は、図１の積層チップにおけるワイヤボン
ディング用端子の一部拡大断面図である。FIG. 2 is a partially enlarged sectional view of a wire bonding terminal in the laminated chip of FIG. 1;

【図３】半導体チップに導電保護層を形成する工程の一
実施例を示す断面図である。FIG. 3 is a cross-sectional view showing one embodiment of a step of forming a conductive protective layer on a semiconductor chip.

【図４】本願発明に係る半導体チップの実装構造を有す
る積層チップの製造工程の一実施例を示す断面図であ
る。FIG. 4 is a cross-sectional view showing one embodiment of a manufacturing process of a laminated chip having a semiconductor chip mounting structure according to the present invention.

【図５】本願発明に係る半導体装置の一実施例を示す断
面図である。FIG. 5 is a sectional view showing one embodiment of a semiconductor device according to the present invention.

【図６】従来の積層チップの一例を示す一部拡大断面図
である。FIG. 6 is a partially enlarged sectional view showing an example of a conventional laminated chip.

【符号の説明】[Explanation of symbols]

１ 第１のチップ ２ 第２のチップ ３ 異方性導電フィルム（ＡＣＦ） ３ｂ 導電性粒子 １１，２１ 導電保護層 １１Ａ，２１Ａ 電極パッド １２ 導電保護層 １２Ａ ワイヤボンディング用の電極パッド １３ａ バリアメタル層 １３ｂ 金属層 １５ 絶縁膜 ２０ モールド樹脂 Ｗ ワイヤ Ａ 積層チップ Ｂ 半導体装置 REFERENCE SIGNS LIST 1 first chip 2 second chip 3 anisotropic conductive film (ACF) 3b conductive particles 11, 21 conductive protective layer 11A, 21A electrode pad 12 conductive protective layer 12A electrode pad for wire bonding 13a barrier metal layer 13b Metal layer 15 Insulating film 20 Mold resin W Wire A Multilayer chip B Semiconductor device

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップがそれらの厚み方向
に積層しており、上記半導体チップの積層面に設けられ
た電極パッドどうしが異方性導電膜を介して電気的に接
合している半導体チップの実装構造であって、 上記電極パッドは、導電保護層を表面に有しており、 上記半導体チップは、積層面でない領域にワイヤボンデ
ィング用の電極パッドを有しており、 上記ワイヤボンディング用の電極パッドも、上記導電保
護層を表面に有していることを特徴とする、半導体チッ
プの実装構造。1. A semiconductor in which a plurality of semiconductor chips are stacked in their thickness direction, and electrode pads provided on a stacked surface of the semiconductor chips are electrically connected via an anisotropic conductive film. A chip mounting structure, wherein the electrode pad has a conductive protection layer on a surface thereof, and the semiconductor chip has an electrode pad for wire bonding in a region other than the lamination surface; A mounting structure of a semiconductor chip, characterized in that the electrode pad also has the conductive protective layer on the surface. 【請求項２】 上記導電保護層は、バリアメタル層上に
金属層が積層したものであることを特徴とする、請求項
１に記載の半導体チップの実装構造。2. The semiconductor chip mounting structure according to claim 1, wherein said conductive protection layer is formed by laminating a metal layer on a barrier metal layer. 【請求項３】 上記バリアメタル層はチタン層に白金層
が積層したものであり、上記金属層は金からなる電極バ
ンプであることを特徴とする、請求項２に記載の半導体
チップの実装構造。3. The mounting structure of a semiconductor chip according to claim 2, wherein the barrier metal layer is formed by stacking a platinum layer on a titanium layer, and the metal layer is an electrode bump made of gold. . 【請求項４】 上記導電保護層は、ポリチアジル、ポリ
アセチレン、ポリジアセチレン、ポリピロール、ポリパ
ラフェニレン、ポリパラフェニレンスルフィド、ポリパ
ラフェニレンビニレンおよびポリチオフェンから選ばれ
る少なくとも１種の導電性高分子からなることを特徴と
する、請求項１に記載の半導体チップの実装構造。4. The conductive protective layer comprises at least one conductive polymer selected from polythiazyl, polyacetylene, polydiacetylene, polypyrrole, polyparaphenylene, polyparaphenylene sulfide, polyparaphenylene vinylene, and polythiophene. The mounting structure of the semiconductor chip according to claim 1, wherein: 【請求項５】 上記電極パッドはアルミニウムパッドで
あり、上記異方性導電膜はエポキシ樹脂を主成分とする
フィルムであることを特徴とする、請求項１に記載の半
導体チップの実装構造。5. The semiconductor chip mounting structure according to claim 1, wherein said electrode pad is an aluminum pad, and said anisotropic conductive film is a film mainly composed of epoxy resin. 【請求項６】 請求項１から５のいずれかに記載の半導
体チップの実装構造を有する半導体装置であって、上記
半導体チップはモールド樹脂でパッケージされているこ
とを特徴とする、半導体装置。6. A semiconductor device having a semiconductor chip mounting structure according to claim 1, wherein said semiconductor chip is packaged with a mold resin.
JP33159797A 1997-01-24 1997-12-02 Semiconductor chip mounting structure and semiconductor device Expired - Fee Related JP3326553B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP33159797A JP3326553B2 (en) 1997-12-02 1997-12-02 Semiconductor chip mounting structure and semiconductor device
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33159797A JP3326553B2 (en) 1997-12-02 1997-12-02 Semiconductor chip mounting structure and semiconductor device

Publications (2)

Publication Number Publication Date
JPH11163051A true JPH11163051A (en) 1999-06-18
JP3326553B2 JP3326553B2 (en) 2002-09-24

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JP5066302B2 (en) * 2011-02-10 2012-11-07 パナソニック株式会社 Semiconductor device
CN103367350A (en) * 2012-04-05 2013-10-23 英飞凌科技股份有限公司 Electronic module
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JP5066302B2 (en) * 2011-02-10 2012-11-07 パナソニック株式会社 Semiconductor device
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US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

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