TWI618206B - 半導體封裝結構及其製作方法 - Google Patents

半導體封裝結構及其製作方法 Download PDF

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TWI618206B
TWI618206B TW106119241A TW106119241A TWI618206B TW I618206 B TWI618206 B TW I618206B TW 106119241 A TW106119241 A TW 106119241A TW 106119241 A TW106119241 A TW 106119241A TW I618206 B TWI618206 B TW I618206B
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thermal expansion
layer
packaging
carrier board
epoxy resin
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TW106119241A
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TW201903995A (zh
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許詩濱
許哲瑋
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恆勁科技股份有限公司
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Priority to US15/703,022 priority patent/US10475752B2/en
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Abstract

一種半導體封裝結構及其製作方法，其包含載板、晶片、凸塊、封裝層與熱膨脹匹配層。晶片位於載板之上表面上。凸塊用以電性連接晶片與載板之內連接端。封裝層用以包覆凸塊、晶片及載板之上表面。熱膨脹匹配層覆蓋於封裝層之整個上表面，並暴露出封裝層之側面，其中熱膨脹匹配層之熱膨脹係數與封裝層之熱膨脹係數不同，且熱膨脹匹配層之邊緣與封裝層之邊緣齊平。藉由熱膨脹匹配層產生整體平衡效果，而減少板翹問題。

Description

半導體封裝結構及其製作方法
本發明是有關於一種半導體封裝結構及其製作方法，且特別是有關於一種利用熱膨脹匹配層降低翹曲問題之半導體封裝結構及其製作方法。
晶片封裝主要提供積體電路(IC)保護、散熱、電路導通等功能。承載基板(亦稱載板)是介於積體電路晶片及印刷電路板(printed circuit board，PCB)之間的結構，主要功能為承載晶片，做為載體之用，並以載板線路連結晶片與印刷電路板之間訊號連結。隨晶圓製程技術演進，晶圓佈線密度、傳輸速率及降低訊號干擾等效能需求提高，使得積體電路晶片封裝的技術要求逐漸增加。
封裝載板的技術，區分為晶片與載板的連接方式，及載板與印刷電路板的連接方式。在晶片與載板的連接方式，主要有打線焊接(wire bound，WB)與覆晶(flip chip，FC)封裝。打線焊接是利用導線連接晶片上之電性接點(electric pad)與載板。覆晶封裝是將具有凸塊接點之晶片反貼覆置於載板上。
第1圖係表示習知覆晶封裝結構10，其包含晶片12、載板14、錫球(solder ball)16、封裝層18。晶片12係置放在載板14上，晶片12包含電性接點20，載板14包含導通層30。晶片12透過本身的電性接點20與錫球16電性連接至載板14的導通層30，藉此導通至覆晶封裝結構10的下表面，作為覆晶封裝結構10的輸出/輸入引腳。封裝層18對覆晶封裝結構10提供物理保護、電性保護、污染隔離與水氣隔離。之後，覆晶封裝結構10可進一步焊接在印刷電路板上(圖未示)。
晶片12的熱膨脹係數約為2.6百萬分之一/攝氏溫度(ppm/℃)，而封裝層18的熱膨脹係數約為10ppm/℃至50ppm/℃。如第2A圖與第2B圖所示，在高低溫循環測試與高溫迴銲後冷卻時，由於晶片12、載板14與封裝層18之熱膨脹係數差異(CTE dis-match)，覆晶封裝結構10會出現內應力，導致載板14翹曲(warpage)。覆晶封裝結構10翹曲會使得晶片12與錫球16連接觸不良，也會導致後續的印刷電路板無法組裝。熱膨脹係數的差異使得封裝結構承受熱應力而彎曲，可能導致焊點斷裂，進一步甚至可能發生晶片12破裂，而降低封裝結構的可靠度。尤其當晶片封裝朝向薄型化與球柵陣列封裝(ball Grid Array，BGA)技術發展時，解決翹曲問題更是日益重要。
因此，本發明之目的係提供一種具有熱膨脹匹配層之半導體封裝結構及其製作方法，其可以避免因晶片、載板與封裝層之熱膨脹係數差異而導致的翹曲問題。此外，本發明之製作方法從基板到晶片封裝皆以大板面形式(panel type)進行，可提升生產效率、縮短製程時間。
根據上述目的，本發明提供一種半導體封裝結構，其包含載板、晶片、複數個凸塊、封裝層與熱膨脹匹配層。載板具有上表面及下表面，其中在載板之上表面具有複數個內連接端，以及在下表面具有複數個外連接端。晶片位於載板之上表面上。凸塊用以電性連接晶片與載板之內連接端。封裝層用以包覆凸塊、晶片及載板之上表面。封裝層具有上表面與側面。熱膨脹匹配層覆蓋於封裝層之整個上表面，並暴露出封裝層之側面，其中熱膨脹匹配層之熱膨脹係數與封裝層之熱膨脹係數不同，且熱膨脹匹配層之邊緣與封裝層之邊緣齊平。
於本發明之一實施例中，封裝層係包覆凸塊、晶片之側面以及載板之上表面，而熱膨脹匹配層覆蓋於封裝層之整個上表面與晶片之整個背面。
於本發明之另一實施例中，封裝層係包覆凸塊、載 板之上表面以及整個晶片。
根據上述目的，本發明另提供一種製作半導體封裝結構之方法。首先，提供集合載板(panel type substrate)。集合載板具有上表面及下表面。集合載板包含複數個內連接端與複數個外連接端。內連接端與外連接端分別位於上表面與下表面。接著，提供複數個晶片，於晶片上形成複數個凸塊。其後，放置晶片在集合載板之上表面上，使凸塊電性連接晶片及集合載板之內連接端。之後，形成封裝層，以包覆凸塊、晶片及集合載板之上表面。封裝層具有上表面與側面。接著，形成熱膨脹匹配層，以覆蓋於封裝層之整個上表面。其中熱膨脹匹配層之熱膨脹係數與封裝層之熱膨脹係數不同。其後，進行切割製程，用以切割集合載板、熱膨脹匹配層與封裝層，使各晶片彼此獨立，且使熱膨脹匹配層之邊緣與封裝層之邊緣齊平。
綜合上述，本發明藉由熱膨脹匹配層產生整體平衡效果，而減少板翹問題，進而提高產品良率。此外，本發明之製作方法從基板到晶片封裝皆以大板面形式(panel type)進行，因此可批次量產多個半導體封裝結構，進一步提升生產效率、縮短製程時間。
10‧‧‧覆晶封裝結構
16‧‧‧錫球
20‧‧‧電性接點
30‧‧‧導通層
100、200‧‧‧半導體封裝結構
110‧‧‧集合載板
110a‧‧‧上表面
110b‧‧‧下表面
14、111‧‧‧載板
112‧‧‧基板
114‧‧‧內連線
116‧‧‧內連接端
118‧‧‧外連接端
12、120‧‧‧晶片
120a‧‧‧主動面
120b‧‧‧背面
120c‧‧‧側面
122‧‧‧凸塊
18、130‧‧‧封裝層
130a‧‧‧上表面
130c‧‧‧側面
140‧‧‧熱膨脹匹配層
150‧‧‧電性連接元件
1-1’‧‧‧剖面線
2-2’‧‧‧剖面線
第1圖係習知覆晶封裝結構之剖視示意圖。
第2A圖與第2B圖係習知覆晶封裝結構的翹曲問題之剖視示意圖。
第3A圖至第7A圖係表示本發明第一實施例製作半導體封裝結構之方法的俯視示意圖。
第3B圖至第7B圖係表示前述第一實施例之製作方法沿著剖面線1-1'的剖視示意圖。
第8A圖及第9A圖係表示本發明第二實施例製作半導體封裝結構之方法的俯視示意圖。
第8B圖及第9B圖係表示前述第二實施例之製作方法沿著剖面 線2-2'的剖視示意圖。
第10圖係本發明製作半導體封裝結構之方法的流程示意圖。
關於本發明之優點與精神可以藉由以下發明詳述及所附圖式得到進一步的瞭解。本發明較佳實施例之製造及使用係詳細說明如下。必須瞭解的是本發明提供了許多可應用的創新概念，在特定的背景技術之下可以做廣泛的實施。此特定的實施例僅以特定的方式表示，以製造及使用本發明，但並非限制本發明的範圍。
第3A圖至第7A圖係表示本發明第一實施例製作半導體封裝結構100之方法的俯視示意圖；第3B圖至第7B圖係表示前述製作方法沿著剖面線1-1'的剖視示意圖。如第3A圖與第3B圖所示，先提供集合載板110。集合載板110表面定義有上表面110a及下表面110b。集合載板110具有基板112、複數個內連線114、複數個內連接端116、複數個外連接端118。內連接端116與外連接端118分別位於集合載板110的上表面110a與下表面110b，內連線114電性連接內連接端116與外連接端118。集合載板110可以是單層結構基板，也可以是多層結構基板，層數不限。
如第4A圖與第4B圖所示，接著進行晶片連接(die bond)製程與封裝(molding)製程。詳而言之，先提供複數個晶片120。各晶片120表面定義有主動面120a、背面120b與側面120c，在主動面120a上具有複數個電性接點(electrical pad，圖未示)。接著在晶片120之電性接點上形成複數個凸塊122。凸塊122是電性導通元件，例如為錫球(solder ball)。其後以晶片120之主動面120a朝下的方式，將晶片120置放在集合載板110上，使凸塊122電性連接晶片120之電性接點與集合載板110之內連接端116。晶片120可以是半導體晶片、積體電路晶片、發光二極體晶片或其他任何晶片結構。在其他實施例中，在晶片120與集合載板110之間另可包含黏著層(圖未示)，用以將晶片120固著在集合載板110上。之後，在集合載板110上形成封裝層130，以包覆住凸塊122、整個晶片120 及集合載板110之整個上表面110a。封裝層130具有上表面130a。
形成封裝層130之步驟可包含將封裝膠置入模具中(圖未示)，加熱後經由澆道與澆口，注入已放好晶片與載板的模穴，完成壓模程序，接著進行烘烤製程，以固化封裝層130。封裝層130包含第一型環氧樹脂封裝材料(epoxy molding compound，EMC，亦稱為固態封裝材料)，第一型環氧樹脂封裝材料可包含二氧化矽、環氧樹脂、硬化劑與耐燃劑。
如第5A圖與第5B圖所示，接著，形成熱膨脹匹配層140，以覆蓋於封裝層130之整個上表面130a。其中熱膨脹匹配層140之熱膨脹係數與封裝層130之熱膨脹係數不同。
如果封裝結構在不具熱膨脹匹配層140時會向下翹曲(封裝層130朝向集合載板110的方向彎曲，如第2A圖所示)，則本發明會採用熱膨脹係數較封裝層130更大的熱膨脹匹配層140；反之，如果封裝結構在不具熱膨脹匹配層140時會向上翹曲(集合載板110朝向封裝層130的方向彎曲，如第2B圖所示)，則本發明會採用熱膨脹係數較封裝層130更小的熱膨脹匹配層140。
熱膨脹匹配層140可包含第二型環氧樹脂封裝材料、聚酰亞胺(polyimide)，或單純包含環氧樹脂(epoxy)。第二型環氧樹脂封裝材料可包含二氧化矽、環氧樹脂、硬化劑與耐燃劑，並可另包含其他添加劑。其他添加劑例如為觸媒、加速劑、脫膜劑、應力緩和劑與/或著色劑。
第二型環氧樹脂封裝材料之二氧化矽的成份比例約佔68~79%，環氧樹脂約佔10~15%，硬化劑約佔10~15%，耐燃劑約佔1%。第一型與第二型環氧樹脂封裝材料彼此的成份比例不同，因此兩者的熱膨脹係數不同。例如，由於二氧化矽之熱膨脹係數較低，故增加二氧化矽的成份比例時可以降低環氧樹脂封裝材料之熱膨脹係數。其中，熱膨脹匹配層140所使用之環氧樹脂例如為甲酚清漆型環氧樹脂。聚酰亞胺之熱膨脹係數約為28ppm/℃。
形成熱膨脹匹配層140之步驟可包含進行壓合 (lamination)製程或塗布(coating)製程，再進行烘烤製程，以形成封裝體。在烘烤之後，將封裝結構之溫度降低至室溫。
如第6B圖，接著可選擇性地在集合載板110的下表面110b上形成複數個電性連接元件150，電性連接元件150可電性連接外連接端118，使各半導體封裝結構於後續的製程可進一步連接在印刷電路板上(圖未示)。在此，電性連接元件150可以是錫球，即後續形成之半導體封裝結構為球柵陣列封裝。球柵陣列封裝常用來固定並電性連結晶片120與電路板。球柵陣列封裝能提供比其他如雙列直插封裝(Dual in-line package)或四側引腳扁平封裝(Quad Flat Package)容納更多的接腳，具有更短的平均導線長度，故具備更佳的高速效能。另外，在其他實施例中，電性連接元件150亦可以是金、銅等導電凸塊。
於其他實施例中，本發明集合載板110之外連接端118即為接觸點，而後續形成之半導體封裝結構為平面網格陣列封裝(land grid array，LGA)。平面網格陣列封裝特點在於其針腳是位於插座上而非積體電路晶片上。平面網格陣列封裝的晶片120的接觸點能直接被連接到印刷電路板上。與傳統針腳在積體電路上的封裝方式相比，可減少針腳損壞的問題並可增加腳位。
如第7A圖與第7B圖所示，其後進行切割製程，用以切割集合載板110、熱膨脹匹配層140與封裝層130，使各晶片120彼此獨立，以批次完成複數個半導體封裝結構100，並使熱膨脹匹配層140之邊緣與封裝層130之邊緣齊平。切割後的集合載板110成為載板111，承載各別晶片120。透過載板111的扇出(fan out)功能，以確定晶片邏輯閘(logic gate)輸出能達到電路板上邏輯閘輸入的最大數目。
本發明實施例所製作之半導體封裝結構100即如第7B圖所示，半導體封裝結構100包含載板111、晶片120、複數個凸塊122、封裝層130與熱膨脹匹配層140。載板111具有上表面110a及下表面110b，其中在載板111之上表面110a具有複數個內連接端116，以及在下表面110b具有複數個外連接端118。晶片120位於載 板111之上表面110a上。凸塊122用以電性連接晶片120與載板111之內連接端116。封裝層130用以包覆凸塊122、整個晶片120及載板111之上表面110a。封裝層130具有上表面130a與側面130c。熱膨脹匹配層140覆蓋於封裝層130之整個上表面130a，並暴露出封裝層130之側面130c。其中，熱膨脹匹配層140之熱膨脹係數與封裝層130之熱膨脹係數不同，且熱膨脹匹配層140之邊緣與封裝層130之邊緣齊平。由於熱膨脹匹配層140可以整合封裝結構之熱膨脹係數差異，產生整體平衡效果，因此可減少板翹問題。
第8A圖及第9A圖係表示本發明第二實施例製作半導體封裝結構200之方法的俯視示意圖；第8B圖及第9B圖係表示前述製作方法沿著剖面線2-2'的剖視示意圖；第10圖係本發明第二實施例製作半導體封裝結構之方法的流程示意圖。本實施例與第一實施例的不同之處在於，在形成熱膨脹匹配層140之前，更包括薄化封裝層130之步驟。
如第8A圖與第8B圖所示，於形成封裝層130之步驟後，且在形成熱膨脹匹配層140之前，更包括利用化學機械研磨(chemical mechanical polishing，CMP)製程或研磨(grinding)製程來薄化封裝層130之步驟。薄化封裝層130之步驟可暴露出晶片120之背面120b。此時，封裝層130係包覆凸塊122、晶片120之側面120c以及集合載板110之上表面110a。在其他實施例中，薄化封裝層130之步驟亦可不暴露出晶片120之背面120b，而僅是用以減少封裝層130的厚度。
如第9A圖與第9B圖所示，接著形成熱膨脹匹配層140，其後選擇性形成電性連接元件150，再進行切割製程。本實施例之熱膨脹匹配層140係覆蓋於封裝層130之整個上表面130a與晶片120之整個背面120b。
熱膨脹匹配層140除了提供熱應力調整之功能，亦可對半導體封裝結構200提供物理保護、電性保護、污染隔離與水氣隔離。因此，本發明第二實施例可以薄化原有的封裝層130，如此不但可薄化半導體封裝結構200的整體結構，減少封裝層造成的應 力影響，且可維持半導體封裝結構200的封裝保護效果。
本發明藉由熱膨脹匹配層材料的熱膨脹係數產生整體平衡效果，而減少板翹問題，進而提高產品良率。此外，本發明之製作方法從基板到晶片封裝皆以大板面形式進行，因此可批次量產多個半導體封裝結構，進一步提升生產效率、縮短製程時間。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包括於後附之申請專利範圍中。
100‧‧‧半導體封裝結構
111‧‧‧載板
116‧‧‧內連接端
118‧‧‧外連接端
120‧‧‧晶片
120a‧‧‧主動面
120b‧‧‧背面
120c‧‧‧側面
122‧‧‧凸塊
130‧‧‧封裝層
110a、130a‧‧‧上表面
110b‧‧‧下表面
130c‧‧‧側面
140‧‧‧熱膨脹匹配層
150‧‧‧電性連接元件

Claims (9)

  1. 一種半導體封裝結構，包括：一載板，具有一上表面及一下表面，該載板包含複數個內連接端與複數個外連接端，該等內連接端與該等外連接端分別位於該上表面與該下表面；一晶片，位於該載板之該上表面上；複數個凸塊，係用以電性連接該晶片及該載板之該等內連接端；一封裝層，用以包覆該等凸塊、該晶片及該載板之該上表面，該封裝層具有一上表面與至少一側面，該封裝層包含一第一型環氧樹脂封裝材料，其至少含有二氧化矽、環氧樹脂、硬化劑及耐燃劑；以及一熱膨脹匹配層，覆蓋於該封裝層之整個該上表面，並暴露出該封裝層之該至少一側面，其中該熱膨脹匹配層之熱膨脹係數與該封裝層之熱膨脹係數不同，且該熱膨脹匹配層之邊緣與該封裝層之邊緣齊平，該熱膨脹匹配層包含一第二型環氧樹脂封裝材料，其至少含有聚酰亞胺、二氧化矽、環氧樹脂、硬化劑及耐燃劑，其中，該第一型環氧樹脂封裝材料與該第二型環氧樹脂封裝材料具有不同成分比例之二氧化矽、環氧樹脂、硬化劑及耐燃劑。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該晶片具有一背面與至少一側面，該封裝層係包覆該等凸塊、該晶片之側面以及該載板之該上表面，而該熱膨脹匹配層覆蓋於該封裝層之整個該上表面與該晶片之整個該背面。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中該封裝層係包覆該等凸塊、該載板之該上表面以及整個該晶片。
  4. 如申請專利範圍第1項所述之半導體封裝結構，更包含複數個錫球，設置在該載板之該下表面，且與該等外連接端電性連接。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中該載板之該等外連接端為複數個接觸點。
  6. 一種製作半導體封裝結構之方法，包含：提供一集合載板，該集合載板具有一上表面及一下表面，該集合載板包含複數個內連接端與複數個外連接端，該等內連接端與該等外連接端分別位於該上表面與該下表面；提供複數個晶片；於該等晶片上形成複數個凸塊；放置該等晶片在該集合載板之該上表面上，使該等凸塊電性連接該等晶片及該集合載板之該等內連接端；形成一封裝層，以包覆該等凸塊、該等晶片及該集合載板之該上表面，該封裝層具有一上表面與至少一側面，該封裝層包含一第一型環氧樹脂封裝材料，其至少含有二氧化矽、環氧樹脂、硬化劑及耐燃劑；形成一熱膨脹匹配層，以覆蓋於該封裝層之整個該上表面，其中，該熱膨脹匹配層包含一第二型環氧樹脂封裝材料，其至少含有聚酰亞胺、二氧化矽、環氧樹脂、硬化劑及耐燃劑，該第一型環氧樹脂封裝材料與該第二型環氧樹脂封裝材料具有不同成分比例之二氧化矽、環氧樹脂、硬化劑及耐燃劑，使該熱膨脹匹配層之熱膨脹係數與該封裝層之熱膨脹係數不同；以及進行一切割製程，用以切割該集合載板、該熱膨脹匹配層與該封裝層，使該熱膨脹匹配層之邊緣與該封裝層之邊緣齊平。
  7. 如申請專利範圍第6項所述之方法，其中在形成該熱膨脹匹配層之前，更包括利用一化學機械研磨製程或一研磨製程來薄化該封裝層之一步驟。
  8. 如申請專利範圍第7項所述之方法，其中薄化該封裝層之該步驟用以暴露出部分之該晶片，使後續形成之該熱膨脹匹配層覆蓋於該封裝層之整個該上表面與部分之該晶片。
  9. 如申請專利範圍第6項所述之方法，其中形成該熱膨脹匹配層之該步驟包括一壓合製程或一塗布製程。
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