JP2000188369A - 半導体装置 - Google Patents

半導体装置

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Publication number
JP2000188369A
JP2000188369A JP10364155A JP36415598A JP2000188369A JP 2000188369 A JP2000188369 A JP 2000188369A JP 10364155 A JP10364155 A JP 10364155A JP 36415598 A JP36415598 A JP 36415598A JP 2000188369 A JP2000188369 A JP 2000188369A
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JP
Japan
Prior art keywords
semiconductor
semiconductor chip
semiconductor device
chip
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10364155A
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English (en)
Other versions
JP3512657B2 (ja
Inventor
Hiroyuki Juso
博行 十楚
Yoshiki Soda
義樹 曽田
Tomoyo Maruyama
朋代 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18481116&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2000188369(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP36415598A priority Critical patent/JP3512657B2/ja
Priority to US09/460,245 priority patent/US6181002B1/en
Publication of JP2000188369A publication Critical patent/JP2000188369A/ja
Application granted granted Critical
Publication of JP3512657B2 publication Critical patent/JP3512657B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 従来、半導体チップの片側をモールド樹脂で
封止した構造をもつため、半導体チップとモールド樹脂
との間のバイメタル現象により、温度変化した場合、半
導体装置に反りが発生する。この反りにより、半導体装
置とプリント基板との間の接続部分に応力が発生し、接
続部にクラックが発生する。 【解決手段】 絶縁性基板４上に搭載された複数の半導
体チップ１ａ、１ｂのうち、面積の大きい半導体チップ
１ａの厚さが、面積の小さい半導体チップ１ｂの厚さよ
りも厚い。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、高密度実装に適した半導体チップを積層した
樹脂封止型半導体装置に関するものである。
【０００２】
【従来の技術】携帯機器等にメモリ等の付加価値や容量
の増大のために１つのパッケージ内に複数の半導体チッ
プを搭載したパッケージがある。例えば、複数個の半導
体チップを横に配列し搭載したマルチチップモジュール
があるが、半導体チップを横に並べて配列するために、
搭載する半導体チップの総面積よりも小さいパッケージ
の作製は不可能である。
【０００３】一方、複数個の半導体チップを積層させ搭
載することにより、実装密度を高めている構造のパッケ
ージ（以下、「スタックドパッケージ」という。）があ
る。
【０００４】このスタックドパッケージのうち、電気絶
縁基板上に半導体チップを搭載し、その裏面にマトリッ
クス状に外部接続用の端子を備え、ほぼチップサイズの
構造のもの（以下、「ＣＳＰ」という。）がある。
【０００５】図５にＣＳＰ構造の半導体装置の断面図を
示す。図５に示す半導体装置は、積層された各々の半導
体チップの面積が異なる場合、パッケージの外形サイズ
は、最大面積を有する半導体チップに依存する。従来の
半導体装置では積層された半導体チップの厚さについて
は何ら考慮されていないか、又はそれぞれが等しいた
め、ＣＳＰ構造で半導体装置内にただ１つの半導体チッ
プを有する図６に示す構造と比較すると、スタックドパ
ッケージでは回路形成面の面積の小さいチップがあるた
めに、半導体装置内でモールド樹脂に比べて半導体チッ
プが占める体積が小さくなる。
【０００６】
【発明が解決しようとする課題】上述の半導体装置は、
小型で、実装用外部端子がエリアアレイ構造をもつ。こ
のような構造をもつ半導体装置はプリント基板上に、リ
フロー実装され使用される。実装用外部端子がはんだボ
ールを有するＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）構造のものや、台形状でハンダペーストだけで接続
を行うＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）構造
のもの等がある。
【０００７】リフロー実装後にヒートサイクル等により
半導体装置とプリント基板に温度変化が発生すると、半
導体装置の反り、半導体装置とプリント基板との線膨張
係数の違い等により、半導体装置とプリント基板との接
続部に応力が発生する。
【０００８】上述の半導体装置は、半導体チップの片側
をモールド樹脂で封止した構造をもつため、半導体チッ
プとモールド樹脂との間のバイメタル現象により、温度
変化した場合、図７に示すように半導体装置に反りが発
生する。この反りにより、半導体装置とプリント基板と
の間の接続部分に応力が発生し、接続部にクラックが発
生し、更には破断に至る場合がある。
【０００９】
【課題を解決するための手段】請求項１に記載の本発明
の半導体装置は、半導体チップ搭載面側に配線層が形成
され、上記半導体チップ搭載面と反対面側に実装用外部
端子が形成された絶縁性基板上に、上記配線層と電気的
に接続された複数の半導体チップが積層されてなる半導
体装置において、上記半導体チップは、面積の大きい半
導体チップの方が面積の小さい半導体チップに比べて厚
さが厚いことを特徴とするものである。
【００１０】また、請求項２に記載の本発明の半導体装
置は、上記絶縁性基板に形成された配線層が上記半導体
チップ搭載面と反対側にも形成されていることを特徴と
する、請求項１に記載の半導体装置である。
【００１１】
【発明の実施の形態】以下、一実施の形態に基づいて、
本発明を詳細に説明する。
【００１２】図１の本発明の第１の実施の形態の半導体
装置の断面図を示す。絶縁性基板４の半導体チップ搭載
面に配線層３が形成され、その反対面側にはエリアアレ
イ状に配列された外部接続端子６をもつ絶縁性基板４上
に、半導体チップ１ａ、１ｂを搭載し、ワイヤーボンド
により配線基板と半導体チップ１ａ、１ｂとの間の電気
的接続を確保し、その後、トランスファーモールド法に
より、半導体チップ１ａ、１ｂ及びワイヤー２を封止樹
脂５により封止し、貫通穴部分に外部接続端子６とし
て、ハンダボールが接続されている。半導体チップ１ａ
は半導体チップ１ｂに比べて回路形成面の面積が大き
く、且つ、厚い。
【００１３】本発明は、絶縁性基板４上に搭載された複
数の半導体チップ１ａ、１ｂのうち、面積の大きい半導
体チップ１ａの厚さが、面積の小さい半導体チップ１ｂ
の厚さよりも厚いことを特徴とするものである。半導体
チップの厚さは、ダイシング前のウエハ状態での機械研
磨法、ケミカルエッチング法等によって変更する。
【００１４】本実施の形態において、封止樹脂の厚さを
８００μｍ、半導体チップ１ａの厚さを３００μｍ、半
導体チップ１ｂの厚さを１００μｍとした場合と半導体
チップ１ａ、１ｂの厚さをともに２００μｍとした場
合、それぞれについてリフロー実装後の温度サイクル試
験で半導体装置とプリント基板との間の接合部に生じる
応力のシュミレーションを図７を用いて実施した。シュ
ミレーションは一次元で、パッケージ長は１１．００ｍ
ｍ、半導体チップ１ａを９．００ｍｍ、半導体チップ１
ｂを４．８２ｍｍ、ハンダボールを０．８ｍｍピッチで
１２個配置し、１３５℃の温度差を与えた。このとき、
半導体装置とプリント基板との間の応力集中部に発生す
る応力は図９に示すように半導体チップ１ａ、１ｂの厚
さの比を３：１にした場合、リフロー実装後の温度サイ
クル試験時に半導体装置とプリント基板との間に発生す
る応力が、半導体チップ１ａ、１ｂの厚さの比を１：１
にした場合に比べて約９２％に減少することがシュミレ
ーションによって確認され、半導体装置をプリント基板
にリフロー実装した後の信頼性に効果があることが確認
された。
【００１５】図２に半導体チップ１ａ、１ｂ、１ｃを３
段に積層した第２の実施の形態について説明する。
【００１６】半導体チップを３段以上に積層した場合で
も、回路形成面の面積の大きい半導体チップの厚さを厚
くすることで図１に示した場合と同様の効果が得られ
る。
【００１７】図３に半導体チップを３段に積層し、最下
層の半導体チップ１ｄと絶縁性基板４の配線層との接続
をフリップチップ方式で接続した実施の形態の断面図で
ある。
【００１８】本実施の形態において、半導体チップ１ａ
が半導体チップ１ｂ、１ｄより回路形成面の面積が大き
いので、厚くしている。このように、面積の大きい半導
体チップが最下層にない場合でも、面積が最大の半導体
チップを厚くすることで同じ効果が得られる。
【００１９】図４に本発明の他の実施の形態としての、
配線基板として絶縁性基板の両面に配線層がある両面配
線板を用い、半導体チップ１ａをフリップチップ接続し
たＬＧＡ構造の半導体装置の断面図である。両面配線板
は表裏の配線がスルーホールで接続されている。図８は
絶縁性基板の配線層が多層の場合の半導体装置の断面図
を示している。いずれも回路形成面の大きいチップを厚
くしている。このようにすることにより、半導体装置内
において、モールド樹脂に比べて半導体チップの占める
体積を大きくすることにより、応力を小さくしている。
【００２０】本発明において、絶縁性基板の材質、半導
体チップと絶縁性基板との間の電気的接続方法、半導体
チップとプリント基板とのダイボンド方式、外部接続端
子の形状等は特に限定されない。絶縁性基板は耐熱性に
優れた樹脂基板又はフィルムで材質は特に限定されな
い。例えば、ポリイミド、ガラスエポキシ、ＢＴ（ビス
マレイド・トリアジン）レジン、ポリエステル、ポリア
ミド、テプロン、セラミック、ガラスポリエステル等の
樹脂基板が上げられる。配線層数も基材に外部接続端子
を接続するための貫通穴を開けた１層配線板、スルーホ
ールにより両面配線を接続した両面配線板や図８に示す
ように配線層が多層になっている多層基板等が挙げられ
る。半導体チップを絶縁性基板上の配線層に接続する方
法も特に限定はない。１層目の半導体チップと絶縁性基
板との接続は、フェイスダウンのフリップフロップ方
式、フェイスアップのワイヤーボンド方式等が挙げられ
る。
【００２１】また、２層目より上の半導体チップについ
ては絶縁性基板へのワイヤーボンド、下層の半導体チッ
プ上の再配線へのフリップチップ方式、ワイヤーボンド
方式による接合などが挙げられる。外部接続端子の形状
は、ハンダボールを使用したＢＧＡタイプや多層絶縁性
基板を用いたＬＧＡタイプなどが挙げられる。
【００２２】
【発明の効果】以上、詳細に説明したように、本発明を
用いることにより、チップサイズパッケージにおいて
も、実装後の信頼性を従来より改善した半導体装置を提
供することができる。
【００２３】また、請求項２に記載の本発明を用いるこ
とにより、より配線のレイアウトの自由度が向上する。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態の半導体装置の断面
図である。
【図２】本発明の第２の実施の形態の半導体装置の断面
図である。
【図３】本発明の第３の実施の形態の半導体装置の断面
図である。
【図４】本発明の第４の実施の形態の半導体装置の断面
図である。
【図５】第１の従来技術による半導体装置の断面図であ
る。
【図６】第２の従来技術による半導体装置の断面図であ
る。
【図７】半導体装置の反りの発生するメカニズムの説明
に供する図である。
【図８】多層配線基板を用いた本発明の実施の形態の半
導体装置の断面図である。
【図９】半導体チップの厚さの比と応力集中部に発生す
る応力の比との関係を示す図である。
【符号の説明】
１ａ、１ｂ、１ｃ、１ｄ 半導体チップ ２ Ａｕワイヤー ３ 配線層 ４ 絶縁性基板 ５ 封止樹脂 ６ 外部接続端子 ７ フリップチップ接続用端子 ８ プリント基板 ９ スルーホール １０ 実装用ランド

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 半導体チップ搭載面側に配線層が形成さ
    れ、上記半導体チップ搭載面と反対面側に実装用外部端
    子が形成された絶縁性基板上に、上記配線層と電気的に
    接続された複数の半導体チップが積層されてなる半導体
    装置において、 上記半導体チップは、面積の大きい半導体チップの方が
    面積の小さい半導体チップに比べて厚さが厚いことを特
    徴とする半導体装置。
  2. 【請求項２】 上記絶縁性基板に形成された配線層が上
    記半導体チップ搭載面と反対側にも形成されていること
    を特徴とする、請求項１に記載の半導体装置。
JP36415598A 1998-12-22 1998-12-22 半導体装置 Expired - Lifetime JP3512657B2 (ja)

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JP36415598A JP3512657B2 (ja) 1998-12-22 1998-12-22 半導体装置
US09/460,245 US6181002B1 (en) 1998-12-22 1999-12-13 Semiconductor device having a plurality of semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36415598A JP3512657B2 (ja) 1998-12-22 1998-12-22 半導体装置

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951774B2 (en) 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US7135353B2 (en) 2003-09-09 2006-11-14 Samsung Electronics Co., Ltd. Apparatus for stacking semiconductor chips, method for manufacturing semiconductor package using the same and semiconductor package manufactured thereby
US7405485B2 (en) 2004-06-16 2008-07-29 Rohm Co., Ltd. Semiconductor device
JP2012089904A (ja) * 2012-02-10 2012-05-10 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法

Families Citing this family (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1040397A (en) * 1996-12-04 1998-06-29 Hitachi Limited Semiconductor device
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP2000294692A (ja) * 1999-04-06 2000-10-20 Hitachi Ltd 樹脂封止型電子装置及びその製造方法並びにそれを使用した内燃機関用点火コイル装置
JP3521325B2 (ja) * 1999-07-30 2004-04-19 シャープ株式会社 樹脂封止型半導体装置の製造方法
KR20010037247A (ko) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
JP2001127246A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
KR100421774B1 (ko) * 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US6621155B1 (en) 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
JP3768761B2 (ja) * 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6252305B1 (en) * 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US7122889B2 (en) * 2000-05-03 2006-10-17 Rambus, Inc. Semiconductor module
US6833984B1 (en) * 2000-05-03 2004-12-21 Rambus, Inc. Semiconductor module with serial bus connection to multiple dies
JP2002076250A (ja) * 2000-08-29 2002-03-15 Nec Corp 半導体装置
JP2002204053A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 回路実装方法、回路実装基板及び半導体装置
US6503776B2 (en) * 2001-01-05 2003-01-07 Advanced Semiconductor Engineering, Inc. Method for fabricating stacked chip package
KR100731007B1 (ko) * 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지
US6900549B2 (en) * 2001-01-17 2005-05-31 Micron Technology, Inc. Semiconductor assembly without adhesive fillets
SG100635A1 (en) 2001-03-09 2003-12-26 Micron Technology Inc Die support structure
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
US6798055B2 (en) 2001-03-12 2004-09-28 Micron Technology Die support structure
SG95637A1 (en) * 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) * 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
KR100393448B1 (ko) * 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme
US6597059B1 (en) 2001-04-04 2003-07-22 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package
US6586825B1 (en) * 2001-04-26 2003-07-01 Lsi Logic Corporation Dual chip in package with a wire bonded die mounted to a substrate
JP4149377B2 (ja) 2001-06-07 2008-09-10 株式会社ルネサステクノロジ 半導体装置の製造方法
US6700794B2 (en) * 2001-07-26 2004-03-02 Harris Corporation Decoupling capacitor closely coupled with integrated circuit
US6916682B2 (en) 2001-11-08 2005-07-12 Freescale Semiconductor, Inc. Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
EP1455392A4 (en) * 2001-12-07 2008-05-07 Fujitsu Ltd SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
US6858932B2 (en) 2002-02-07 2005-02-22 Freescale Semiconductor, Inc. Packaged semiconductor device and method of formation
US6721189B1 (en) * 2002-03-13 2004-04-13 Rambus, Inc. Memory module
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7061088B2 (en) * 2002-10-08 2006-06-13 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
KR100618812B1 (ko) * 2002-11-18 2006-09-05 삼성전자주식회사 향상된 신뢰성을 가지는 적층형 멀티 칩 패키지
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
JP2004296719A (ja) * 2003-03-26 2004-10-21 Renesas Technology Corp 半導体装置
US7217597B2 (en) 2004-06-22 2007-05-15 Micron Technology, Inc. Die stacking scheme
US7250684B2 (en) * 2004-06-30 2007-07-31 Intel Corporation Circular wire-bond pad, package made therewith, and method of assembling same
JP4601365B2 (ja) * 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
TWI303873B (en) 2005-09-23 2008-12-01 Freescale Semiconductor Inc Method of making stacked die package
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7323968B2 (en) * 2005-12-09 2008-01-29 Sony Corporation Cross-phase adapter for powerline communications (PLC) network
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
JP5947165B2 (ja) * 2012-09-05 2016-07-06 ルネサスエレクトロニクス株式会社 電子装置
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US10629519B2 (en) * 2016-11-29 2020-04-21 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11495505B2 (en) 2019-06-03 2022-11-08 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
US11398455B2 (en) * 2019-06-03 2022-07-26 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993023982A1 (en) * 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
JPH09186289A (ja) * 1995-12-28 1997-07-15 Lucent Technol Inc 多層積層化集積回路チップ組立体
KR100443484B1 (ko) * 1996-02-19 2004-09-18 마츠시타 덴끼 산교 가부시키가이샤 반도체장치및그제조방법
US5953588A (en) * 1996-12-21 1999-09-14 Irvine Sensors Corporation Stackable layers containing encapsulated IC chips

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951774B2 (en) 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
KR100818423B1 (ko) * 2001-04-06 2008-04-01 가부시키가이샤 히타치세이사쿠쇼 반도체 장치 및 그 제조 방법
US7135353B2 (en) 2003-09-09 2006-11-14 Samsung Electronics Co., Ltd. Apparatus for stacking semiconductor chips, method for manufacturing semiconductor package using the same and semiconductor package manufactured thereby
US7374966B2 (en) 2003-09-09 2008-05-20 Samsung Electronics Co., Ltd. Apparatus for stacking semiconductor chips, method for manufacturing semiconductor package using the same and semiconductor package manufactured thereby
US7405485B2 (en) 2004-06-16 2008-07-29 Rohm Co., Ltd. Semiconductor device
JP2012089904A (ja) * 2012-02-10 2012-05-10 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法

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