JP3239909B2 - 積層可能な三次元マルチチップ半導体デバイスとその製法 - Google Patents

積層可能な三次元マルチチップ半導体デバイスとその製法

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Publication number
JP3239909B2
JP3239909B2 JP06252693A JP6252693A JP3239909B2 JP 3239909 B2 JP3239909 B2 JP 3239909B2 JP 06252693 A JP06252693 A JP 06252693A JP 6252693 A JP6252693 A JP 6252693A JP 3239909 B2 JP3239909 B2 JP 3239909B2
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JP
Japan
Prior art keywords
carrier substrate
chip carrier
solder
semiconductor die
solder bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP06252693A
Other languages
English (en)
Other versions
JPH0613541A (ja
Inventor
ポ−ル・ティ−・リン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Solutions Inc
Motorola Inc
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Filing date
Publication date
Application filed by Motorola Solutions Inc, Motorola Inc filed Critical Motorola Solutions Inc
Publication of JPH0613541A publication Critical patent/JPH0613541A/ja
Application granted granted Critical
Publication of JP3239909B2 publication Critical patent/JP3239909B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01014—Silicon [Si]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/14—Integrated circuits
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dram (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は一般に半導体デバイスに
関し、具体的には積層可能な３次元半導体マルチチップ
・モジュールに関する。
【０００２】
【従来の技術】現在、ほとんどの大規模集積回路（Ｉ
Ｃ）は、プラスチックもしくはセラミック製のパッケー
ジに封止されており、このパッケージからプリント回路
（ＰＣ）板にはんだづけするため、またはソケットに挿
入するための金属リードが伸びている。通常、これらの
ＩＣパッケージはデュアル・イン・ライン（ＤＩＰ）ま
たはカッド・フラット（quad-flat ）パッケージとして
構成されている。大抵の例では、１個のＩＣだけが１つ
のパッケージ内に入れられているが、時には１つのパッ
ケージの中に複数のチップが入れられることもある。セ
ラミックもしくはプラスチックのパッケージは、特にソ
ケットを使用する場合、実装表面（通常はプリント回路
板）の面積を比較的喰わないので、このようなパッケー
ジ技術の結果、回路密度はそれほど高くならない。
【０００３】またプリント回路板は、電子機器の他のあ
らゆるものと同様、小型化、高速化、高密度化してい
る。実装面積が限られている場合、または速度に関する
考慮要件から回路素子を近接して設置することが要求さ
れる場合には、よりコンパクトなパッケージ技術が必要
とされる。このような技術は、コファイアド（cofired
セラミック基板をの使用する構成をとっており、この基
板の上にＩＣが未パッケージ形態でセラミック実装表面
に直接接着され、この実装表面の導電領域にワイヤボン
ディングされるか、または反転されて、たとえばはんだ
バンプ技術によってセラミック実装表面上のメタライズ
領域に直接接続される。しかしながらこのマルチチップ
・モジュール（ＭＣＭ）技術にはいくつかの限界があ
る。１つのセラミック実装表面上で複数のＩＣを相互接
続するには、望ましくはクロスオーバを回避するような
パターンで、金属材料を被着する必要がある。また多く
の表面では、きわめて精細な解像度の金属導体の被着は
難しい。多層相互接続も可能であるが、時にはひどく高
い費用がかかることがあり、空気冷却下では、熱的許容
損失機能に限界がある。またチップの直接接着は、モジ
ュール組立前のバーンイン機能がないという制約があ
り、基板実装後の修理も難しい。さらに、能動、受動を
問わず回路に対して部品が必要な場合、これに伴うサイ
ズおよび実装機構の問題から、個別部品を使用しなけれ
ばならない。
【０００４】にも拘らずＭＣＭの出現は、ＩＣのパッケ
ージングに目ざましい利点をもたらす。チップ間の時間
遅延が少なくなり、電気ノイズおよびクロストークが減
少し、サイズが小さくなる。また使用するチップを大き
くすることができ、マルチチップ・モジュール当たりの
Ｉ／Ｏリード・カウントが大幅に増大する。しかしなが
らこれら種々の利点にも拘らず、現在のＭＣＭは一連の
問題を抱えている。熱管理の問題が大きくなっているの
である。複数デバイスから発生する熱は除去しなければ
ならない。１個のチップ上のゲートの密度が高まるにつ
れ、ダイから、ダイ接着剤，基板，ヒートシンクまでの
熱通路全体を考慮に入れるべきである。単結晶シリコ
ン、ならびに窒化アルミニウムや炭化珪素など熱伝導性
セラミックは、従来のセラミック材料およびプリント回
路板材料に比べて熱伝達機能や熱平均化機能が優れてい
る。また熱の漸次変化も、はんだ，ワイヤボンドおよび
電気接続の信頼性に大きな影響を与える。実際、ＭＣＭ
設計を成功させるには、個別的に最も効果的な導電性を
有する材料と、集団的に熱膨張係数が似通っている材料
との間で、バランスをとらなければならない。
【０００５】従来、すべてのダイは組立前に一つ一つプ
ローブで検査する一方、重要なユニットは、エージング
を加速した条件下でバーンインを行って、後のシステム
障害発生リスクを最小限にする。バーンインは弱いデバ
イスをふるい落とすために実施するもので、通常は裸チ
ップよりもむしろパッケージされたデバイスに対してバ
ーンインを行う。ほとんどのバーンイン障害は、弱い酸
化ゲートを原因とするデバイスもしくはダイに関連する
ものである。ＭＣＭに対してバーンインを採用する場
合、このプロセスは、パッケージされたモジュール・レ
ベルで実施すべきである。モジュール・レベルでのバー
ンインの欠点は、モジュール内の１パーセントのダイが
障害を起こすことで、適切な取り外し手順によって、別
の良好なダイと交換しなければならない。
【０００６】もう１つのＭＣＭアプローチでは、ＸＹ平
面ではなく、Ｚ軸に沿って裸チップを相互接続する。３
次元パッケージングは、平面マルチチップ基板に比べ
て、より高いメモリ密度を提供し、必要な相互接続密度
を減らしている。その結果、ＭＣＭ，個別部品および受
動部品をリンクする接続システムは、基板に対し直角を
なすＺ軸方向に伸びると予想される。ＩＣの３次元パッ
ケージングは、多くの分野で利点をもたらす。たとえ
ば、速度と高密度化が重要なスーパーコンピュータのメ
モリ、或いはアクセス時間と高密度化が重要な大規模キ
ャッシュ・メモリに、役立てることができる。
【０００７】裸チップを相互接続する１つの方法はチッ
プを積み重ねて１つのキューブを形成することである。
チップは、キューブを形成する前に予め、金線によっ
て、一つ一つ、ＴＡＢフィルムと同一の薄膜上で相互接
続される。電気試験およびバーンインに合格した後、そ
れらは、ＴＡＢフィルムを使って、それぞれの上に積み
重ねられて接着される。この構成のいちばんの欠点は熱
放散が制限されることである。またいったんこのチップ
のキューブが形成されて基板の上に実装されると、後の
チップ故障の再加工がきわめて実施しにくくなり、積層
内に冗長チップを含めるので、モジュール全体のコスト
が高くなる。
【０００８】超高密度ＭＣＭは、平面マルチチップ・モ
ジュールに、この３次元アプローチを理想的に組み込む
ものである。ピン・グリッド・アレイ（Pin Grid Array
s ）（ＰＧＡ）を積層してＭＣＭを形成する方法は、２
０年前からあった。下部基板には従来の方法で、銅ピン
が付けられる。半導体ダイはついで、チップ・キャリヤ
基板にフリップ・チップ実装される。挿入器（interpos
er）は、相互接続をはんだ接合する方法によって、チッ
プ・キャリヤ基板を別のチップ・キャリヤまたは下部基
板に物理的および電気的に結合する。これらの相互接続
は各基板の周辺に位置しており、このことによってチッ
プ構成、ひいては各レベルにおけるチップ密度が制限を
受けやすくなる。ＰＧＡの銅ピンと挿入器は、キャリヤ
間にスタンドオフを提供し、互いに破損し合わないよう
に保っている。
【０００９】
【発明が解決しようとする課題】このためＭＣＭの設計
を成功させるには、電力配分，熱放散および温度をはじ
め、試験，バーンインおよび再加工を考慮に入れるべき
である。ＭＣＭの設計の難しさは、電気特性，機械特性
および熱特性が適正に配合された材料をみつけて組み立
てることである。トレードオフはほとんど常に必要であ
り、それもアプリケーションによって異なるのが普通で
ある。以上述べた設計基準のすべてを満足すると共にコ
スト効果の高い、製造の容易な超高密度ＭＣＭに対する
ニーズが存在する。
【００１０】
【課題を解決するための手段】本発明に基づき、下方チ
ップ・キャリヤ基板，上方チップ・キャリヤ基板および
半導体ダイを有する積層半導体マルチチップ・モジュー
ルが提供される。下方チップ・キャリヤは熱伝導性材料
で作られており、上面と底面の両方に複数のはんだバン
プを有している。上方チップ・キャリヤ基板も熱伝導性
材料で作られており、その底面に複数のはんだバンプを
有している。半導体ダイは、基板当たり少なくとも１個
の割合で、下方および上方チップ・キャリヤ基板に対し
て、電気的および物理的に接着される。上記およびその
他の特性ならびに利点は、添付図面と合わせて、以下の
詳細な説明からより明確に把握されよう。指摘すべき重
要なことは、図は必ずしも正確な縮尺で示されているわ
けではないこと、また具体的に示していない本発明の他
の実施例も存在し得ることである。
【００１１】
【実施例】本発明を用いれば、先に述べた３次元マルチ
チップ・モジュールの望ましい特性を満足して、ＸＹ平
面の基板面積を余り犠牲にせずに、半導体を高密度にパ
ッケージすることができる。本発明は、マルチチップ・
モジュールをＺ軸方向に積層することを可能にする。さ
らに本発明はこのようなモジュールを製造する方法を提
供する。はんだリフロー前の、本発明に基づく積層マル
チチップ・モジュール８の断面図を図１に示す。半導体
ダイ１０は、下方チップ・キャリヤ基板１２の上に実装
される。半導体ダイ１０と、下方チップ・キャリヤ基板
１２との間の電気接続は、従来のやり方でワイヤ１３を
ボンディングすることによって行う。また半導体ダイ１
０は封止材１４によって封止され、これは封止樹脂もし
くはグロブ・トップ（glob top）などの従来の封止材、
またはその他の適切な材料で作ることができる。下方チ
ップ・キャリヤ基板１２は、窒化アルミニウムまたはシ
リコンなど熱伝導性材料によって形成するのが望まし
い。ＦＲ−４などのプリント回路板材も使用できるが、
この材料は、セラミックまたはシリコンほど熱伝導性が
ない。ＰＣ板材を選択する場合には、熱膨張の大きな食
い違いも考慮に入れなければならない。しかしながら低
コストであることは、ユーザが受け入れる充分な動機に
なろう。
【００１２】また図１に示すように、下方チップ・キャ
リヤ基板１２は、基板の底面に複数のはんだバンプ１５
を有している。これらのはんだバンプ１５は、下方チッ
プ・キャリヤ基板１２を、実際のＰＣ板（図示していな
い）に実装するのに用いられる。さらに下方チップ・キ
ャリヤ基板１２は基板の上面にも複数のはんだパッドま
たはバンプ１６を有している。はんだパッド１６は下方
チップ・キャリヤ基板１２を、この上に実装する別のチ
ップ・キャリヤに結び付ける働きをする。
【００１３】また図１に、上方チップ・キャリヤ基板２
０の上に実装されたもう一つの半導体ダイ１８を示す。
半導体ダイ１８と上方チップ・キャリヤ基板２０との間
の電気接続は、基板に対してＴＡＢボンディングされた
ワイヤ２１によって行う。また半導体ダイ１８は封止材
２２によって封止され、これは封止樹脂もしくはグロブ
・トップなどの従来の封止材、またはその他の適切な材
料で作ることができる。下方チップ・キャリヤ基板１２
と上方チップ・キャリヤ基板２０がはんだ接合のために
適正に整合されると、はんだバンプ１６，２３が結合し
て、小型はんだ柱を形成する。
【００１４】この実施例では、下方チップ・キャリヤ基
板１２および上方チップ・キャリヤ基板２０は、相互の
電気接続および他の基板との電気接続を行うために、ス
ルーホール・バイア２４を有している。しかしながら多
層チップ・キャリヤ基板も、別の基板との電気接続を作
るという同じ目的に使用できる。
【００１５】図２に、積層マルチチップ・モジュール２
５の断面図を示す。この実施例の機構の多くは、図１で
検討したのと全く同じであるので、同じ番号が付けられ
ている。この実施例では、下方チップ・キャリヤ基板２
６の上には、１個の半導体デバイス２７が実装されてい
る。熱伝導性のふた２８が半導体デバイス２７を覆って
いる。ふた２８は、砂時計形状のはんだ接合２９を作る
ためのスタンドオフ凸起の働きもできる。この砂時計形
状は、疲れ応力によりはんだ接合２９の障害が発生する
までの時間を最大限引き延ばす。図１で述べたはんだバ
ンプまたはパッド１６，２３のサイズは、はんだ接合２
９の砂時計形状を達成するため、ふたの高さに従って最
適化する必要がある。ふたが適所にないと、上部および
底部のはんだバンプが、はんだリフロー工程の間に合体
して、大きな１個のはんだバンプを形成する。この形状
でも許容できるが、砂時計形状の方が耐久寿命にとって
より望ましい。上方チップ・キャリヤ基板３０の上に
は、２個の半導体デバイス３２，３４がスタガ構成で実
装されている。ヒートシンク４０は、上方チップ・キャ
リヤ基板３０に接着されており、このヒートシンクで下
方半導体デバイス２７からの熱を、熱伝導性の上方チッ
プ・キャリヤ基板３０およびふた２８を介して、放散で
きる。注意すべきことは、第３レベル・チップ・キャリ
ヤを使用する場合には、さらに上のレベル半導体デバイ
スともスタガリングして、下のレベル半導体デバイスか
らの熱を放散させるために、ヒートシンクを接着できる
ようにしなければならないことである。第２ヒートシン
ク４１は、ヒートシンク４０の上に実装されて、積層冷
却フィン構成を形成する。ＭＣＭの熱放散水準を高める
ために、ヒートシンク４１の上にさらにヒートシンクを
付加することも完全に可能であり、その際、ＭＣＭを実
装するＰＣ板上の利用可能な容積が制限されるだけであ
る。
【００１６】また３次元ＭＣＭを作るためにチップ・キ
ャリヤを積層する方法も、本発明に基づくものである。
図３に、部分的にポピュレートされた（populated ）チ
ップ・キャリヤ４２の断面図を示す。図３に示すよう
に、半導体デバイス４４は、チップ・キャリヤ基板４６
の上に実装される。図ではチップ・キャリヤ基板４６は
多層となっている。注意すべきことは、いずれの実施例
のチップ・キャリヤ基板も、デバイスと基板との電気接
続を可能にするために、多層にしたり、またはスルーホ
ール・バイアを持つようにできることである。ついで、
特定のはんだ組成を有する複数のはんだバンプまたはボ
ール２３を、チップ・キャリヤ基板４６の底面上に被着
する。たとえばこのはんだは、鉛と錫の比率が８０：２
０の組成、またはその他の実際的なはんだ合金組成をと
ってもよい。電気接続は、半導体デバイス４４とはんだ
バンプ２３との間に多層相互接続４７を介して作られ
る。チップ・キャリヤ４２は、はんだバンプ２３を被着
する前もしくは後に、試験およびバーンインを実施でき
る。
【００１７】図４に、完全にポピュレートされたチップ
・キャリヤ４８の断面図を示す。半導体デバイス５０
は、チップ・キャリヤ基板５２の上に実装される。図４
に示すように、半導体デバイス５０は、Ｃ４法はんだバ
ンプ５３によって、基板５２の上に実装されたパッド・
アレイ・キャリヤ（Pad Array Carrier ）（ＰＡＣ）と
して示されるが、他の実施可能な実装方法も使用でき
る。複数のはんだバンプまたはボール１６は、はんだバ
ンプ２３とは異なる組成であることが望ましく、チップ
・キャリヤ基板５２の上面に被着される。はんだバンプ
１６は鉛と錫の比率が６０：４０または別の比率の合金
組成で作ることができる。各チップ・キャリヤ基板の上
に、異なる合金組成のはんだを使用する理由は、再加工
を容易にし、後続のはんだリフローにおけるはんだ接合
の再溶解を防止するためである。考えられる後続のリフ
ロー動作段階の一例は、第３キャリヤをマルチチップ・
モジュールの上に積層することである。集束光線を用い
てはんだ接合を除去するので、再加工も簡単にできる。
そのため、はんだの再溶解の間、はんだおよび基板の他
のインタフェースを阻害しないことが望ましい。チップ
・キャリヤ基板５２の上部にあるはんだバンプ１６のほ
かに、複数のはんだバンプ１５も、基板５２の底面に被
着される。これらのはんだバンプ１６は、完全なＭＣＭ
を、ＰＣ板（図示していない）に実装するのに使用され
る。ここでもこれらはんだバンプは、先に述べた理由か
ら、はんだバンプ２３または、はんだバンプ１６とは異
なる組成であることが望ましい。
【００１８】チップ・キャリヤ４２，４８はそれぞれ、
積層ＭＣＭを組み立てる前に、別個に試験およびバーン
インが実施できる。図５に、本発明の１つの実施例、す
なわち積層３次元ＭＣＭ４９を示す。積層工程におい
て、２つのチップ・キャリヤ基板４６，５２ならびに特
にはんだバンプ１６，２３の配列を、はんだリフローの
前に互いに適正に整合すべきである。図１に、適正な整
合の例を示す。はんだリフロー・プロセスでは、図５に
示すように、はんだバンプ１６，２３が合体して、１個
のはんだ接合柱５８を形成する。上部および底部のはん
だバンプを共に溶融して、銅ピンの場合のように、接合
の弱いポイントなしに、１個の相互接続を形成するの
で、この構成は、２個の銅ピンを接合するはんだよりも
より信頼性の高いものになるはずである。
【００１９】本発明の１つのバリエーションを図６に示
す。積層ＭＣＭ５９の断面図を示す。熱伝導性のふた６
０をこの積層構成に付加して、はんだ接合２９のための
スタンドオフを形成している。ふた６０が課す物理的制
約のために、はんだ接合２９は砂時計形状をとってお
り、この形状は、接合の端に集中している応力が減少す
るので、接合の耐久寿命を長くする。
【００２０】積層ＭＣＭを作るプロセスのいちばんの利
点は、モジュールを組み立てる前に、各レベルのチップ
・キャリヤに対し、組立、試験、バーンインが実施でき
ることである。そのためコスト増につながる不良品や冗
長チップ・セットの使用が回避できる。また本発明の再
加工も簡単に実施できる。はんだ接合またははんだ柱は
局部的に熱風をあてる方法により、それぞれ取り外して
再接合できる。
【００２１】上記の説明およびここに含まれる図は、本
発明に関連する多くの利点を示している。またこの３次
元ＭＣＭの構成は、効率的な熱放散ユニットであること
が明かとなった。はんだ柱の配列は、モジュールからの
自然熱対流を促進するための冷却フィンの働きをする。
本発明に基づき、先に述べたニーズおよび利点を完全に
満足する積層可能な３次元マルチチップ・モジュールが
提供されることが明かとなる。本発明は、具体的な実施
例を参照して説明しているが、本発明がこれら図示した
実施例に限定されることを意図するものではない。当業
者は、本発明の意図から逸脱せずに、変形およびバリエ
ーションが可能なことを認めよう。たとえば、ダミーの
はんだバンプも、下方チップ・キャリヤを機械的にサポ
ートするのに使用でき、その際、積層３次元ＭＣＭの電
気特性、または積層構成のＸＹ平面におけるスペース節
約の利点のいずれかに影響を及ぼすことはない。また注
意すべき重要なことは、本発明は決して、積層パッド配
列キャリヤのみに限定するものではなないことである。
パッケージされた半導体デバイスをチップ・キャリヤ基
板に実装し、電気的に結合する適切な方法で、なおかつ
基板の積層を可能にする方法ならいずれを利用してよ
い。したがって本発明は、添付請求の範囲に属するすべ
てのバリエーションおよび変形を包含することを意図し
ている。
【図面の簡単な説明】
【図１】本発明に基づく積層３次元半導体マルチチップ
・モジュール（ＭＣＭ）の、はんだリフロー前の断面図
である。
【図２】ヒートシンクを有する積層３次元半導体ＭＣＭ
の断面図であり、本発明の１つの実施例を示している。
【図３】基板の下部表面上にはんだバンプを有するチッ
プ・キャリヤ基板に実装された半導体デバイスの断面図
であり、本発明に基づき、３次元半導体ＭＣＭを組み立
てる１つの段階を示している。
【図４】基板の下部および上部表面の両方にはんだバン
プを有するチップ・キャリヤ基板の上に実装された半導
体デバイスの断面図であり、本発明に基づき、３次元半
導体ＭＣＭを組み立てる１つの段階を示している。
【図５】積層３次元半導体ＭＣＭの断面図であり、本発
明の１つの実施例を示している。
【図６】下方半導体デバイスを覆うふたを備えた積層３
次元半導体マルチチップ・モジュールの断面図であり、
本発明の１つの実施例を示している。
【符号の説明】
８ 積層可能なマルチチップ・モジュール １０ 半導体ダイ １２ 下方チップ・キャリヤ基板 １３ ワイヤ １４ 封止材 １５ はんだバンプ １６ はんだパッド １８ 半導体ダイ ２０ 上方チップ・キャリヤ基板 ２２ 封止材 ２３ はんだバンプ／ボール ２４ スルーホール・バイア ２５ 積層マルチチップ・モジュール ２６ 下方チップ・キャリヤ基板 ２７ 半導体デバイス ２８ ふた ２９ はんだ接合 ３０ 上方チップ・キャリヤ基板 ３２，３４ 半導体デバイス ４０，４１ ヒートシンク ４２ チップ・キャリヤ ４４ 半導体デバイス ４６ チップ・キャリヤ基板 ４７ 多層相互接続 ４８ チップ・キャリヤ ４９ 積層３次元ＭＣＭ ５０ 半導体デバイス ５２ チップ・キャリヤ基板 ５３ はんだバンプ ５８ はんだ接合柱 ５９ 積層ＭＣＭ ６０ ふた
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−37248（ＪＰ，Ａ) 特開 平５−335478（ＪＰ，Ａ) 特開 昭55−165661（ＪＰ，Ａ) 特開 平２−174255（ＪＰ，Ａ) 実開 平２−127040（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/00 - 25/18

Claims (3)

    (57)【特許請求の範囲】
  1. 【請求項１】 積層半導体マルチチップ・モジュールで
    あって： 熱伝導性材料でできており、底部表面と、上部表面と、
    前記底部表面上にある第１はんだバンプ（１５）とを有
    する下方チップ・キャリヤ基板； 前記下方チップ・キャリヤ基板に電気的および物理的に
    取り付けられた第１半導体ダイ； 第１半導体ダイを封入する封止材； 熱伝導性材料でできており、底部表面および上部表面を
    有する上方チップ・キャリヤ基板； 上方チップ・キャリヤ基板に取り付けられ電気的に結合
    された第２半導体ダイ；ならびに下方チップ・キャリア
    基板と上方チップ・キャリア基板との間にあり、下方チ
    ップキャリヤ基板の上部表面に沿ってのみ下方チップキ
    ャリヤ基板に接触し、上方チップキャリヤ基板の底部表
    面に沿ってのみ上方チップキャリヤ基板に接触する第２
    はんだバンプであって、前記封止材は下方チップ・キャ
    リヤ基板と上方チップ・キャリア基板との間の分離体と
    して機能する、ところの第２はんだバンプ； によって構成されることを特徴とする積層半導体マルチ
    チップ・モジュール。
  2. 【請求項２】 積層半導体マルチチップ・モジュールで
    あって： 熱伝導性材料でできており、上部表面および底部表面の
    両方に複数のはんだバンプを有する、下方チップ・キャ
    リヤ基板； 前記下方チップ・キャリヤ基板に電気的および物理的に
    取り付けられた第１半導体ダイ； 熱伝導性材料でできており、上部表面および底部表面を
    有する、上方チップ・キャリヤ基板； 前記上方チップ・キャリヤ基板の底部表面にある複数の
    はんだバンプ； 前記上方チップ・キャリヤ基板に取り付けられ電気的に
    結合された第２半導体ダイであって、前記下方チップ・
    キャリヤ基板と前記上方チップ・キャリヤ基板とがはん
    だ接合によって互いに電気的に接続されている、ところ
    の第２半導体ダイ；ならびに前記第1 半導体ダイを覆っ
    ており、前記上方チップ・キャリア基板と前記下方チッ
    プ・キャリア基板との間の分離体として機能する、とこ
    ろのふた； によって構成されることを特徴とする積層半導体マルチ
    チップ・モジュール。
  3. 【請求項３】 積層可能な半導体マルチチップ・モジュ
    ールを製造する方法であって： 熱伝導性材料でできた下方チップ・キャリヤ基板を設け
    る段階； 前記下方チップ・キャリヤ基板の上部表面に第１の複数
    のはんだバンプを付着させる段階；前記下方チップ・キャリヤ基板の底部表面に第２の複数
    のはんだバンプを付着させる段階； 第１半導体ダイを前記下方チップ・キャリヤ基板上に取
    り付け、前記下方チップキャリヤ基板に電気的に接合す
    る段階； 熱伝導性材料ででき、上部表面および底部表面を有する
    上方チップ・キャリヤ基板を設ける段階； 前記上方チップ・キャリヤ基板の底部表面上に、第３の
    複数のはんだバンプを付着させる段階； 第２半導体ダイを、前記上方チップ・キャリヤ基板に取
    り付けて電気的に結合する段階；前記第１半導体ダイ上にふたを置いて、前記下方チップ
    ・キャリア基板と前記上方チップ・キャリア基板との間
    の分離体として機能させる段階； 前記第１の複数のはんだバンプおよび前記第３の複数の
    はんだバンプの位置により、前記上方チップ・キャリヤ
    基板を前記下方チップ・キャリヤ基板に整合させる段
    階；ならびに前記第１の複数のはんだバンプおよび前記
    第３の複数のはんだバンプをリフローして、物理的接続
    および電気的接続を達成する段階； によって構成されることを特徴とする積層可能な半導体
    マルチチップ・モジュールを製造する方法。
JP06252693A 1992-03-02 1993-03-01 積層可能な三次元マルチチップ半導体デバイスとその製法 Expired - Lifetime JP3239909B2 (ja)

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US07/844,075 US5222014A (en) 1992-03-02 1992-03-02 Three-dimensional multi-chip pad array carrier

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US5222014A (en) 1993-06-22
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