CN1998077B - 半导体装置的制造方法及半导体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 157
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 46
- 239000011347 resin Substances 0.000 claims abstract description 46
- 238000007789 sealing Methods 0.000 claims abstract description 14
- 239000003566 sealing material Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 118
- 239000008393 encapsulating agent Substances 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 32
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 238000004026 adhesive bonding Methods 0.000 claims description 4
- 238000005304 joining Methods 0.000 claims description 4
- 238000011109 contamination Methods 0.000 abstract 2
- 229920006015 heat resistant resin Polymers 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 16
- 238000005538 encapsulation Methods 0.000 description 11
- 238000000465 moulding Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 7
- 239000000523 sample Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 235000014347 soups Nutrition 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- -1 Polyethylene Terephthalate Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229920001131 Pulp (paper) Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- KUCOHFSKRZZVRO-UHFFFAOYSA-N terephthalaldehyde Chemical compound O=CC1=CC=C(C=O)C=C1 KUCOHFSKRZZVRO-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明半导体装置的制造方法,具有:配置耐热薄板(31)以覆盖形成于中继基板(11)上的电极焊垫(端子)(17)的步骤;及利用金属模具(41、42)夹住中继基板与耐热薄板(31),且进行树脂密封的步骤。在利用耐热薄板覆盖电极焊垫(端子)(17)以保护电极焊垫(端子)(17)之后,通过以树脂密封半导体元件(14),就不会发生污物附着在电极焊垫(端子)(17)上的不良情形。因此,可防止中继基板(11)上所发生的树脂毛边或电极焊垫的污染,且可提高制造良率。
Description
技术领域
本发明关于一种具有以树脂只密封基板单面的构成的半导体装置的制造方法及利用该制造方法而制造的半导体装置。更详言之关于一种使用于层叠成数层封装的层叠型半导体装置的半导体装置的制造方法。
背景技术
近年来,如行动电话的可携式电子机器或如IC内存卡的非挥发性记忆媒体等更为小型化,而更要求该等机器或媒体的零件数的削减及零件的小型化。
因而,期望可开发出一种有效率封装用以构成该等机器的零件中作为主要零件的半导体组件的技术。作为满足该种要求的封装之一,为人周知者有将复数个封装,例如内存用的封装与逻辑用的封装予以层叠并形成一个的层叠型封装。有关于层叠型封装的制造方法在专利文献1~3中有揭示。
第1图显示层叠型半导体装置的构成的一例。第1图所示的层叠型封装,在第1半导体装置110的上方层叠第2半导体装置120而构成。第1半导体装置110,在中继基板111上搭载有未图标的半导体元件,且以密封材料112密封该半导体元件。又在中继基板111的背面一侧,设有安装与其它基板电连接用的球形113。同样地第2半导体装置120亦以铸模具树脂122密封搭载于中继基板121上的半导体元件,且在中继基板121的背面一侧设置球形123。
第2(A)图显示第1半导体装置110的习知第1构成的上视图与截面图;(B)显示第1半导体装置110的习知第2构成的上视图与截面图。如第2(A)及(B)图所示在第1半导体装置110的中继基板111上,形成有用以与第2半导体装置120的球形123电性连接用的电极焊垫114。在将第2半导体装置120层叠于第1半导体装置110上时,通过使第2半导体装置120的球形123的位置与第1半导体装置的电极焊垫114的位置一致并使之相接,第1半导体装置110与第2半导体装置120即电性连接。
在此,就以密封材料112来密封第1半导体装置110的半导体元件的方法加以说明。如第1图所示第1及第2半导体装置110、120,由保护半导体元件不受到撞击或受伤用的密封材料112、122所密封。树脂的成型一般可依转移铸模具法来进行。转移铸模具法,在将密封材料112成型于以玻璃环氧基板为代表的硬质中继基板111上时,会如第3图所示地将中继基板111直接配置于金属模具130内并以上下的金属模具130来夹紧。在金属模具130上,形成有成为所要注入的树脂通路的闸门(gate)131、或注入树脂而成型的模具腔(cavity)132,且通过闸门131而供给树脂至模具腔132内,以在半导体元件的周围填充树脂。
又,在成为树脂通路的闸门重迭的中继基板111的1角隅部,如第2(A)图所示地形成有施以与密封材料密接性差的镀金的镀金部115。在树脂成型后,为了拆除闸门部分的树脂,而将该种镀金部115设在中继基板111上。
在形成于中继基板111上的电极焊垫114的数量少时,可如第2(B)图的第1半导体装置110的习知第2构成所示地取较大的密封材料112的形成区域,闸门116亦可设在中继基板111的外侧。但是在如第2(A)图的第1半导体装置110的习知第1构成所示为了增加电极焊垫114的数量而取较小的密封材料112的形成区域,且如第2(A)图所示形成电极焊垫114以包围住密封材料112时,闸门就会被重迭在中继基板111上。因此在闸门被重迭的中继基板111的角隅部上并非是设置电极焊垫114而是设置镀金部115。
专利文献1:日本专利特开平8-236694号公报
专利文献2:日本专利特开2003-218273号公报
专利文献3:日本专利特开平6-13541号公报
发明内容
发明所欲解决的问题
在上面所述的习知转移铸模具法中,由于将中继基板111直接配置在金属模具130内并依密封材料进行密封,所以会发生在中继基板111上贴附油脂或树脂毛边等的粉末灰尘,以致污染电极焊垫114的问题。因此会对接合半导体装置彼此时的接合性带来不良影响,成为制造良率降低的原因。
更且当如第2(A)图所示设置镀金部115时,无法在中继基板111上的该区域设置电极焊垫114。因此,有需要相对增大中继基板的尺寸,而成为阻碍半导体装置的小型化的要因。
又为了解决该种问题虽亦提出一种从半导体元件的上方注入密封材料的顶闸方式的铸模具方法,但是仍会发生很难去除树脂成型后所残留的闸门部与流路部的树脂、树脂的注入口由于小所以每次使用金属模具时需要清洁、及金属模具由于复杂所以变成高价的问题。
本发明有鉴于所述情事而研创者,其目的在于提供一种可防止中继基板上所发生的树脂毛边或电极焊垫的污染,且可提高制造良率的半导体装置的制造方法及半导体装置。
解决问题的手段
为了达成该种目的,本发明的半导体装置的制造方法,具有:配置耐热薄板以覆盖形成于中继基板上的电极端子的步骤;将金属模具与中继基板夹紧以形成闸门部,并使该金属模具的侧面表面与该耐热薄板齐平;以及在水平方向注入密封材料至该闸门部,用于密封材料密封搭载于所述中继基板上的半导体元件的步骤。
在以耐热薄板覆盖电极端子以保护电极端子之后,通过以密封材料密封半导体元件,以使污物不会附着在电极端子。在将密封材料设为树脂的情况可防止中继基板上所发生的树脂毛边或电极焊垫的污染,且可提高制造良率。又,通过在中继基板与所要密封的密封材料之间夹入耐热薄板,即可在成型后从中继基板轻易地剥离密封材料。因而,没有必要设置用以剥离密封材料的镀金,且亦可在相当于中继基板的闸门的区域配置电极端子,而可使半导体装置小型化。
又,所述半导体装置的制造方法中,所述耐热薄板亦可黏接于所述中继基板。
通过将耐热薄板黏接在中继基板,即可防止耐热薄板的位置偏移或剥离。
又所述半导体装置的制造方法中,所述耐热薄板层叠成数层,且与所述中继基板的相接一侧具有柔软性为佳。
由于耐热薄板层叠成数层,且与中继基板的相接一侧具有柔软性,所以不会发生因金属模具夹紧时所产生的压力损坏中继基板的不良情形。又在因金属配线等而在中继基板的表面发生凹凸不平时,通过与具有柔软性的耐热薄板相接而不会使密封材料进入凹凸内。
又所述半导体装置的制造方法中,所述耐热薄板亦可具有将所述耐热薄板配置在所述中继基板上用的开口,以保证不与所述密封材料所密封的半导体元件重叠。
由于耐热薄板在密封材料成型后从中继基板去除,所以通过将耐热薄板配置成不与密封材料部重迭,即可轻易地去除耐热薄板。
又所述半导体装置的制造方法中,亦可具有在配置有所述耐热薄板的所述中继基板的背面一侧安装球形端子的步骤。
通过在附有耐热薄板的状态下直接安装中继基板的背面一侧的球形端子,即可在安装球形端子时通过涂敷助焊剂或使用药液的助焊剂清洗而不使中继基板的电极端子受到污染。
又所述半导体装置的制造方法中,所述中继基板与所述耐热薄板,亦可具有与设在所述金属模具上的导销相嵌合的导孔,且所述中继基板与所述耐热薄板可通过将所述导销插入于所述导孔内而定位于所述金属模具。
配设于金属模具的导销,虽被用于中继基板的定位,但是亦可通过将的用于耐热薄板的定位,而无损中继基板与耐热薄板的位置关而可确实地在金属模具内配置中继基板与耐热薄板。
又所述半导体装置的制造方法中,所述金属模具的构造亦可所述通路与所述模具腔边界入口的截面积,小于所述密封材料注入模具腔内的通路的截面积。
可将配置有耐热薄板的闸门部的内部压力比起模具腔入口附近的内部压力还提高,且可利用内部压力来压住耐热薄板。因而,可防止作为密封材料的树脂进入耐热薄板与中继基板之间。
所述半导体装置的制造方法中,亦可具有从所述中继基板上拆除所述耐热薄板的步骤。
又所述半导体装置的制造方法中,所述电极端子,亦可形成在所述中继基板上的所述半导体元件的配置区域以外的全部区域。
依据该半导体装置的制造方法,则亦可在相当于中继基板上的闸门的区域配置电极端子。因而可将半导体装置小型化。
又所述半导体装置的制造方法中,亦可具有在所述密封材料所密封的所述半导体元件上层叠其它半导体装置的步骤。
通过形成层叠型半导体装置,即可完成半导体元件的有效率的封装。
又所述半导体装置的制造方法中,所述密封材料亦可由树脂组成。通过以树脂来封装半导体元件,即可保护半导体元件不受到撞击或受伤。
本发明的半导体装置,具有:被密封材料所密封的半导体元件;中继基板,其搭载有被所述密封材料所密封的所述半导体元件;及所述密封材料,其使用用以覆盖所述中继基板上的电极端子的耐热薄板,并通过对所述半导体元件进行的密封而使外形成型。
在以耐热薄板覆盖电极端子以保护电极端子之后,通过以密封材料密封半导体元件,以使污物不会附着在电极端子。因而,在将密封材料设为树脂时可防止中继基板上所发生的树脂毛边或电极焊垫的污染,且可提高制造良率。
发明效果
本发明,可防止中继基板上所发生的树脂毛边或电极焊垫的污染,且可提高制造良率。
附图说明
第1图显示习知层叠型半导体装置的构成的截面图。
第2(A)图显示第1半导体装置的习知第1构成的上视图与截面图;(B)显示第1半导体装置的习知第2构成的上视图与截面图。
第3图显示以金属模具夹紧习知第1半导体装置的状态的示意图。
第4图显示本发明的层叠型半导体装置的构成的截面图。
第5图显示第1半导体装置的构成的上视图与截面图。
第6图显示第1半导体装置的制造顺序的流程图。
第7(A)图显示在中继基板11上搭载半导体元件14的状态的示意图;(B)显示将中继基板11载置于下侧金属模具42上的状态的示意图;(C)显示在中继基板11上配置耐热薄板31的状态的示意图;(D)显示以金属模具41、42夹紧搭载有半导体元件14的中继基板11的状态的示意图;(E)显示介以闸口50将树脂密封在模具腔内的状态的示意图;(F)显示在树脂成型后,拆除上侧金属模具41的状态的示意图;(G)将下侧金属模具42从中继基板11拆除的状态的示意图;(H)显示闸门裂断(gate break)处理后的第1半导体装置的构成的示意图;(I)显示去除耐热薄板31后的第1半导体装置的构成的示意图。
第8图显示配置于中继基板上的耐热薄板的示意图。
第9图显示金属模具的构成的截面图。
第10图显示第1半导体装置的其它制造顺序的流程图。
第11(A)图显示将耐热薄板31残留于中继基板11上的状态的示意图;(B)显示依探针60进行测试的状态的示意图;(C)显示测试结束后去除耐热薄板31的状态的示意图。
第12图显示第2实施例的半导体装置的制造顺序的示意图,且显示在第1耐热薄板上配置第2耐热薄板的状态的示意图。
具体实施方式
其次,一面参照附图而一面就实施本发明用的最佳形态加以说明。另外,以下虽以层叠型半导体装置的制造方法为例加以说明,但是依本发明所制造的半导体装置,并非限定于层叠型半导体装置。例如,亦可适用作为依半导体元件的树脂密封而防止信号图案的污染的技术。
实施例1
首先,一面参照第4图一面说明依本发明而制造的层叠型半导体装置的一例。第4图所示的层叠型半导体装置1,采用在第1半导体装置10上层叠第2半导体装置20的二层构成。
第1半导体装置10如第4图所示在中继基板11的表面侧搭载半导体元件14,且以密封材料12来密封该半导体元件14。通过以密封材料12来密封该半导体元件14,即可防止半导体元件14上所发生的撞击或受伤。密封材料12可使用环氧、聚硅氧、聚酰亚胺等的树脂。又在中继基板11的背面一侧设有球形13,其被使用于与试验用探针的试验接脚、或其它基板间的连接。
第2半导体装置20亦如第4图所示在中继基板11的表面侧搭载未图标的半导体元件,且以密封材料来密封中继基板21的基板全面。在中继基板11的背面一侧设有球形23,其可取得第1半导体装置10与第2半导体装置20间的电性连接。又如第4图所示,第1半导体装置10与第2半导体装置20可以接着剂2而黏接固定。
在此,一面参照第5图一面说明第1半导体装置10的构成。第5图显示从上方观看第1半导体装置10的上视图与从侧方观看的侧视图。在第1半导体装置10的中继基板11上,如第5图的上视图所示形成有电极焊垫(端子)17。本实施例中,电极焊垫(端子)17形成于除了半导体元件的形成区域以外的中继基板11上的区域。亦即,由于没有必要形成如第2(A)图所示的镀金部115,所以可在除了半导体元件的形成区域以外的中继基板11上形成电极焊垫(端子)17。通过使电极焊垫(端子)17、与设于第2半导体装置20的背面一侧的球形23接触,第2半导体装置20与第1半导体基板10即电性连接。
其次,一面参照第5图的侧视图一面就密封半导体元件的密封材料12加以说明。密封材料12包含如第5图所示形成于中继基板11上的第1密封材料3(12)、及形成于该第1密封材料3(12)上的四角锥梯形的第2密封材料4(12)。亦即,第1密封材料3(12)包围住第2密封材料4(12)的外周,且第1密封材料3(12)成为第2密封材料4(12)的凸缘部。密封材料12成为该种形状,为了在密封半导体元件的密封材料12的形成步骤中,配置耐热薄板31以覆盖形成于中继基板11上的电极焊垫(端子)17,而形成密封材料所致。换句话说,在密封材料12形成凸缘部,为了将耐热薄板31从密封材料12的配置区域离开指定距离而配置所致(参照第7(C)、(D)图),而流入至形成区域与耐热薄板31之间作为密封材料的树脂会直接残留在中继基板11上而成为凸缘部。
在此,一面参照第6图所示的流程图一面就以密封材料12来密封第1半导体装置10的半导体元件14的顺序加以说明。另外,在此虽以第1半导体装置10为例加以说明,但是就第2半导体装置20而言亦可以同样的顺序来成型密封材料22。又,以下顺序中,使用树脂作为密封材料12,且说明依树脂而密封半导体元件的顺序。
首先,将第1半导体装置10搭载在下侧金属模具42上(步骤S1)。第1半导体装置10如第7(A)图所示在中继基板11上搭载半导体元件14,而半导体元件14与中继基板11可依金属线15而电性连接。又在下侧金属模具42如第7(B)图所示设有导销43,而在第1半导体装置10的中继基板11设有与该导销43相嵌合的导孔16。通过使第1半导体装置10的导孔16嵌合在下侧金属模具42的导销43内,即可如第7(B)图所示地使第1半导体装置10定位于下侧金属模具42。
其次,将依树脂密封而防止电极焊垫(端子)17的污染的耐热薄板31设置在第1半导体装置10的中继基板11上(步骤S2)。在耐热薄板31亦形成有导孔32,通过将下侧金属模具42的导销43插入于该导孔32内,即可使耐热薄板31定位于中继基板11上。第7(C)图显示在中继基板11上配置耐热薄板31的状态;第8图显示配置有耐热薄板31的第1半导体装置10的上视图。耐热薄板31如第8图所示中央部分被凿开而成为开口,且在用以成型密封材料12的模具腔周围,以覆盖电极焊垫(端子)17上的方式而配置。另外,在耐热薄板31亦可事先涂敷接着剂,俾于配置于中继基板11上时不会从中继基板11剥落。
耐热薄板31可使用PET(Polyethylene Terephthalate,聚对苯二甲二乙酯)树脂、氟系树脂、金属性薄板、纸浆系树脂等。又在密封材料12成型时,上下金属模具41、42保持于170℃前后。因此耐热薄板31以选择即使在约175℃的温度下亦几乎不发生变形或尺寸变化者为佳。通过即使在高温下亦不发生尺寸变化即可防止在耐热薄板31与中继基板11之间流入作为密封材料12的树脂。另外,第7图虽只图示搭载于中继基板11上的一个半导体元件14,但是半导体元件的封装,由于可将复数个半导体元件搭载于中继基板11上,且在树脂密封或指定的处理后切断中继基板11以分切成各半导体装置,所以耐热薄板31亦可不依每一半导体元件独立。
其次,如第7(D)图所示夹紧上侧金属模具41与下侧金属模具42(步骤S3),且如第7(E)图所示将密封材料12的树脂密封在模具腔内(步骤S4)。在安装上侧金属模具41时,由于如第7(D)图所示在上侧金属模具41上亦设有导孔44,所以可通过使导孔44嵌合在设于下侧金属模具42上的导销43以使上侧金属模具41配置在第1半导体装置10上的指定位置。
对模具腔内注入密封材料12的树脂,从成为树脂通路的闸门部50开始进行。此时,由于在闸门部50的下方如第7(D)图所示配置有耐热薄板31,所以即使从闸门部50注入树脂亦不会让树脂附着在电极焊垫(端子)17。因此通过在耐热薄板31上产生容易在中继基板11上的密封材料端面发生的树脂毛边,并去除耐热薄板31即可将中继基板11的表面保持干净。又,没有必要在中继基板11上的闸门部50重迭的区域设置镀金部,而可在中继基板11的全部角隅不浪费地配置电极。
又金属模具41、42形成模具腔入口51的截面积比闸门部50的树脂通路的截面积小。亦即,第9图所示的闸门部50的通路的截面积a,形成比模具腔入口51的截面积b大。通过采用该种构成即可将配置有耐热薄板31的闸门部50的内部压力比模具腔入口51附近的内部压力更加提高,且可利用内部压力来压住耐热薄板31。因而,可防止密封材料12进入耐热薄板31与中继基板11之间。
当密封材料12的树脂结束密封时(步骤S4),如第7(F)图所示将上侧金属模具41从第1半导体装置10上拆除(步骤S5),且将第1半导体装置10从下侧金属模具42取出(步骤S6)。
当从下侧金属模具42拆除第1半导体装置10时(步骤S6),进行将密封材料12与闸门部50的树脂予以分离的闸门裂断(gatebreak)处理(步骤S7)。当利用闸门裂断处理以拆除闸门部50的树脂时,将耐热薄板31从中继基板11上去除以结束一系列的处理(步骤S8)。
如此在本制造顺序中,当利用密封材料来密封半导体元件14时,事先配置耐热薄板31,且通过在耐热薄板31上重迭用以注入密封材料12的树脂的闸门部50,即不会在电极焊垫(端子)17上发生污染。因而,可将设在闸门部50的下方的电极焊垫(端子)17使用于与层叠于上方的半导体装置间的电性连接。因此,没有必要增大中继基板的大小,而可提高制造良率。
另外,上面所述的制造顺序中,虽然在闸门裂断处理后才去除耐热薄板31,但是亦可事先将耐热薄板31直接配置于中继基板11上,而使用于后段步骤中。兹就该顺序一面参照第10图所示的流程图一面加以说明。
本顺序中,当以闸门裂断处理来拆除闸门部50的树脂时(步骤S16),以使耐热薄板31搭载于中继基板11上的状态直接安装球形13(步骤S17)。第11(A)图显示在中继基板11的背面一侧安装球形13的状态。当安装球形13时,在该球形13连接第11(B)图所示的探针60以进行测试(步骤S18)。从探针60供给电源或测试信号以测试第1半导体装置10是否正常动作。当测试结束时,如第11(C)图所示将耐热薄板31从中继基板11上剥离,而完成第1半导体装置10(步骤S19)。
如此在本制造顺序中,事先将密封材料成型时所使用的耐热薄板31直接贴附在中继基板11上,以实施球形13的搭载与测试。在球形13的安装方面,由于进行助焊剂涂敷或使用药液的助焊剂清洗,所以中继基板11的电极焊垫(端子)17容易受到污染。因此,通过事先利用耐热薄板31来覆盖电极焊垫(端子)17即可将中继基板11的表面保持于干净的状态,且可谋求制造良率的提高。
实施例2
其次,一面参照附图一面就本发明的第2实施例加以说明。本实施例,如第12图所示在中继基板11上配置二种耐热薄板,且将的以金属模具41、42夹入以进行密封材料12的树脂密封。配置于中继基板11上的第1耐热薄板71,纸张或化学薄板等所构成的具有柔软性的薄板,而配置于第1耐热薄板71上的第2耐热薄板72,金属等所构成的具有刚性的薄板。亦即,在中继基板11与第2耐热薄板72之间夹入具有柔软性的第1耐热薄板71。
通过使与玻璃环氧基板等的硬质中继基板11相对向的第1耐热薄板71具有柔软性(缓冲性),即可防止因金属模具夹紧时的压力而使中继基板11破损的不良情形。又在中继基板11的表面,虽然因铜等的金属配线而会发生凹凸不平,但是通过第1耐热薄板71具备柔软性,即可防止第1耐热薄板71对应中继基板11的凹凸而变形,而使密封材料进入凹凸的不良情形。
另外,该第1耐热薄板71与第2耐热薄板72,亦与上面所述的第1实施例的耐热薄板31同样以选择即使在约175℃的温度下几乎不发生变形或尺寸变化者为佳。更且第12图,虽已例示耐热薄板由第1耐热薄板71与第2耐热薄板72的二片所构成的情况,但是一片耐热薄板亦可分为二层,使下侧的层具有柔软性,上侧的层具有刚性。
上面所述的实施例本发明的较佳实施例。但并非限定于此,只要在未脱离本发明的要旨的范围内均可做各种变化实施。
Claims (11)
1.一种半导体装置的制造方法,具有:
配置耐热薄板以覆盖形成于中继基板上的电极端子的步骤;
将金属模具与中继基板夹紧以形成闸门部,并使该金属模具的侧面表面与该耐热薄板齐平;以及
在水平方向注入密封材料至该闸门部,用于密封材料密封搭载于所述中继基板上的半导体元件的步骤。
2.如权利要求1所述的半导体装置的制造方法,其中,所述耐热薄板黏接于所述中继基板。
3.如权利要求1或2所述的半导体装置的制造方法,其中,所述耐热薄板层叠成数层,且与所述中继基板相接一侧具有柔软性。
4.如权利要求1所述的半导体装置的制造方法,其中,所述耐热薄板具有将所述耐热薄板配置在所述中继基板上用的开口,以保证不与所述密封材料所密封的半导体元件重叠。
5.如权利要求1所述的半导体装置的制造方法,其中,还具有在配置有所述耐热薄板的所述中继基板的背面一侧安装球形端子的步骤。
6.如权利要求1所述的半导体装置的制造方法,其中,所述中继基板与所述耐热薄板具有与设在所述金属模具的导销相嵌合的导孔,且所述中继基板与所述耐热薄板可通过将所述导销插入于所述导孔内而定位于所述金属模具。
7.如权利要求1所述的半导体装置的制造方法,其中,所述金属模具的其中之一在所述密封材料注入模具腔内的通路中具有第一截面积,以及在所述通路与容置所述半导体元件的所述模具腔之间的接口处具有第二截面积,所述第二截面积小于所述第一截面积。
8.如权利要求1或5所述的半导体装置的制造方法,其中,还具有从所述中继基板上拆除所述耐热薄板的步骤。
9.如权利要求1所述的半导体装置的制造方法,其中,所述电极端子形成在所述中继基板上的所述半导体元件的配置区域以外的全部区域。
10.如权利要求1所述的半导体装置的制造方法,其中,还具有在所述密封材料所密封的所述半导体元件上层叠其它半导体装置的步骤。
11.如权利要求1所述的半导体装置的制造方法,其中,所述密封材料由树脂组成。
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WO2005114730A1 (ja) | 2005-12-01 |
US9368424B2 (en) | 2016-06-14 |
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