JP4243177B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4243177B2 JP4243177B2 JP2003424923A JP2003424923A JP4243177B2 JP 4243177 B2 JP4243177 B2 JP 4243177B2 JP 2003424923 A JP2003424923 A JP 2003424923A JP 2003424923 A JP2003424923 A JP 2003424923A JP 4243177 B2 JP4243177 B2 JP 4243177B2
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Description
本実施の形態1の半導体装置の製造方法の一例を図1の工程フローに沿って図2〜図24により説明する。
本実施の形態2では、例えば基板母体11上にフリップチップ実装されている複数のチップ1Cを、可動エアベント構成を有する成型金型を用いてモールドする技術について説明する。
1C 半導体チップ
1S 半導体基板
2a,2b 絶縁膜
3a,3b 表面保護膜
4a,4b 開口部
5 再配線
6 封止樹脂膜
7 バンプ下地金属パターン
8 バンプ電極(突起電極)
9 ダイシングブレード
11 配線基板母体(基板、多層配線基板)
11a 配線基板
12 絶縁層
13 配線層
13a〜13f 導体パターン
14 ソルダレジスト
15a,15b バンプ下地金属パターン
17 モールド装置
17a 下型
17a1 ポットホルダ
17a2 ポット
17a3 プランジャ
17a4 下型キャビティ台
17a5 ガイドピン
17b 上型
17b1 上型キャビティ
17b2 カルブロック
17b3 溝
17b4 開口部
17b5 イジェクタピン
17b6 上型キャビティブロック
17b7 ゲート
17b8 エアベント
17b9 真空吸引孔
17c ラミネートフィルム
17d 真空チャンバ
17d1 排気管
18 一括封止体
18a 封止体
20 バンプ保持ツール
21 半田バンプ
21a バンプ電極(突起電極)
22 ダイシングブレード
23 半導体装置
25 自動モールド装置
26 タブレット整列部
27 タブレットパーツフィーダ
28 基板ローダ
29 基板整列部
30a 搬入搬送部
30b 搬出搬送部
31 ゲートブレイク部
32 基板アンローダ
35 可動ピン
35a 溝
36 弾性体
37a 可動ピン前部
37b 可動ピン部
37c 可動ピン後部
BP ボンディングパッド
DR 製品領域
UDR 単位製品領域
CR チップ搭載領域
MR モールド領域
CB キャビティ
p1 初期圧力(第1のクランプ圧力)
p2 最終圧力(第2のクランプ圧力)
Claims (15)
- (a)基板を用意する工程と、
(b)前記基板の主面上に突起電極を介して半導体チップを搭載する工程と、
(c)前記半導体チップが搭載された基板を樹脂成型用の成型金型の下型の成型面に載置する工程と、
(d)前記成型金型のキャビティを減圧状態とする工程と、
(e)前記基板を前記成型金型の下型と上型とで挟み込むようにクランプした後、前記成型金型のキャビティ内および前記基板と前記半導体チップとの対向面間に封止用樹脂を充填し、前記半導体チップを封止する工程とを有し、
前記(e)工程は、
(e1)前記基板のクランプ圧力が第1のクランプ圧力となるように、前記下型および上型の相対位置関係を設定する工程と、
(e2)前記(e1)工程後、前記成型金型のキャビティの注入口から封止用樹脂を注入する工程と、
(e3)前記封止用樹脂が、前記成型金型の前記注入口とエアベントとの間の途中の位置に達するところで、前記基板のクランプ圧力が、前記第1のクランプ圧力よりも高い第2のクランプ圧力となるように、前記下型および上型の相対位置関係を設定する工程とを有し、
前記成型金型は、
前記キャビティに通じるエアベントと、
前記エアベントに突出する可動ピンとを備え、
前記可動ピンは、弾性体により前記成型面に交差する方向に動作可能な状態で設けられ、前記可動ピンの前記基板の対向面には溝が設けられており、
前記(e)工程においては、前記基板を下型と上型とで挟み込むようにクランプすると、前記可動ピンが前記基板から押圧される一方、前記可動ピンは前記弾性体の反発力により前記基板を押圧するようになり、前記キャビティ内の気体が、前記エアベントおよび前記溝を通じて前記キャビティの外部に排出されることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記基板が多層配線基板であることを特徴とする半導体装置の製造方法。
- 請求項2記載の半導体装置の製造方法において、前記多層配線基板は、樹脂膜と金属箔との積層構成を有することを特徴とする半導体装置の製造方法。
- (a)複数の単位製品領域が配置された製品領域を有する基板を用意する工程と、
(b)前記複数の単位製品領域の各々に突起電極を介して半導体チップを搭載する工程と、
(c)前記半導体チップが複数個搭載された基板を樹脂成型用の成型金型の下型の成型面に載置する工程と、
(d)前記成型金型のキャビティを減圧状態とする工程と、
(e)前記基板を前記成型金型の下型と上型とで挟み込むようにクランプした後、前記成型金型のキャビティ内および前記基板と前記半導体チップとの対向面間に封止用樹脂を充填し、前記製品領域の複数の半導体チップを一括して封止する一括封止体を形成する工程とを有し、
前記(e)工程は、
(e1)前記基板のクランプ圧力が第1のクランプ圧力となるように、前記下型および上型の相対位置関係を設定する工程と、
(e2)前記(e1)工程後、前記成型金型のキャビティの注入口から封止用樹脂を注入する工程と、
(e3)前記封止用樹脂が、前記成型金型の前記注入口とエアベントとの間の途中の位置に達するところで、前記基板のクランプ圧力が、前記第1のクランプ圧力よりも高い第2のクランプ圧力となるように、前記下型および上型の相対位置関係を設定する工程とを有し、
前記成型金型は、
前記キャビティに通じるエアベントと、
前記エアベントに突出する可動ピンとを備え、
前記可動ピンは、弾性体により前記成型面に交差する方向に動作可能な状態で設けられ、前記可動ピンの前記基板の対向面には溝が設けられており、
前記(e)工程においては、前記基板を下型と上型とで挟み込むようにクランプすると、前記可動ピンが前記基板から押圧される一方、前記可動ピンは前記弾性体の反発力により前記基板を押圧するようになり、前記キャビティ内の気体が、前記エアベントおよび前記溝を通じて前記キャビティの外部に排出されることを特徴とする半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、前記基板が多層配線基板であることを特徴とする半導体装置の製造方法。
- 請求項5記載の半導体装置の製造方法において、前記多層配線基板は、樹脂膜と金属箔との積層構成を有することを特徴とする半導体装置の製造方法。
- 請求項4記載の半導体装置の製造方法において、
前記(e)工程後、
(f)前記基板の裏面に突起電極を形成する工程と、
(g)前記(f)工程後、前記一括封止体および基板を前記複数の単位製品領域毎に切断する工程とを有することを特徴とする半導体装置の製造方法。 - (a)基板を用意する工程と、
(b)前記基板の主面上に突起電極を介して半導体チップを搭載する工程と、
(c)前記半導体チップが搭載された基板を樹脂成型用の成型金型の下型の成型面に載置する工程と、
(d)前記成型金型のキャビティを減圧状態とする工程と、
(e)前記基板を前記成型金型の下型と上型とで挟み込むようにクランプした後、前記成型金型のキャビティ内および前記基板と前記半導体チップとの対向面間に封止用樹脂を充填し、前記半導体チップを封止する工程とを有し、
前記成型金型は、
前記キャビティに通じるエアベントと、
前記エアベントに突出する可動ピンとを備え、
前記可動ピンは、弾性体により前記成型面に交差する方向に動作可能な状態で設けられ、前記可動ピンの前記基板の対向面には溝が設けられており、
前記(e)工程においては、前記基板を下型と上型とで挟み込むようにクランプすると、前記可動ピンが前記基板から押圧される一方、前記可動ピンは前記弾性体の反発力により前記基板を押圧するようになり、前記キャビティ内の気体を、前記エアベントおよび前記溝を通じて前記キャビティの外部に排出されることを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、前記基板が多層配線基板であることを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記多層配線基板は、樹脂膜と金属箔との積層構成を有することを特徴とする半導体装置の製造方法。
- (a)複数の単位製品領域が配置された製品領域を有する基板を用意する工程と、
(b)前記複数の単位製品領域の各々に突起電極を介して半導体チップを搭載する工程と、
(c)前記半導体チップが複数個搭載された基板を樹脂成型用の成型金型の下型の成型面に載置する工程と、
(d)前記成型金型のキャビティを減圧状態とする工程と、
(e)前記基板を前記成型金型の下型と上型とで挟み込むようにクランプした後、前記成型金型のキャビティ内および前記基板と前記半導体チップとの対向面間に封止用樹脂を充填し、前記製品領域の複数の半導体チップを一括して封止する一括封止体を形成する工程とを有し、
前記成型金型は、
前記キャビティに通じるエアベントと、
前記エアベントに突出する可動ピンとを備え、
前記可動ピンは、弾性体により前記成型面に交差する方向に動作可能な状態で設けられ、前記可動ピンの前記基板の対向面には溝が設けられており、
前記(e)工程においては、前記基板を下型と上型とで挟み込むようにクランプすると、前記可動ピンが前記基板から押圧される一方、前記可動ピンは前記弾性体の反発力により前記基板を押圧するようになり、前記キャビティ内の気体が、前記エアベントおよび前記溝を通じて前記キャビティの外部に排出されることを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、前記基板が多層配線基板であることを特徴とする半導体装置の製造方法。
- 請求項12記載の半導体装置の製造方法において、前記多層配線基板は、樹脂膜と金属箔との積層構成を有することを特徴とする半導体装置の製造方法。
- 請求項11記載の半導体装置の製造方法において、
前記(e)工程後、
(f)前記基板の裏面に突起電極を形成する工程と、
(g)前記(f)工程後、前記一括封止体および基板を前記複数の単位製品領域毎に切断する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項1、4、8、又は11記載の半導体装置の製造方法において、
前記半導体チップの裏面を覆う前記封止用樹脂の厚さは、前記半導体チップと前記配線基板との対向面間の前記封止用樹脂の厚さよりも厚く、かつ、前記配線基板の厚さよりは薄くされており、
前記封止用樹脂の線膨張率は、前記配線基板の線膨張率よりも大きいことを特徴とする半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243435A (ja) * | 2002-02-14 | 2003-08-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
CN1998077B (zh) * | 2004-05-20 | 2010-06-16 | 斯班逊有限公司 | 半导体装置的制造方法及半导体装置 |
JP2006073586A (ja) * | 2004-08-31 | 2006-03-16 | Renesas Technology Corp | 半導体装置の製造方法 |
US7482193B2 (en) * | 2004-12-20 | 2009-01-27 | Honeywell International Inc. | Injection-molded package for MEMS inertial sensor |
DE102005020427A1 (de) * | 2005-04-29 | 2006-11-09 | Infineon Technologies Ag | Verfahren und Gießformwerkzeug zur Herstellung einer Schutzschicht an integrierten Bauelementen |
JP4587881B2 (ja) * | 2005-06-10 | 2010-11-24 | サンユレック株式会社 | 樹脂封止装置 |
US20090301760A1 (en) * | 2005-06-16 | 2009-12-10 | Masato Shimamura | Method of Soldering a Module Board |
US7491567B2 (en) * | 2005-11-22 | 2009-02-17 | Honeywell International Inc. | MEMS device packaging methods |
US20070114643A1 (en) * | 2005-11-22 | 2007-05-24 | Honeywell International Inc. | Mems flip-chip packaging |
JP4954591B2 (ja) * | 2006-04-13 | 2012-06-20 | シャープ株式会社 | 発光装置およびその製造方法 |
US20070243667A1 (en) * | 2006-04-18 | 2007-10-18 | Texas Instruments Incorporated | POP Semiconductor Device Manufacturing Method |
JP2008047573A (ja) * | 2006-08-11 | 2008-02-28 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置の製造装置、樹脂封止型半導体装置の製造方法、および樹脂封止型半導体装置 |
WO2008026717A1 (en) * | 2006-08-29 | 2008-03-06 | Panasonic Corporation | Electroluminescent phos phor- converted light source and method for manufacturing the same |
JP5054954B2 (ja) | 2006-09-22 | 2012-10-24 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7927923B2 (en) | 2006-09-25 | 2011-04-19 | Micron Technology, Inc. | Method and apparatus for directing molding compound flow and resulting semiconductor device packages |
JP5140517B2 (ja) * | 2008-08-07 | 2013-02-06 | アピックヤマダ株式会社 | 樹脂モールド装置および樹脂モールド方法 |
JP5147758B2 (ja) * | 2008-09-30 | 2013-02-20 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法、半導体装置およびモールド金型 |
TWI416636B (zh) * | 2009-10-22 | 2013-11-21 | Unimicron Technology Corp | 封裝結構之製法 |
KR101708272B1 (ko) | 2009-10-28 | 2017-02-21 | 삼성전자주식회사 | 반도체 패키지의 제조 장치 및 반도체 패키지의 제조 방법 |
JP5490605B2 (ja) * | 2010-04-28 | 2014-05-14 | 住友重機械工業株式会社 | 樹脂封止装置及び樹脂封止方法 |
US8766426B2 (en) * | 2010-09-24 | 2014-07-01 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control and method of manufacture thereof |
KR101425479B1 (ko) * | 2011-12-07 | 2014-08-04 | 콘티넨탈 오토모티브 시스템 주식회사 | 카드형 무선 송수신기 제조 방법 |
KR20130071792A (ko) * | 2011-12-21 | 2013-07-01 | 삼성전자주식회사 | Muf용 pcb 및 그 pcb 몰딩 구조 |
CN102543909B (zh) * | 2012-03-01 | 2016-08-17 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
US8796049B2 (en) * | 2012-07-30 | 2014-08-05 | International Business Machines Corporation | Underfill adhesion measurements at a microscopic scale |
KR101398016B1 (ko) | 2012-08-08 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | 리드 프레임 패키지 및 그 제조 방법 |
US9386701B2 (en) * | 2012-11-30 | 2016-07-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component embedded printed circuit board |
JP6387256B2 (ja) * | 2014-07-07 | 2018-09-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6020667B1 (ja) * | 2015-06-19 | 2016-11-02 | 第一精工株式会社 | トランスファー成形機および電子部品を製造する方法 |
CN105193543B (zh) * | 2015-08-25 | 2017-04-26 | 国网吉林省电力有限公司电力科学研究院 | 抽拉格网式个体降噪耳罩的制备工艺 |
JP6576862B2 (ja) * | 2016-03-16 | 2019-09-18 | 東芝メモリ株式会社 | トランスファ成型装置 |
EP3555928B1 (en) * | 2016-12-15 | 2020-10-07 | Lumileds Holding B.V. | Led module with high near field contrast ratio |
JP6721525B2 (ja) * | 2017-03-03 | 2020-07-15 | キオクシア株式会社 | 金型 |
JP6981168B2 (ja) | 2017-10-18 | 2021-12-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
CN208068673U (zh) * | 2017-11-30 | 2018-11-09 | 南通斯迈尔精密设备有限公司 | 一种对引线框架真空吸附的半导体封装模具的型腔结构 |
CN110446383B (zh) * | 2018-05-02 | 2021-03-05 | 毅力科技有限公司 | 在至少一电子模块上形成保护膜的方法 |
US11419221B2 (en) | 2018-05-02 | 2022-08-16 | Eleadtk Co., Ltd. | Method of forming protective film on at least one electronic module |
US10840209B2 (en) | 2018-12-28 | 2020-11-17 | Micron Technology, Inc. | Methods and systems for manufacturing semiconductor devices |
US10840210B2 (en) * | 2018-12-28 | 2020-11-17 | Micron Technology, Inc. | Methods and systems for manufacturing semiconductor devices |
JP7147650B2 (ja) * | 2019-03-20 | 2022-10-05 | 株式会社デンソー | 半導体装置およびその製造方法 |
CN113276359B (zh) * | 2020-02-19 | 2022-11-08 | 长鑫存储技术有限公司 | 注塑模具及注塑方法 |
KR102214656B1 (ko) * | 2020-09-04 | 2021-02-10 | 김순희 | 반도체칩 보호막 형성용 몰드 내 충진제 주입 방법 |
TWI818248B (zh) | 2021-04-07 | 2023-10-11 | 元太科技工業股份有限公司 | 顯示裝置及其製造方法 |
US11729915B1 (en) * | 2022-03-22 | 2023-08-15 | Tactotek Oy | Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure |
CN115666000B (zh) * | 2022-12-13 | 2023-03-28 | 四川英创力电子科技股份有限公司 | 一种大尺寸印制板的自动化精密开料装置及方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5817545A (en) * | 1996-01-24 | 1998-10-06 | Cornell Research Foundation, Inc. | Pressurized underfill encapsulation of integrated circuits |
JPH11121488A (ja) | 1997-10-15 | 1999-04-30 | Toshiba Corp | 半導体装置の製造方法及び樹脂封止装置 |
JP3017485B2 (ja) * | 1998-01-23 | 2000-03-06 | アピックヤマダ株式会社 | 半導体装置の樹脂封止方法及び樹脂封止装置 |
JP3327251B2 (ja) * | 1999-05-20 | 2002-09-24 | 日本電気株式会社 | 半導体装置の樹脂封止方法 |
JP3901427B2 (ja) * | 1999-05-27 | 2007-04-04 | 松下電器産業株式会社 | 電子装置とその製造方法およびその製造装置 |
JP2001135658A (ja) | 1999-11-08 | 2001-05-18 | Towa Corp | 電子部品の組立方法及び組立装置 |
DE10127009A1 (de) * | 2001-06-05 | 2002-12-12 | Infineon Technologies Ag | Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform |
CA2350747C (en) * | 2001-06-15 | 2005-08-16 | Ibm Canada Limited-Ibm Canada Limitee | Improved transfer molding of integrated circuit packages |
JP3989329B2 (ja) * | 2002-03-26 | 2007-10-10 | 富士フイルム株式会社 | 光機能素子およびその製造方法 |
JP2004134591A (ja) * | 2002-10-10 | 2004-04-30 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
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