JP5499986B2 - 半導体装置の製造方法及び半導体製造装置 - Google Patents
半導体装置の製造方法及び半導体製造装置 Download PDFInfo
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- JP5499986B2 JP5499986B2 JP2010180028A JP2010180028A JP5499986B2 JP 5499986 B2 JP5499986 B2 JP 5499986B2 JP 2010180028 A JP2010180028 A JP 2010180028A JP 2010180028 A JP2010180028 A JP 2010180028A JP 5499986 B2 JP5499986 B2 JP 5499986B2
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- sealing
- resin
- substrate
- lower mold
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
2 封止樹脂
3 上金型ユニット
4 真空吸着機構
5 基板配置領域
6 上金型エジェクターピン
7 下金型ユニット
8 外側下金型
9 金型弁
10 内側下金型
11 流入通路
12 ポット
13 プランジャー
14 位置制御部
15 封止中基板
16 下金型エジェクターピン
17 封止樹脂
20 封止前基板
21 基板
22 半導体素子
23 接着剤
24 電極
25 ボンディング端子
26 ボンディングワイヤ
27 ランド
28 封止中基板
29 封止後基板
30,80,110,130 上金型ユニット
31,81,111,131 上金型
32,82,112 カル
33,83,113 ランナ
34,84,117,132 上金型エジェクターピン
35,85,124,133 基板配置領域
36,86,134 吸着孔
37,87,135 真空吸着機構
40,90,120,140 下金型ユニット
41,91 ランナ
42,92,114 ゲート
43,93,115,141 キャビティー
44,94,116,142 ベント
45,95,143 外側下金型
46,96,144 内側下金型
47,97,122 ポット
48,98,123 プランジャー
49,125,145 下金型エジェクターピン
50,99,146 圧力制御部
51,100 金型弁
52,101 位置制御部
60 樹脂格納部
61 ノズル
62,63,64,65 封止樹脂
70 半導体装置
71 はんだボール
72 ダイシングテープ
73 ブレード
121 下金型
Claims (5)
- 半導体素子を搭載し、前記半導体素子の電極と基板の配線パターンとをボンディングワイヤで接続し、前記基板の裏面に設けた基板電極に外部端子を接続した封止前基板を樹脂封止する半導体装置の製造方法であって、
封止装置を用いて圧縮成形封止方法により前記封止前基板を樹脂封止して封止中基板とする第1の樹脂封止工程と、
前記封止装置と同じ封止装置を用いてトランスファー封止方法により前記封止中基板を連続して樹脂封止する第2の樹脂封止工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記第1の樹脂封止工程の後に、前記封止装置を構成する内側下金型と、前記内側下金型の外周に接する枠状の金型弁を位置制御部により位置決めして、前記第2の樹脂封止工程における樹脂収容空間を構成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記金型弁の断面形状が、前記内側下金型に向かってL字状であり、前記第1の樹脂封止工程と前記第2の樹脂封止工程において、前記金属弁を上昇させて前記封止後の樹脂を前記内側下金型から取り外すことを特徴とする請求項1または請求項2に記載の半導体装置の製造方法。
- 前記第1の樹脂封止工程と前記第2の樹脂封止工程とに用いる封止樹脂が、同じ組成の樹脂であることを特徴とする請求項1乃至請求項3のいずれか1項に記載の半導体装置の製造方法。
- 真空吸着機構を備えるとともに、半導体素子を搭載し、前記半導体素子の電極と基板の配線パターンとをボンディングワイヤで接続し、前記基板の裏面に設けた基板電極に外部端子を接続した封止前基板を収容する基板配置領域を備えた上金型ユニットと
封止樹脂を押し出すポットを備えるとともに、外側下金型と内側下金型と、前記外側下金型と内側下金型との間に設けた金型弁とを備えた下金型ユニットと
を有し、
少なくとも前記内側下金型の高さ位置制御により、圧縮成形封止用の樹脂収容空間とトランスファー封止用の樹脂収容空間とを形成する位置制御機構と
前記上金型ユニットと前記下金型ユニットとの当接部に前記ポットに収容した封止樹脂を前記トランスファー封止用の樹脂収容空間に流入させる流入通路と
を備えたことを特徴とする半導体製造装置。
Priority Applications (1)
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JP2010180028A JP5499986B2 (ja) | 2010-08-11 | 2010-08-11 | 半導体装置の製造方法及び半導体製造装置 |
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JP2010180028A JP5499986B2 (ja) | 2010-08-11 | 2010-08-11 | 半導体装置の製造方法及び半導体製造装置 |
Publications (2)
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JP2012039024A JP2012039024A (ja) | 2012-02-23 |
JP5499986B2 true JP5499986B2 (ja) | 2014-05-21 |
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JP2010180028A Expired - Fee Related JP5499986B2 (ja) | 2010-08-11 | 2010-08-11 | 半導体装置の製造方法及び半導体製造装置 |
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JP (1) | JP5499986B2 (ja) |
Families Citing this family (3)
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JP6058431B2 (ja) * | 2013-03-08 | 2017-01-11 | アピックヤマダ株式会社 | 樹脂モールド装置、および樹脂モールド方法 |
JP6137679B2 (ja) * | 2013-05-13 | 2017-05-31 | アピックヤマダ株式会社 | 樹脂モールド装置および樹脂モールド方法 |
JP6499941B2 (ja) * | 2015-07-23 | 2019-04-10 | アピックヤマダ株式会社 | 樹脂成形方法および樹脂成形装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH02194634A (ja) * | 1989-01-24 | 1990-08-01 | Hitachi Chem Co Ltd | 半導体装置の製造方法 |
JPH0825860A (ja) * | 1994-07-11 | 1996-01-30 | Sharp Corp | 回路基板の一体成形方法 |
JP2003249605A (ja) * | 2002-02-22 | 2003-09-05 | Sharp Corp | 半導体装置、その製造方法、及びその金型 |
JP5415823B2 (ja) * | 2008-05-16 | 2014-02-12 | 株式会社デンソー | 電子回路装置及びその製造方法 |
JP2011243801A (ja) * | 2010-05-19 | 2011-12-01 | Elpida Memory Inc | 半導体パッケージの製造装置及び製造方法 |
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