CN104584209A - 薄型衬底PoP结构 - Google Patents

薄型衬底PoP结构 Download PDF

Info

Publication number
CN104584209A
CN104584209A CN201380043024.9A CN201380043024A CN104584209A CN 104584209 A CN104584209 A CN 104584209A CN 201380043024 A CN201380043024 A CN 201380043024A CN 104584209 A CN104584209 A CN 104584209A
Authority
CN
China
Prior art keywords
substrate
encapsulation agent
terminal
couple
nude film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201380043024.9A
Other languages
English (en)
Other versions
CN104584209B (zh
Inventor
钟智明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of CN104584209A publication Critical patent/CN104584209A/zh
Application granted granted Critical
Publication of CN104584209B publication Critical patent/CN104584209B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明公开了一种PoP(层叠封装)封装件，其包括具有被封装到封装剂中的衬底的底部封装件，其中裸片耦接到衬底的顶部。裸片的至少一部分暴露于底部封装件衬底上的封装剂上方。顶部封装件包括衬底，该衬底的前侧和背侧两者上均具有封装剂。顶部封装件衬底的背侧耦接到底部封装件衬底的顶侧，其中裸片的至少一部分位于顶部封装件衬底的背侧上的封装剂中的凹陷部中。

Description

薄型衬底PoP结构
技术领域
本发明涉及半导体封装以及用于封装半导体器件的方法。更具体地，本发明涉及使用薄型或无芯(coreless)衬底的PoP(层叠封装)。
背景技术
随着在半导体工业中对更低成本、更高性能、更大的集成电路密度和更大的封装密度的要求持续，层叠封装(“PoP”)技术已变得越来越普及。随着对越来越小的封装件的推进增强，裸片(die)和封装件的集成(例如，“预堆叠”或片上系统(“SoC”)技术与存储器技术的集成)允许更薄的封装件。此类预堆叠已成为细小间距PoP封装件的关键组成部分。
伴随细小间距PoP封装件所出现的问题是，随着PoP封装件中的顶部封装件或底部封装件上的端子(例如，球诸如焊料球)之间的间距减小，可能会发生翘曲。翘曲可能是由用于封装件(例如，衬底和施用于衬底的封装剂(encapsulant))的材料的热特性的差异所导致的。由于顶部封装件不附接到阻止翘曲的任何外部部件，因此顶部封装件可能尤其会出现翘曲问题。例如，可将底部封装件附接到印刷电路板，该印刷电路板有助于阻止底部封装件中的翘曲。
随着在顶部封装件中使用薄型或无芯衬底，可能进一步增加顶部封装件中的翘曲问题。薄型或无芯衬底可能具有较小的机械强度而不能抵抗由衬底和所施用的封装剂之间的热特性的差异所导致的效应。翘曲问题可能会导致PoP封装件的失效或性能降低和/或利用PoP封装件的设备的可靠性问题。
发明内容
在某些实施例中，一种用于PoP封装件的组装系统包括底部封装件和顶部封装件。底部封装件可包括耦接到裸片的衬底。衬底和裸片可被封装到封装剂中，其中裸片的至少一部分暴露于封装剂上方。裸片的至少一部分暴露于底部封装件衬底上的封装剂上方。顶部封装件可包括衬底，该衬底的前侧(顶部)和背侧(底部)两者上均具有封装剂。因为顶部封装件的两侧上均具有封装剂，所以可基本上平衡该顶部封装件中的热特性。平衡热特性可平衡顶部封装件上的热应力并减小或阻止顶部封装件中的翘曲。
在某些实施例中，顶部封装件衬底的背侧上的封装剂包括凹陷部。在一些实施例中，衬底的至少一部分暴露于凹陷部中。在其他实施例中，在凹陷部中基本上覆盖衬底。在某些实施例中，当耦接底部封装件和顶部封装件以形成PoP封装件时，顶部封装件中的凹陷部容纳耦接到底部封装件中的衬底的裸片(例如，裸片的至少一部分位于凹陷部中)。在一些实施例中，当将底部封装件耦接到顶部封装件时，底部封装件衬底的顶部上的端子(例如，焊料球)耦接到顶部封装件衬底的底部上的端子。
附图说明
当与附图结合时，参考根据本发明的目前优选的但仅为示例性的实施例的以下详细描述，将更充分地理解本发明的方法与装置的特征和优点，在该附图中：
图1示出了在组装前针对PoP(“层叠封装”)封装件的顶部封装件和底部封装件的实例的横截面表示。
图2示出了PoP封装件组装系统的实施例的横截面表示。
图3示出了在衬底上方施用封装剂期间所使用的模具版框的侧视图表示。
图4示出了PoP封装件组装系统的另选实施例的横截面表示。
图5示出了顶部封装件的底部视图表示，其中衬底暴露于凹陷部中。
图6示出了当将底部封装件耦接到顶部封装件时所形成的PoP封装件的实施例的横截面表示。
尽管本发明易受多种修改形式和替代形式的影响，但附图中以举例的方式示出了其具体实施例并将在本文中详细描述。附图可能不是按比例的。然而，应当理解，附图和详细描述并非旨在将本发明限制于所公开的特定形式，而正相反，其目的在于覆盖落在由所附权利要求所限定的本发明的实质和范围内的所有修改形式、等同形式和替代形式。
具体实施方式
图1示出了在组装前针对PoP(“层叠封装”)封装件的顶部封装件和底部封装件的实例的横截面表示(例如PoP封装系统)。PoP封装件组装系统100包括底部封装件102和顶部104。底部封装件102包括具有至少部分地覆盖衬底106的封装剂108的衬底。裸片110可使用端子112(例如焊料球)来耦接到衬底106并至少部分地覆盖于封装剂108中。端子114(例如焊料球)可耦接到衬底106的上(顶部)表面。端子115(例如焊料球)可耦接到衬底106的下(底部)表面。
顶部封装件104包括具有覆盖衬底116的上(顶部)表面的封装剂118的衬底。端子120(例如焊料球)耦接到衬底116的下(底部)表面。如图1中所示，顶部封装件104可能由于衬底116、封装剂118和端子120之间的不同热特性(例如热膨胀系数(“CTE”)和/或收缩率)而发生翘曲。翘曲可能导致问题，诸如但不限于在组装PoP封装件之后，底部封装件102中的端子114与顶部封装件104中的端子120之间失去连接。如果衬底116是相对薄型的衬底(例如，厚度小于约400μm)和/或衬底是无芯衬底(例如，仅由电介质聚合物和铜迹线所制成的衬底)，则顶部封装件104中的翘曲问题可能增大。
图2示出了PoP(“层叠封装”)封装件组装系统100'的实施例的横截面表示。系统100'包括底部封装件102'和顶部封装件104'。在某些实施例中，底部封装件102'包括衬底106。衬底106可以是例如封装件衬底或用于封装件的基础衬底。在某些实施例中，衬底106为无芯衬底。在一些实施例中，衬底106是带芯的薄型衬底。衬底106可具有小于约400μm的厚度。在一些实施例中，衬底106的厚度小于约200μm或小于约100μm。
裸片110可使用端子112和/或用于将裸片耦接到衬底的其他机构而被耦接到衬底106的上(顶部、顶侧或前侧)表面。裸片110可以是例如半导体芯片、集成电路裸片或倒装芯片裸片。在某些实施例中，裸片110是片上系统(“SoC”)。在某些实施例中，端子114耦接到衬底106的顶部。端子115可耦接到衬底106的下(底部、底侧或背侧)表面。端子112、114和/或115可包括但不限于由例如焊料或铜所制成的球、柱或塔。
在将裸片110和端子114耦接到衬底106之后，衬底的顶部(例如上表面)可由封装剂108至少部分地覆盖。封装剂108可以是例如聚合物或模塑化合物。在某些实施例中，封装剂108具有所选定的特性(例如，所选定的热特性)。例如，在一些实施例中，封装剂108具有介于约115℃和约190℃之间的玻璃化转变温度(Tg)。在一些实施例中，封装剂108具有在玻璃化转变温度以下介于约10ppm/℃和约38ppm/℃之间以及在玻璃化转变温度以上介于约40ppm/℃和约145ppm/℃之间的热膨胀系数(CTE)。在一些实施例中，封装剂108具有在25℃下介于约570kgf/mm2和约2400kgf/mm2之间的模量或在约260℃下具有介于约8kgf/mm2和约70kgf/mm2之间的模量。在某些实施例中，封装剂108具有尽可能接近衬底106的热特性的热特性。
在某些实施例中，裸片110至少部分地覆盖于封装剂108中，并且裸片的至少一部分暴露于封装剂上方，如图2中所示。在某些实施例中，使用模具版框来形成衬底106上方的封装剂108。图3示出了在衬底106上方施用封装剂108期间所使用的模具版框500的侧视图表示。如图3中所示，模具版框500具有当紧贴裸片110放置模具版框时阻止封装剂108覆盖裸片的顶表面的形状。在一些实施例中，在封装工艺期间将保护膜放置于裸片110的顶表面上方。当裸片接触模具版框500时，保护膜可保护裸片110免受损坏。保护膜可以是例如聚合物膜。
在某些实施例中，如图2中所示，端子114由封装剂108至少部分地覆盖。例如，端子114的至少一部分暴露于封装剂108上方，如图2中所示。在一些实施例中，当向衬底106施用封装剂时，端子114首先被封装剂108覆盖，然后移除封装剂的一部分以暴露端子的部分。例如，可使用诸如但不限于激光钻孔/消融的技术将端子114暴露于空腔中，从而暴露端子的部分，如图2中所示。在其他实施例中，使用平坦型处理来暴露端子114的部分，诸如但不限于机械研磨/切割处理。在一些实施例中，使用膜辅助模具(FAM)工艺来形成模具形状的封装剂108，该封装剂暴露端子114的部分(例如，模具形状具有用于端子的空腔，如图2中所示)。
在某些实施例中，端子114在衬底106上方具有由虚线122B所表示的高度，其高于由虚线122A所表示的衬底上方的封装剂108的高度。端子114可具有比封装剂108更高的高度，以确保底部封装件102'中的端子与顶部封装件104'中的端子(例如端子120)之间的连接。
在某些实施例中，顶部封装件104'包括衬底116。衬底116可以是例如封装件衬底或用于封装件的基础衬底。在某些实施例中，衬底116是无芯衬底。在一些实施例中，衬底116是带芯的薄型衬底。衬底116可具有小于约400μm的厚度。在一些实施例中，衬底116的厚度小于约200μm或小于约100μm。
在某些实施例中，端子120耦接到衬底116的下(底部、底侧或背侧)表面。端子120可包括但不限于例如由焊料或铜所制成的球、柱或塔。可对准端子120以与底部封装件102'中的端子114连接。
衬底116的上(顶部、顶侧或前侧)表面可由封装剂118至少部分地覆盖。封装剂118可以是与封装剂108相同的材料和/或具有与封装剂108类似的特性。在一些实施例中，封装剂118基本上覆盖衬底116的整个顶部，如图2中所示。
在某些实施例中，如图2中所示，顶部封装件104'的底部由封装剂124至少部分地覆盖。封装剂124可以是与封装剂108和/或封装剂118相同的材料和/或具有类似的特性。在某些实施例中，在封装剂124中形成凹陷部126。在一些实施例中，在封装/模塑工艺期间(例如，使用设计有凹陷部的模具版框空腔)形成凹陷部126。在其他实施例中，在封装/模塑工艺之后形成凹陷部126。例如，可使用机械研磨/切割工艺或激光钻孔/消融工艺来形成凹陷部126。
在某些实施例中，如图2中所示，凹陷部126被形成，其中在凹陷部中留下至少一些封装剂124(例如，封装剂124在凹陷部中基本上覆盖或包封衬底116，并且衬底未暴露于凹陷部中)。在一些实施例中，顶部封装件衬底暴露于凹陷部中。图4示出了PoP(“层叠封装”)封装件组装系统100″的实施例的横截面表示。如图4中所示，顶部封装件104″包括具有凹陷部126'的封装剂124。衬底116至少部分地暴露于凹陷部126'中。在某些实施例中，衬底116基本上暴露于凹陷部126'中。图5示出了其中衬底116暴露于凹陷部126'中的顶部封装件104″的底部视图表示。
在某些实施例中，凹陷部126(或凹陷部126')的尺寸设定成当将顶部封装件104'(或顶部封装件104″)耦接到底部封装件102'时容纳裸片110的暴露部分。图6示出了当将底部封装件102'耦接到顶部封装件104'时所形成的PoP封装件600的实施例的横截面表示。如图6中所示，在凹陷部126(或凹陷部126')中容纳裸片110减小了PoP封装件600的总体厚度。
在某些实施例中，如图2和图4中所示，端子120的至少一些部分暴露于封装剂124上方。可暴露端子120以允许当将顶部封装件104'(或顶部封装件104″)耦接到底部封装件时端子120和端子114之间的互连，如图6中所示。
在一些实施例中，当向衬底116施用封装剂时，首先由封装剂124覆盖端子120，然后移除封装剂的一部分以暴露端子的部分。例如，可使用诸如但不限于激光钻孔/消融的技术将端子120暴露于空腔中，从而暴露端子的部分。图2和图4中所示的端子120A示出了通过空腔型处理所暴露的端子的实例。在一些实施例中，使用平坦型处理来暴露端子120的部分，诸如但不限于机械研磨/切割处理。图2和图4中所示的端子120B示出了通过平坦型处理所暴露的端子的实例。在一些实施例中，使用膜辅助模具(FAM)工艺来形成模具形状的封装剂124，该封装剂暴露端子120的部分(例如，模具形状具有用于端子的空腔，或是平坦的但暴露端子的部分)。
端子114可具有比封装剂108更高的高度，以确保底部封装件102'中的端子与顶部封装件104'中的端子(例如端子120)之间的连接。
如上文针对图2-图6中所示的实施例所述的，除了利用封装剂118覆盖顶部封装件104'(或顶部封装件104″)的顶部(前侧)之外，还利用封装剂124至少部分地覆盖顶部封装件的底部(背侧)，这样可形成具有基本上平衡的热特性的顶部封装件结构(例如，在顶部封装件的背侧和前侧上具有封装剂平衡了热特性，诸如但不限于顶部封装件的CTE和收缩率)。平衡顶部封装件中的热特性可平衡顶部封装件上的热应力，并减小或阻止顶部封装件中的翘曲，尤其针对具有薄型或无芯衬底的顶部封装件。减少顶部封装件中的翘曲可改善预堆叠并改善具有小间距(例如端子之间减小的间距)和薄型或无芯衬底的PoP封装件的可靠性。此外，在封装剂124中的凹陷部126(或凹陷部126')中容纳来自底部封装件的裸片以允许PoP封装件保持减小(或薄)的总体PoP封装件厚度。
本文所述的实施例描述了用于形成具有顶部封装件的PoP封装件的结构和方法，在该顶部封装件的两侧上均具有封装剂。然而，对于本领域的技术人员而言将显而易见的是，可将本文所述的实施例与印刷电路板上和/或模块/系统级组件中的表面安装技术(SMT)一起使用以应用于底部封装件。
根据本说明书，本发明各个方面的其他修改和替代实施例对于本领域的技术人员而言将是显而易见的。因此，将本说明书理解为仅是示例性的并且目的是教导本领域的技术人员该执行本发明的一般方式。应当理解，本文所示和所述的本发明的形式将被当做目前优选的实施例。元素与材料可被本文所示和所述的那些元素与材料所替代，可反向部件和工艺并且可独立地利用本发明的某些特征，在受益于本发明的本说明书之后，所有这些对于本领域的技术人员而言都将是显而易见的。可在不脱离以下权利要求书中所描述的本发明的实质和范围的情况下对本文所述的元素作出修改。

Claims (18)

1.一种半导体器件封装组件，包括：
具有第一封装剂的第一衬底，所述第一封装剂至少部分地覆盖所述第一衬底的顶部；
耦接到所述第一衬底的所述顶部的裸片，其中所述裸片至少部分地被封装于所述第一封装剂中，其中所述裸片的至少一部分暴露于所述第一封装剂上方；以及
具有第二封装剂和第三封装剂的第二衬底，所述第二封装剂至少部分地覆盖所述第二衬底的顶部，并且第三封装剂至少部分地覆盖所述第二衬底的底部；
其中所述第二衬底的所述底部耦接到所述第一衬底的所述顶部；并且
其中所述裸片的至少一部分位于所述第三封装剂中的凹陷部中。
2.根据权利要求1所述的组件，其中所述第一衬底和所述第二衬底是无芯衬底。
3.根据权利要求1所述的组件，其中所述第三封装剂在所述凹陷部中基本上覆盖所述第二衬底的所述底部。
4.根据权利要求1所述的组件，其中所述第二衬底的至少一部分暴露于所述凹陷部中。
5.根据权利要求1所述的组件，还包括耦接到所述第一衬底的所述顶部的一个或多个第一端子，其中所述第一端子的至少一些部分暴露于所述第一封装剂上方。
6.根据权利要求1所述的组件，还包括耦接到所述第二衬底的所述底部的一个或多个第二端子，其中所述第二端子的至少一些部分暴露于所述第三封装剂下方。
7.根据权利要求1所述的组件，其中所述第二衬底的所述底部通过一个或多个端子耦接到所述第一衬底的所述顶部。
8.一种半导体器件封装组件，包括：
底部封装件，所述底部封装件包括第一衬底，所述第一衬底上方具有第一封装剂；
裸片，所述裸片位于所述第一衬底上方并且耦接到所述第一衬底，其中所述裸片至少部分地被封装于所述第一衬底上方的所述第一封装剂中，其中所述裸片的至少一部分暴露于所述第一封装剂外；以及
顶部封装件，所述顶部封装件耦接到所述底部封装件，其中所述顶部封装件包括第二衬底，所述第二衬底上方具有第二封装剂并且所述第二衬底下方具有第三封装剂，并且其中所述第三封装剂包括凹陷部，所述裸片的暴露部分的至少一部分位于所述凹陷部中。
9.根据权利要求1所述的组件，其中所述第一衬底和所述第二衬底的厚度小于400μm。
10.根据权利要求1所述的组件，其中所述第三封装剂在所述凹陷部中基本上包封所述第二衬底。
11.根据权利要求1所述的组件，其中所述第二衬底的至少一部分暴露于所述凹陷部中。
12.根据权利要求1所述的组件，还包括一个或多个端子，其中所述端子将所述第一衬底耦接到所述裸片。
13.一种用于形成半导体器件封装组件的方法，包括：
将裸片耦接到第一衬底的顶表面；
将所述第一衬底的所述顶表面封装到第一封装剂中，其中所述裸片的至少一部分暴露于所述第一封装剂上方；
将第二衬底的顶表面封装到第二封装剂中；
将所述第二衬底的底表面封装到第三封装剂中，其中所述第三封装剂包括凹陷部；以及
将所述第一衬底的所述顶表面耦接到所述第二衬底的所述底表面，使得所述裸片的至少一部分位于所述第三封装剂中的所述凹陷部中。
14.根据权利要求13所述的方法，还包括模塑所述第三封装剂以形成所述凹陷部。
15.根据权利要求13所述的方法，还包括移除所述第三封装剂的一部分以形成所述凹陷部。
16.根据权利要求13所述的方法，还包括将一个或多个第一端子耦接到所述第一衬底的所述顶表面，其中所述第一端子的至少一些部分暴露于所述第一封装剂上方。
17.根据权利要求13所述的方法，还包括将一个或多个第二端子耦接到所述第二衬底的所述底表面，其中所述第二端子的至少一些部分暴露于所述第三封装剂下方。
18.根据权利要求13所述的方法，还包括将一个或多个第一端子耦接到一个或多个第二端子，其中所述一个或多个第一端子耦接到所述第一衬底的表面的所述顶部，所述一个或多个第二端子耦接到所述第二衬底的所述底表面。
CN201380043024.9A 2012-08-15 2013-08-14 薄型衬底PoP结构 Active CN104584209B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/586,375 US8546932B1 (en) 2012-08-15 2012-08-15 Thin substrate PoP structure
US13/586,375 2012-08-15
PCT/US2013/055018 WO2014028670A1 (en) 2012-08-15 2013-08-14 THIN SUBSTRATE PoP STRUCTURE

Publications (2)

Publication Number Publication Date
CN104584209A true CN104584209A (zh) 2015-04-29
CN104584209B CN104584209B (zh) 2018-01-19

Family

ID=49004084

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380043024.9A Active CN104584209B (zh) 2012-08-15 2013-08-14 薄型衬底PoP结构

Country Status (7)

Country Link
US (2) US8546932B1 (zh)
EP (1) EP2885812B1 (zh)
JP (1) JP6134795B2 (zh)
KR (1) KR101720441B1 (zh)
CN (1) CN104584209B (zh)
TW (1) TWI553801B (zh)
WO (1) WO2014028670A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511399A (zh) * 2017-07-06 2018-09-07 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8546193B2 (en) * 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
US8546932B1 (en) * 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure
US8963311B2 (en) 2012-09-26 2015-02-24 Apple Inc. PoP structure with electrically insulating material between packages
TW201415602A (zh) * 2012-10-09 2014-04-16 矽品精密工業股份有限公司 封裝堆疊結構之製法
US9287317B2 (en) * 2013-01-25 2016-03-15 Samsung Electro-Mechanics Co., Ltd. Image sensor module and method of manufacturing the same
US8970024B2 (en) * 2013-03-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding material forming steps
US9064718B1 (en) 2014-05-07 2015-06-23 Freescale Semiconductor, Inc. Pre-formed via array for integrated circuit package
US10032652B2 (en) * 2014-12-05 2018-07-24 Advanced Semiconductor Engineering, Inc. Semiconductor package having improved package-on-package interconnection
TWI576976B (zh) * 2015-08-28 2017-04-01 欣興電子股份有限公司 無核心層封裝結構
KR102457119B1 (ko) 2015-09-14 2022-10-24 삼성전자주식회사 반도체 패키지의 제조 방법
JP2018026395A (ja) * 2016-08-08 2018-02-15 ソニーセミコンダクタソリューションズ株式会社 撮像素子パッケージおよびカメラモジュール
US10658334B2 (en) * 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
CN110709986B (zh) * 2017-06-09 2023-08-08 株式会社村田制作所 电子部件模块
KR20190004964A (ko) * 2017-07-05 2019-01-15 삼성전자주식회사 반도체 패키지
KR102497572B1 (ko) 2018-07-03 2023-02-09 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
CN111524869A (zh) * 2019-02-01 2020-08-11 矽品精密工业股份有限公司 电子结构及其制法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303079A (ja) * 2005-04-19 2006-11-02 Akita Denshi Systems:Kk 積層型半導体装置及びその製造方法
US20100025837A1 (en) * 2006-10-24 2010-02-04 Lintec Corporation Composite semiconductor device, semiconductor package and spacer sheet used in the same, and method for manufacturing composite semiconductor device
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6201299B1 (en) 1999-06-23 2001-03-13 Advanced Semiconductor Engineering, Inc. Substrate structure of BGA semiconductor package
US6150730A (en) 1999-07-08 2000-11-21 Advanced Semiconductor Engineering, Inc. Chip-scale semiconductor package
TWI220781B (en) 2003-04-28 2004-09-01 Advanced Semiconductor Eng Multi-chip package substrate for flip-chip and wire bonding
TWI225299B (en) 2003-05-02 2004-12-11 Advanced Semiconductor Eng Stacked flip chip package
TWI228806B (en) 2003-05-16 2005-03-01 Advanced Semiconductor Eng Flip chip package
TWI236109B (en) 2004-02-26 2005-07-11 Advanced Semiconductor Eng Chip package
TWI237370B (en) 2004-07-30 2005-08-01 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
TWI242855B (en) 2004-10-13 2005-11-01 Advanced Semiconductor Eng Chip package structure, package substrate and manufacturing method thereof
TWI236048B (en) 2004-10-21 2005-07-11 Advanced Semiconductor Eng Method for flip chip bonding by utilizing an interposer with embeded bumps
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US20070139012A1 (en) 2005-11-01 2007-06-21 Aerovironment, Inc. Motive power dual battery pack
JP5230997B2 (ja) * 2007-11-26 2013-07-10 新光電気工業株式会社 半導体装置
JP2009252916A (ja) 2008-04-04 2009-10-29 Nec Electronics Corp 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
TWI368983B (en) 2008-04-29 2012-07-21 Advanced Semiconductor Eng Integrated circuit package and manufacturing method thereof
TWI372458B (en) 2008-05-12 2012-09-11 Advanced Semiconductor Eng Stacked type chip package structure
TW200947654A (en) 2008-05-12 2009-11-16 Advanced Semiconductor Eng Stacked type chip package structure and method of fabricating the same
KR101198411B1 (ko) * 2008-11-17 2012-11-07 삼성전기주식회사 패키지 온 패키지 기판
JP5340718B2 (ja) * 2008-12-24 2013-11-13 新光電気工業株式会社 電子装置の製造方法
JP5556072B2 (ja) 2009-01-07 2014-07-23 ソニー株式会社 半導体装置、その製造方法、ミリ波誘電体内伝送装置
TWI499024B (zh) 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8035235B2 (en) 2009-09-15 2011-10-11 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR101624973B1 (ko) 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
US8404518B2 (en) 2009-12-13 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
TWI451539B (zh) 2010-08-05 2014-09-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8466567B2 (en) 2010-09-16 2013-06-18 Stats Chippac Ltd. Integrated circuit packaging system with stack interconnect and method of manufacture thereof
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
KR101711479B1 (ko) 2010-10-06 2017-03-03 삼성전자 주식회사 반도체 패키지 장치 및 그의 검사 시스템
US8409923B2 (en) * 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8546932B1 (en) * 2012-08-15 2013-10-01 Apple Inc. Thin substrate PoP structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303079A (ja) * 2005-04-19 2006-11-02 Akita Denshi Systems:Kk 積層型半導体装置及びその製造方法
US20100025837A1 (en) * 2006-10-24 2010-02-04 Lintec Corporation Composite semiconductor device, semiconductor package and spacer sheet used in the same, and method for manufacturing composite semiconductor device
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511399A (zh) * 2017-07-06 2018-09-07 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
CN108511399B (zh) * 2017-07-06 2021-04-20 日月光半导体制造股份有限公司 半导体封装装置及其制造方法

Also Published As

Publication number Publication date
US20140048957A1 (en) 2014-02-20
KR101720441B1 (ko) 2017-03-27
US8546932B1 (en) 2013-10-01
CN104584209B (zh) 2018-01-19
JP2015525007A (ja) 2015-08-27
WO2014028670A1 (en) 2014-02-20
JP6134795B2 (ja) 2017-05-24
TWI553801B (zh) 2016-10-11
US8766424B2 (en) 2014-07-01
EP2885812A1 (en) 2015-06-24
EP2885812B1 (en) 2018-07-25
TW201413890A (zh) 2014-04-01
KR20150038318A (ko) 2015-04-08

Similar Documents

Publication Publication Date Title
CN104584209A (zh) 薄型衬底PoP结构
KR101749284B1 (ko) 패키지 적층의 집적 회로 패키징 시스템 및 그 제조 방법
US20080111224A1 (en) Multi stack package and method of fabricating the same
US20120153509A1 (en) Semiconductor package and manufacturing method therefor
US20070164407A1 (en) Double encapsulated semiconductor package and manufacturing method thereof
US20070273019A1 (en) Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier
JP5980566B2 (ja) 半導体装置及びその製造方法
WO2007083352A1 (ja) 半導体装置およびその製造方法
KR20130094336A (ko) 봉지된 다이, 이를 포함하는 마이크로일렉트로닉 패키지, 및 상기 마이크로일렉트로닉 패키지를 제조하는 방법
TWI430425B (zh) 採用凸塊技術之積體電路封裝件系統
US9082607B1 (en) Molded leadframe substrate semiconductor package
CN111613541A (zh) 半导体装置和制造半导体装置的方法
KR20150059963A (ko) 반도체 패키지의 제조방법
US11462461B2 (en) System in package for lower z height and reworkable component assembly
KR20140009799A (ko) 전자 소자의 패키지 및 제조 방법
JP4001608B2 (ja) 半導体装置および半導体装置の製造方法
KR100850213B1 (ko) 몰딩된 볼을 구비한 반도체 패키지 및 그 제조방법
US10461044B2 (en) Wafer level fan-out package and method of manufacturing the same
US20050046012A1 (en) Leadframe-based mold array package heat spreader and fabrication method therefor
KR101565016B1 (ko) 휨 개선을 위한 반도체 패키지 구조 및 방법
US20160190072A1 (en) Stacked semiconductor packages with cantilever pads
KR101391081B1 (ko) 플립칩 반도체 패키지 및 그 제조방법
US20080251910A1 (en) Fabricating method of semiconductor package and heat-dissipating structure applicable thereto
JP4823161B2 (ja) 半導体装置
US20240128185A1 (en) Semiconductor device and pre-forming adaptor thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant