CN108511399A - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

Info

Publication number
CN108511399A
CN108511399A CN201810113354.5A CN201810113354A CN108511399A CN 108511399 A CN108511399 A CN 108511399A CN 201810113354 A CN201810113354 A CN 201810113354A CN 108511399 A CN108511399 A CN 108511399A
Authority
CN
China
Prior art keywords
electronic building
building brick
semiconductor encapsulation
encapsulation device
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810113354.5A
Other languages
English (en)
Other versions
CN108511399B (zh
Inventor
叶昶麟
陈昱敞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN108511399A publication Critical patent/CN108511399A/zh
Application granted granted Critical
Publication of CN108511399B publication Critical patent/CN108511399B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

一种半导体封装装置包含衬底、安置于所述衬底上的电子组件以及封装主体。所述电子组件具有邻近于所述衬底的第一表面，以及与所述第一表面相对的第二表面。所述第二表面具有至少五个边缘，且所述封装主体包封所述电子组件，且暴露所述电子组件的所述第二表面。

Description

半导体封装装置及其制造方法
技术领域
本发明大体上涉及一种半导体封装装置及其制造方法。本发明涉及一种包含双侧模制结构的半导体封装装置及其制造方法。
背景技术
在比较性双侧半导体封装装置中，为了促进半导体封装装置中的散热，半导体装置的背侧(例如裸片)可从包封层暴露。然而，裸片与包封层之间的热膨胀系数(CTE)失配可引起应力，其可导致在一些实施方案中不合意的效应，例如半导体封装装置的翘曲、包封层上的损坏等。此类现象可例如在裸片与包封层之间的边界处出现。开裂或其它损坏可在靠近裸片拐角的包封层中出现。
发明内容
在一个方面中，一种半导体封装装置包含衬底、安置于所述衬底上的电子组件，以及封装主体。所述电子组件具有邻近于所述衬底的第一表面，以及与所述第一表面相对的第二表面。所述第二表面具有至少五个边缘，且所述封装主体包封所述电子组件，且暴露所述电子组件的所述第二表面。
另一方面，一种半导体封装装置包含衬底、安置于所述衬底上的电子组件，以及封装主体。所述电子组件具有邻近于所述衬底的第一表面，以及与所述第一表面相对的第二表面。由所述电子组件的第二表面的两个邻近边缘界定的至少一个角度大于约90度。所述封装主体包封所述电子组件，且暴露所述电子组件的第二表面。
附图说明
图1A说明根据本发明的第一方面的半导体封装装置的一些实施例的横截面视图。
图1B说明根据本发明的一些实施例的图1A中所示的半导体封装装置的仰视图。
图1C说明根据本发明的一些实施例的图1A中所示的半导体封装装置的放大部分的透视图。
图1D说明根据本发明的一些实施例的图1A中所示的半导体封装装置的放大部分的透视图。
图2A说明根据本发明的一些实施例的图1A中所示的半导体封装装置的放大部分的透视图。
图2B说明根据本发明的一些实施例的图1A中所示的半导体封装装置的仰视图。
图2C说明根据本发明的一些实施例的图1A中所示的半导体封装装置的放大部分的透视图。
图3A说明根据本发明的第二方面的半导体封装装置的一些实施例的横截面视图。
图3B说明根据本发明的一些实施例图3A中所示的半导体封装装置的仰视图。
图3C说明根据本发明的一些实施例的图3A中所示的半导体封装装置的放大部分的透视图。
图3D说明根据本发明的一些实施例的图3A中所示的半导体封装装置的放大部分的透视图。
图4A说明根据本发明的第三方面的半导体封装装置的一些实施例的横截面视图。
图4B说明根据本发明的第三方面的半导体封装装置的一些实施例的横截面视图。
图5说明根据本发明的第四方面的半导体封装装置的一些实施例的仰视图。
贯穿图式和详细描述使用共同参考标号指示相同或类似元件。从以下结合附图作出的详细描述将更加显而易见本发明。
具体实施方式
图1A说明根据本发明的第一方面的半导体封装装置1的一些实施例的横截面视图。半导体封装装置1包含衬底10；电子组件11a、11b和13；封装主体12、14；以及载体15。
衬底10可包含例如印刷电路板，例如，基于纸的铜箔层压件、复合铜箔层压件或聚合物浸渍的基于玻璃纤维的铜箔层压件。衬底10可包含互连结构10r，例如再分布层(RDL)或接地元件。衬底10具有表面101和与表面101相对的表面102。衬底10的表面101在本文中被称作顶部表面或第一表面，且所述衬底的表面102在本文中被称作底部表面或第二表面。
电子组件11a、11b安置于衬底10的顶部表面101上。电子组件11a可包含有源组件，例如集成电路(IC)芯片或裸片。电子组件11b可包含无源电子组件，例如电容器、电阻器或电感器。电子组件11a、11b中的每一或任一者可电连接到一或多个其它电子组件(例如另一电子组件11a或11b)和/或电连接到衬底10(例如RDL)。此类电连接可例如借助于倒装芯片或导线接合技术来实现。
封装主体12安置在衬底10的顶部表面101上，且覆盖或包封电子组件11a、11b。在一些实施例中，封装本体12包含具有填充剂的环氧树脂、模制化合物(例如环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、具有分散在其中的硅酮的材料，或其组合。
电子组件13安置在衬底10的底部表面102上。在一些实施例中，电子组件13可包含有源组件，例如集成电路(IC)芯片或裸片。电子组件13可通过衬底10内的互连结构10r电连接到电子组件11a、11b中的至少一者。电子组件13具有有源表面131和与有源表面131相对的背表面132。有源表面131可面向底部表面102。
封装主体14安置于衬底10的底部表面102上，且覆盖或包封电子组件13的第一部分，且暴露电子组件13的第二部分。在一些实施例中，封装主体14包含具有填充剂的环氧树脂、模制化合物(例如环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、具有分散在其中的硅酮的材料，或其组合。
载体15可包含(例如)印刷电路板，例如基于纸的铜箔层压体、复合铜箔层压体，或聚合物浸染的基于玻璃纤维的铜箔层压体。载体15具有表面151和与表面151相对的表面152。载体15的表面151在本文中被称作顶部表面或第一表面，且载体15的表面152在本文中被称作底部表面或第二表面。载体15可包含互连结构15r(例如包含一或多个通孔的互连结构)，其穿透载体15，且将载体15的顶部表面151电连接到载体15的底部表面152。
一或多个导电垫15p安置于载体15的顶部表面151上。一或多个导电垫10p安置于衬底10的底部表面102上。多个互连结构14c穿透封装主体14，且将衬底10的底部表面102上的导电垫10p电连接到载体15的顶部表面151上的导电垫15p。
热界面材料(TIM)15a安置于电子组件13的后表面132与载体15的顶部表面151之间。TIM 15接触电子组件的后表面132和载体15的顶部表面151，且可实现电子组件13的增强型散热。在一些实施例中，热界面材料15a可由适合于散热的焊料或其它材料(例如导热材料，例如包含金属的材料)代替。
图1B说明根据本发明的一些实施例的从电子组件13的后表面132看的半导体封装装置1的电子组件13的仰视图。
如图1B所示，电子组件13的后表面132具有八个边缘。由电子组件13的后表面132的两个邻近边缘界定的电子组件13的每一内角(θ)大于约90度。换句话说，由电子组件13的后表面132的两个邻近边缘界定的封装主体14的拐角的每一内角(θ)大于约90度。举例来说，所述角度为约100度或更大，约110度或更大，约120度或更大，或约135度或更大。在一些实施例中，电子组件13的后表面132具有任何合适数目的边缘，且由邻近边缘中的任何两个界定的每一内角大于约90度。
图1C说明根据本发明的一些实施例的半导体封装装置1的放大部分A(由图1A中的点线识别)的透视图。图1C示出电子组件13的拐角。
如图1C所示，除后表面132之外，电子组件13具有表面133、134、135和136。表面133邻近于后表面132，且大体上垂直于后表面132。表面134邻近于后表面132，且大体上垂直于后表面132。表面135邻近于后表面132，邻近于表面133和表面134并在其间延伸，且大体上垂直于后表面132。表面136邻近于表面135，且大体上平行于后表面132。表面136可安置于大体上平行于后表面132和衬底10的底部表面102并在其之间的平面上。在一些实施例中，通过去除由表面132、133和134界定的拐角的一部分，来形成表面135和136(例如从电子组件13的主体暴露)。在一些实施例中，电子组件13的拐角可界定大体上为棱镜的形状(例如大体上为三角棱镜的形状)的凹部或凹口。
封装主体14包封或覆盖表面136，且暴露表面133、134和135中的一或多者的一部分。举例来说，封装主体14的暴露表面相对于后表面132凹进。在一些实施例中，封装主体14可包封或覆盖表面133、134、135和136，使得封装主体14与后表面132大体上共面。在一些实施例中，由表面133和135界定和/或由表面134和135界定的封装主体14的拐角的内角大于约90度。
如上文所提到，为了促进半导体封装装置中的散热，半导体装置的后表面(例如裸片)可从包封层暴露。然而，归因于裸片与包封层之间的CTE失配，应力可集中在裸片的后表面的拐角(尤其在拐角的角度小于或等于约90度时)。此类应力集中可导致靠近裸片拐角的包封层中的开裂。对于图1A、图1B和图1C中描绘的实施例，电子组件13的暴露的后表面132以及电子组件13的后表面132的拐角具有界定大于约90度的一或多个角度的表面可实现应力在封装主体14中靠近电子组件13的拐角的释放或再分布，这可有助于避免开裂或其它损坏。
图1D说明根据本发明的一些实施例的半导体封装装置1的放大部分A的透视图。图1D示出电子组件13的拐角。图1D中所示的结构类似于图1C中所示的结构，因为电子组件13的拐角可界定大体上为棱镜的形状(例如大体上为三角棱镜的形状)的凹部或凹口，不同之处在于由表面132、133和134界定的拐角处的直角扩展缺失或去除。举例来说，表面135从后表面132延伸到电子组件13的有源表面131。图1D中所示的结构并不具有图1C中所示的结构的表面136。在一些实施例中，表面135大体上为矩形形状。
图2A说明根据本发明的一些实施例的半导体封装装置1的放大部分A的透视图。图2A示出电子组件13的拐角。
如图2A所示，除后表面132之外，电子组件13还具有表面133、134和236。表面133邻近于后表面132，且大体上垂直于后表面132。表面134邻近于后表面132，且大体上垂直于后表面132。表面236邻近于后表面132，且邻近于表面133和表面134且在其间延伸。由表面236以及表面132、133和134中的任一者界定的电子组件13的拐角的内角大于约90度。在一些实施例中，表面236大体上为三角形形状。在一些实施例中，通过去除由表面132、133和134界定的拐角的一部分来形成表面236。
封装主体14暴露表面133、134和236的一部分。举例来说，封装主体14的暴露表面相对于后表面132凹进。在一些实施例中，封装主体14可包封或覆盖表面133、134和236，使得封装主体14与后表面132大体上共面。在一些实施例中，由表面133和236界定或由表面134和236界定的封装主体14的内角大于约90度。
图2B说明根据本发明的一些实施例的从电子组件13的后表面132来看的半导体封装装置1的电子组件13的仰视图。
如图2B所示，电子组件13的后表面132具有八个边缘。由电子组件13的后表面132的两个邻近边缘界定的电子组件13的每一内角(θ)大于约90度。换句话说，由电子组件13的后表面132的两个邻近边缘界定的封装主体14的拐角的每一内角(θ)大于约90度。举例来说，所述角度为约100度或更大，约110度或更大，约120度或更大，或约135度或更大。在一些实施例中，电子组件13的后表面132具有任何合适数目的边缘，且由邻近边缘的任何两个界定的每一角度大于约90度。
图2C说明根据本发明的一些实施例的半导体封装装置1的放大部分A的透视图。图2C示出电子组件13的拐角。图2C中所示的结构类似于图2A中所示的结构，不同之处在于其省略了电子组件13的拐角的下部，且表面236从后表面132延伸到电子组件13的有源表面131。
对于图2A、2B和2C中描绘的实施例，电子组件13的暴露的后表面132以及电子组件13的后表面132的拐角具有限定大于约90度的一或多个角度的表面可实现应力在靠近电子组件13的拐角的封装主体14中的释放或再分布，这可帮助避免开裂或其它损坏。
图3A说明根据本发明的一些实施例的半导体封装装置2的一些实施例的横截面视图。半导体封装装置2类似于图1A中所示的半导体封装装置1，不同之处在于其包含电子组件33，而不是电子组件13或除电子组件13之外。电子组件33可类似于电子组件13，但可具有不同结构。由图3A中的点线识别的半导体封装装置的电子组件33的拐角部分B为圆形(例如大体上为弧形)。
图3B说明根据本发明的一些实施例的从电子组件33的后表面332来看的半导体封装装置2的电子组件33的仰视图。
如图3B所示，电子组件33的后表面332具有四个弧形边缘。由电子组件33的后表面332的边缘与邻近弧形边缘的切线界定的电子组件33的每一内角(θ1)大于约90度。换句话说，由电子组件33的后表面332的边缘与邻近弧形边缘的切线界定的封装主体14的每一内角(θ1)大于约90度。
图3C说明根据本发明的一些实施例的半导体封装装置2的放大部分B的透视图。图3C示出电子组件33的拐角。
如图3C所示，除后表面332之外，电子组件33具有表面333、334、335和336。表面333邻近于后表面332，且大体上垂直于后表面332。表面334邻近于后表面332，且大体上垂直于后表面332。表面335邻近于后表面332，邻近于表面333和表面334并在其之间延伸，且大体上垂直于后表面332。表面336邻近于表面335，且大体上平行于后表面332。在一些实施例中，通过去除由表面332、333和334界定的拐角的一部分来形成表面335和336。在一些实施例中，表面335是弯曲表面(例如连接表面333与表面334的弯曲表面)。在一些实施例中，电子组件33的拐角可限定凹部或凹口。
封装主体14包封或覆盖表面336，且暴露表面333、334和335的一部分。举例来说，封装主体34的暴露表面相对于后表面332凹进。在一些实施例中，封装主体14可包封或覆盖表面333、334、335和336，使得封装主体14与后表面332大体上共面。在一些实施例中，由表面333和335或表面334和335界定的封装主体14的拐角的内角大于约90度。
图3D说明根据本发明的一些实施例的半导体封装装置2的放大部分B的透视图。图3D示出电子组件33的拐角。图3D中所示的结构类似于图3C中所示的结构，不同之处在于由表面332、333和334界定的拐角处的直角扩展缺失或去除。举例来说，表面335从后表面332延伸到电子组件33的有源表面331。图3D中所示的结构省略图3C中所示的结构的表面336。在一些实施例中，表面335是弯曲表面。
对于图3A、3B、3C和3D中描绘的实施例，电子组件13的暴露的后表面132以及电子组件13的后表面132的拐角具有限定大于约90度的一或多个角度的表面可实现应力在靠近电子组件13的拐角的封装主体14中的释放或再分布，这可有助于避免开裂或其它损坏。
图4A说明根据本发明的一些实施例的半导体封装装置3A的横截面视图。半导体封装装置3A类似于图1A中所示的半导体封装装置1，不同之处在于半导体封装装置3A包含电子组件43，而不是电子组件13或除电子组件13之外。电子组件43可类似于电子组件13，但可具有不同结构。此外，半导体封装装置3A可不同于图1A中所示的半导体封装装置1，因为半导体封装装置3A的电子组件43的后表面432具有四个边缘，且电子组件43由封装主体14覆盖或包封(例如大体上完全覆盖或包封)。
另外，半导体封装装置3A可不同于图1A中所示的半导体封装装置1，因为半导体封装装置3A可包含多个热导体14v(例如至少部分填充有导热材料的通孔)，其穿透封装主体14，以将电子组件13的后表面132连接到TIM 15a。热导体14v可实现将电子组件13所产生的热量传输到TIM 15a，从而增加电子组件43的散热。
图4B说明根据本发明的一些实施例的半导体封装装置3B的横截面视图。半导体封装装置3B类似于图4A中所示的半导体封装装置3A，不同之处在于半导体封装装置3B可省略热导体14v。
另外，半导体封装装置3B可不同于图4A中所示的半导体封装装置3A，因为电子组件43的后表面432的一部分从封装主体14暴露。TIM 15a接触电子组件43的后表面432的暴露部分以及载体15，这可实现电子组件43的增加的散热。在一些实施例中，TIM 15a的顶部表面的面积小于电子组件43的后表面432的面积。在一些实施例中，电子组件43的后表面432从封装主体14暴露(例如大体上完全暴露)，且TIM 15a的顶部表面的面积大体上等于或大于电子组件43的后表面432的面积。
图5说明根据本发明的一些实施例的半导体封装装置4的仰视图。半导体封装装置4包含靠近在一起安置的电子组件51a、51b、51c和51d，以及覆盖或包封电子组件51a、51b、51c和51d的至少一部分的封装主体52，且因此应力集中可在图5中的点线所识别的区C处出现。如图5中所示，去除每一电子组件51a、51b、51c和51d的拐角的一部分(例如去除或省略最接近于其它电子组件的拐角的一部分，以本文所述的任何方式，使得电子组件51a、51b、51c和51d中的任一者是根据本文所描述的实施例)可有助于避免封装主体52的开裂。
如本文所使用，术语“大约”、“大体上”、“大体”和“约”用以描述和考虑小变化。当与事件或情形结合使用时，所述术语可指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差值小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同。举例来说，“基本上”平行可能是指相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。举例来说，“基本上”垂直可指相对于90°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么可认为所述两个表面是共面的或大体上共面的。
如本文所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”指代传递电流的能力。导电材料通常指示展现对于电流流动的极少或零对抗的那些材料。电导率的一个量度为西门子/米(S/m)。通常，导电材料是电导率大于约104S/m(例如至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外规定，否则在室温下测量材料的导电性。
在一些实施例的描述中，组件提供于另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个介入组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述并说明了本发明，但这些描述和说明并不限制本发明。所属领域的技术人员可清晰地理解，在不脱离如由所附权利要求书定义的本发明的真实精神和范围的情况下，可进行各种改变，且可在实施例内取代等效组件。所述说明可能未必按比例绘制。归因于制造过程中的变量等等，本发明中的艺术再现与实际设备之间可能存在区别。可存在并未特定说明的本发明的其它实施例。应将所述说明书和图式视为说明性的，而非限制性的。可做出修改，以使特定情况、材料、物质组成、方法或过程适应于本发明的目标、精神以及范围。所有此类修改意图在所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所发明的方法，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (23)

1.一种半导体封装装置，其包括：
衬底；
电子组件，其安置于所述衬底上，所述电子组件具有邻近于所述衬底的第一表面，
以及与所述第一表面相对的第二表面，其中所述第二表面具有至少五个边缘；以及
封装主体，其包封所述电子组件且暴露所述电子组件的所述第二表面。
2.根据权利要求1所述的半导体封装装置，其中由所述电子组件的所述第二表面的两个邻近边缘界定的所述第二表面的至少一个内角(θ)大于约90度。
3.根据权利要求1所述的半导体封装装置，其中由所述电子组件的所述第二表面的两个邻近边缘界定的所述封装主体的拐角的至少一个内角(θ)大于约90度。
4.根据权利要求1所述的半导体封装装置，其中
所述电子组件包含邻近于所述第二表面的第一侧表面，以及邻近于所述第二表面和第一侧表面的第二侧表面，
所述电组件进一步包含第一暴露表面和第二暴露表面，所述第一暴露表面大体上垂直于所述第二表面，且在所述第一侧表面与所述第二侧表面之间延伸，且所述第二暴露表面大体上平行于所述第二表面，且
所述电组件的拐角由所述第一侧表面、所述第二侧表面、所述第二表面、所述第一暴露表面和所述第二暴露表面界定。
5.根据权利要求4所述的半导体封装装置，由所述第一暴露表面以及所述第一侧表面和所述第二侧表面中的任一者界定的角度大于约90度。
6.根据权利要求4所述的半导体封装装置，其中所述封装主体覆盖所述第一侧表面的至少一部分、所述第二侧表面的至少一部分、所述第二暴露表面的至少一部分以及所述第一暴露表面的至少一部分。
7.根据权利要求4所述的半导体封装装置，其中所述第一暴露表面是弯曲表面。
8.根据权利要求1所述的半导体封装装置，其中
所述电组件包含邻近于所述第二表面的第一侧表面，以及邻近于所述第二表面和第一侧表面的第二侧表面，
所述电组件进一步包含在所述第一侧表面与所述第二侧表面之间延伸的暴露表面，且
所述电组件的拐角由所述第一侧表面、所述第二侧表面和所述暴露表面界定。
9.根据权利要求8所述的半导体封装装置，其中所述暴露表面的至少一部分、所述第一侧表面的至少一部分和所述第二侧表面的至少一部分由所述封装主体覆盖。
10.根据权利要求8所述的半导体封装装置，其中由所述暴露表面和所述第一侧表面或所述暴露表面和所述第二侧表面界定的角度大于约90度。
11.根据权利要求8所述的半导体封装装置，其中所述暴露表面是弯曲表面。
12.根据权利要求8所述的半导体封装装置，其中所述暴露表面从所述第二表面延伸到所述电组件的所述第一表面。
13.一种半导体封装装置，其包括：
衬底；
电子组件，其安置于所述衬底上，所述电子组件具有邻近于所述衬底的第一表面以及与所述第一表面相对的第二表面，其中由所述电子组件的所述第二表面的两个邻近边缘界定的至少一个角度大于约90度；以及
封装主体，其包封所述电子组件且暴露所述电子组件的所述第二表面。
14.根据权利要求13所述的半导体封装装置，其中由所述电子组件的所述第二表面的两个邻近边缘界定的所述封装主体的拐角的至少一个角度大于约90度。
15.根据权利要求13所述的半导体封装装置，其中
所述电子组件包含邻近于所述第二表面的第一侧表面，以及邻近于所述第二表面和所述第一侧表面的第二侧表面，
所述电组件进一步包含第一暴露表面和第二暴露表面，所述第一暴露表面大体上垂直于所述第二表面，且在所述第一侧表面与所述第二侧表面之间延伸，且所述第二暴露表面大体上平行于所述第二表面，且
所述电组件的拐角由所述第一侧表面、所述第二侧表面、所述第一暴露表面和所述第二暴露表面界定。
16.根据权利要求15所述的半导体封装装置，其中由所述第一暴露表面以及所述第一侧表面和所述第二侧表面中的任一者界定的角度大于约90度。
17.根据权利要求15所述的半导体封装装置，其中所述封装主体覆盖所述第一侧表面的至少一部分、所述第二侧表面的至少一部分、所述第二暴露表面的至少一部分和所述第一暴露表面的至少一部分。
18.根据权利要求15所述的半导体封装装置，其中所述第一暴露表面是弯曲表面。
19.根据权利要求13所述的半导体封装装置，其中
所述电子组件包含邻近于所述第二表面的第一侧表面，以及邻近于所述第二表面和所述第一侧表面的第二侧表面，
所述电组件进一步包含在所述第一侧表面与所述第二侧表面之间延伸的暴露表面，且
所述电组件的拐角由所述第一侧表面、所述第二侧表面和所述暴露表面界定。
20.根据权利要求19所述的半导体封装装置，其中所述暴露表面的至少一部分、所述第一侧表面的至少一部分和所述第二侧表面的至少一部分由所述封装主体覆盖。
21.根据权利要求19所述的半导体封装装置，其中由所述暴露表面和所述第一侧表面或所述暴露表面和所述第二侧表面界定的所述封装主体的拐角的角度大于约90度。
22.根据权利要求19所述的半导体封装装置，其中所述第三暴露表面是弯曲表面。
23.根据权利要求19所述的半导体封装装置，其中所述暴露表面从所述第二表面延伸到所述电组件的所述第一表面。
CN201810113354.5A 2017-07-06 2018-02-05 半导体封装装置及其制造方法 Active CN108511399B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/643,470 2017-07-06
US15/643,470 US10096578B1 (en) 2017-07-06 2017-07-06 Semiconductor package device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN108511399A true CN108511399A (zh) 2018-09-07
CN108511399B CN108511399B (zh) 2021-04-20

Family

ID=63374951

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810113354.5A Active CN108511399B (zh) 2017-07-06 2018-02-05 半导体封装装置及其制造方法

Country Status (2)

Country Link
US (1) US10096578B1 (zh)
CN (1) CN108511399B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11239168B2 (en) 2019-07-30 2022-02-01 Industrial Technology Research Institute Chip package structure
US11682626B2 (en) * 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335594A (ja) * 1994-06-06 1995-12-22 Murata Mfg Co Ltd 半導体装置および半導体装置の面取り方法
US20050042804A1 (en) * 2003-08-20 2005-02-24 Kim Tae Hoon Method for fabricating surface acoustic wave filter packages and package sheet used therein
JP2007081131A (ja) * 2005-09-14 2007-03-29 Kyocera Corp 単結晶ウエハ及びそれを用いたエピタキシャル成長用基板
US20080006900A1 (en) * 2004-10-21 2008-01-10 Infineon Technologies Ag Semiconductor Package and Method for Producing the Same
CN104584209A (zh) * 2012-08-15 2015-04-29 苹果公司 薄型衬底PoP结构
CN105552059A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装结构和半导体工艺
WO2016146199A1 (en) * 2015-03-19 2016-09-22 Osram Opto Semiconductors Gmbh A window for covering an optoelectronic semiconductor chip, a panel comprising a plurality of windows, a method for producing windows and an optoelectronic semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130328220A1 (en) 2012-06-12 2013-12-12 KyungHoon Lee Integrated circuit packaging system with film assist and method of manufacture thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335594A (ja) * 1994-06-06 1995-12-22 Murata Mfg Co Ltd 半導体装置および半導体装置の面取り方法
US20050042804A1 (en) * 2003-08-20 2005-02-24 Kim Tae Hoon Method for fabricating surface acoustic wave filter packages and package sheet used therein
US20080006900A1 (en) * 2004-10-21 2008-01-10 Infineon Technologies Ag Semiconductor Package and Method for Producing the Same
JP2007081131A (ja) * 2005-09-14 2007-03-29 Kyocera Corp 単結晶ウエハ及びそれを用いたエピタキシャル成長用基板
CN104584209A (zh) * 2012-08-15 2015-04-29 苹果公司 薄型衬底PoP结构
CN105552059A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装结构和半导体工艺
WO2016146199A1 (en) * 2015-03-19 2016-09-22 Osram Opto Semiconductors Gmbh A window for covering an optoelectronic semiconductor chip, a panel comprising a plurality of windows, a method for producing windows and an optoelectronic semiconductor device

Also Published As

Publication number Publication date
CN108511399B (zh) 2021-04-20
US10096578B1 (en) 2018-10-09

Similar Documents

Publication Publication Date Title
CN108511399A (zh) 半导体封装装置及其制造方法
US10128214B2 (en) Substrate and the method to fabricate thereof
US10566320B2 (en) Method for fabricating electronic package
CN109755187B (zh) 半导体封装装置及其制造方法
US8482134B1 (en) Stackable package and method
CN108878396A (zh) 半导体封装装置及其制造方法
CN108573934A (zh) 半导体装置封装及其制造方法
CN109003963B (zh) 半导体封装及制造其的方法
US10615105B2 (en) Semiconductor device package and method of manufacturing the same
US10763244B2 (en) Power module having power device connected between heat sink and drive unit
CN103050462A (zh) 半导体器件封装件及方法
KR102228461B1 (ko) 반도체 패키지 장치
EP3577684B1 (en) Power semiconductor module
CN108735686A (zh) 半导体封装装置和其制造方法
CN109390293A (zh) 半导体封装装置及其制造方法
US6975025B2 (en) Semiconductor chip package and method of manufacturing same
US11145621B2 (en) Semiconductor package device and method of manufacturing the same
TW201530667A (zh) 晶片封裝體結構及其形成方法
JP2016536780A (ja) 回路装置及び該回路装置の製造方法
US11150710B2 (en) Apparatuses and methods for encapsulated devices
CN109427725A (zh) 中介基板及其制法
TWI313915B (en) Structure for stress releasing in an electronic package and fabricating the same
CN201229938Y (zh) 芯片封装结构
CN112349711A (zh) 半导体设备封装
CN106024738A (zh) 具有倾斜侧壁的半导体器件及相关方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant