1313915 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種應力釋放之電子構裝架構與方法，特別是 有關一種具應力釋放層或應力緩衝層的電子構裝架構與方法。 【先前技術】 隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路 元件高密度化，積體電路晶片所呈現的功能越強，而搭配的被動 元件數量亦隨之遽增，特別是消費性電子產品。再者，在電子產 品強調輕薄短小之際，如何在有限的構裝空間中容納數目龐大的 電子元件，已成為電子構裝業者急待解決與克服的技術瓶頸。為 了解決此一問題，構裝技術逐漸走向單構裝系統（System in Package，SIP)的系統整合階段，特別是多晶片模組（Multi-Chip Module，MCM)的構裝，其埋藏式主、被動元件技術(embedded technology)與表面積層技術(build up)成為關鍵技術。藉由元件 的内埋化，可使構裝體積大幅度縮小，讓多餘的空間能放入更多 高功能性元件；表面積層技術則可以提高線路密度、縮小元件厚 度，藉此提高產品整體的構裝密度。 然而，當構裝面積大幅度縮小，接點密度越來越高的同時， 可靠度的問題也越來越嚴重。造成可靠度降低的主要原因之一， 係由於構裝體内部積層（build-up layers)架構中，因熱膨脹係 數不匹配所產生應力集中的問題，另外也可能因環境溫度變化而 1313915 產生翹曲的現象，或者電路基板與構裝體之間因熱膨脹係數不匹 配所造成凸塊之接點可靠度問題’都可能會造成構裝元件的失效。 為了改善上述問題，有人提出了各種構裝架構或方法。美國 專利第 5,757,072 號（題為”Structure for Protecting Air Bridges on Semiconductor Chips from Damage”）提出一種 於高密度連接導線（High Density Interconnect，HDI)結構中， p 使用保護蓋(protective cap)的概念。如第一圖所示的剖面圖，以 保護蓋130覆蓋於基板110中的晶片120,用以增加其強度，且 使其在製程當中不受污染。此種保護蓋130的製作方法複雜，製 程成本也較高，而且和傳統的構裝或半導體製程之相容度較低。 美國專利第 6,586,836 號（題為”Process for Forming Microelectronic Packages and Intermediate Structures Formed therewith”）使用對稱結構來降低内埋式晶片之翹曲現 象(warpage)’以改善因為翹曲所產生的應力集中而導致晶片失效 的情形。第二圖顯示結構剖面圖，其將晶片230以背對背（back to back)的方式對稱的黏貼在基板210上；晶片230與晶片230之 間以及邊緣處則填充封膠材料(encapsul这tion material) 2 2 0。 這種方式只能應用於多晶片且對稱的構裝結構，因此可適用的範 圍較小_。 1313915 美國專利第 5,866,952號（題為”High Density Interconnected Circuit Module with a Compliant Layer as Part of a Stress-reducing Molded Substrate”）提出一種使用 柔性層（compliant layer)以降低因熱膨脹係數差異所引起的應 力。如第三圖所示，晶片320與晶片型電容330部份埋入或黏貼 於基板310上，晶片320、晶片型電容330之間則填充以柔性層 340，再以積層方式將黏結層370、高分子介電層360與金屬導 φ 線350製作於晶片320上。然而，此文獻所使用的柔性層受限於 材質的選擇，造成實施應用上的不便。 美國專利第 5,786,988 號（題為"Integrated Circuit Chips1313915 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electronically mounted architecture and method for stress relief, and more particularly to an electronic architecture and method having a stress relief layer or a stress buffer layer. [Prior Art] As the demand for electronic products is toward higher functionality, higher signal transmission speed, and higher density of circuit components, the more powerful the integrated circuit chip exhibits, the more the number of passive components is increased. It is a consumer electronics product. Moreover, how to accommodate a large number of electronic components in a limited configuration space has become a technical bottleneck that electronic assembly operators urgently need to solve and overcome when electronic products emphasize lightness and shortness. In order to solve this problem, the packaging technology gradually moves toward the system integration phase of the System in Package (SIP), especially the multi-Chip Module (MCM), which is buried in the main mode. Embedded technology and surface-up technology have become key technologies. By embedding the components, the bulk of the package can be greatly reduced, allowing extra space to be placed in more highly functional components. The surface layer technology can increase the line density and reduce the thickness of the components, thereby improving the overall product. Construction density. However, as the construction area is greatly reduced and the contact density is getting higher and higher, the reliability problem is becoming more and more serious. One of the main reasons for the decrease in reliability is the stress concentration caused by the mismatch of thermal expansion coefficients in the build-up layers structure of the structure, and the warpage of 1313915 may also occur due to changes in ambient temperature. The phenomenon, or the joint reliability problem of the bump caused by the mismatch of the thermal expansion coefficient between the circuit board and the structure, may cause the failure of the component. In order to improve the above problems, various architectures or methods have been proposed. U.S. Patent No. 5,757,072 ("Structure for Protecting Air Bridges on Semiconductor Chips from Damage") proposes a concept of using a protective cap in a High Density Interconnect (HDI) structure. As shown in the first cross-sectional view, the protective cover 130 covers the wafer 120 in the substrate 110 to increase its strength and protect it from contamination during the process. Such a protective cover 130 is complicated in manufacturing method, high in process cost, and low in compatibility with a conventional package or semiconductor process. U.S. Patent No. 6,586,836 ("Process for Forming Microelectronic Packages and Intermediate Structures Formed therewith") uses a symmetrical structure to reduce the warpage of a buried wafer to improve stress concentration due to warpage. The case of wafer failure. The second figure shows a cross-sectional view of the structure in which the wafer 230 is symmetrically adhered to the substrate 210 in a back-to-back manner; the encapsulation material is encapsulated between the wafer 230 and the wafer 230 and at the edges. 2 2 0. This method can only be applied to multi-wafer and symmetrical structures, so the applicable range is small. 1313915 U.S. Patent No. 5,866,952 ("High Density Interconnected Circuit Module with a Compliant Layer as Part of a Stress-reducing Molded Substrate") proposes to use a compliant layer to reduce the stress caused by the difference in thermal expansion coefficient. As shown in the third figure, the wafer 320 and the chip capacitor 330 are partially embedded or adhered to the substrate 310, and the wafer 320 and the chip capacitor 330 are filled with a flexible layer 340, and the bonding layer 370 is laminated. The polymer dielectric layer 360 and the metal lead φ line 350 are formed on the wafer 320. However, the flexible layer used in this document is limited by the choice of materials, causing inconvenience in implementation. U.S. Patent No. 5,786,988 (titled "Integrated Circuit Chips
Made Bendable by Forming Indentations in Their Back Surfaces Flexible Packages thereof and Methods ofMade Bendable by Forming Indentations in Their Back Surfaces Flexible Packages thereof and Methods of
Manufacture”）係利用在晶片背®增加切割裂縫的方式，使晶片Manufacture") uses wafers on the back of the wafer to increase the cutting crack to make the wafer
具有些許的可撓性，可以應用在晶片型信用卡或智慧卡上。第四A 圖顯示出晶片卡40中的晶片420及裂縫的配置；第四B圖則顯 示局部剖面圖，晶片420的背面切割有裂缝結構，晶片420製於 ， 卡片主體410中心螻空的部分，上下則為高分子保護層430。此 ' 方法在晶片上所留下的裂縫可能導致強度下降，而使晶片容易破 裂。 鑑於傳統構裝技術所存在的諸多缺點，亟需提出一種有效釋放應 力的電子構裝架構與方法，以改善應力集中問題、翹曲現象、或 1313915 凸塊接點可靠度問題。 【發明内容】 本發明的目的在於提出一種能夠有效釋放應力的電子構裝架 構與方法，以改善構裝體内部積層（build-up layers)架構中， '因熱膨脹係數不匹配所產生的應力集中問題、或者因環境溫度變 化所產生的龜曲現象。 本發明的另一目的在於提出一種應力釋放之電子構裝架構與 方法，以改善電路基板與構裝體之間因熱膨脹係數不匹配所造成 凸塊之接點可靠度問題。 本發明的又一目的在於提出一種應力釋放之電子構裝架構與 方法，其製程簡單、成本低、與傳統構裝或半導體製程之相容度 高、其結構之可適用範圍大、材質之選擇彈性大、且構裝體強度 大。 根據上述的目的，本發明揭露一種應力釋放之電子構裝架構與方 法。根據本發明實施例，具有電極的電子元件承載於支撐基板上， 並於電子元件上覆蓋至少一層介電層，其中，介電層内有連接導 線，其電性連接於電子元件的電極。位於支撐基板、介電層之間， 或者位於相鄰介電層之間則形成有應力防護層，其可以為應力釋 放層、應力緩衝層、或者其組合。 【實施方式】 第五A圖至第五Η圖顯示本發明之應力釋放電子構裝架構及 卡d的雙一 ♦你⑹—a J—：卑rp' Λ 園ώί·夭$皂|系国，膝本；JL六费终 9 •1313915 或鲜塾S〇2的電子元件5〇1固定或黏著於支撐基板503上。在 本實施例中，電子元件501可以是一種用於内埋式構裝的元件， 例如主# _ ^ L ^ 、 勒几件中的具積艘電路晶片基板（底下簡稱積體電路基板 01 )或被動元件中的晶片塑電容、電阻、電感等等；支撐基板可 ' Μ為硬式或軟式 高分子基板、或金屬基板’例如一或多層之印刷 電5^-拓 ,. °接著，形成遮罩廣506於支撑基板503的部分表面，如 第五B ~ 鲁 圖所示。在本實施例中，係以高分子薄膜層506來實施此 遮罩層 ’然而其它材質的薄膜層或者一般的遮罩（mask)也都可 X適用。高分子薄臈層5〇6的形成可以採用印刷、沈積、塗佈、 熱壓八、β ° 或黏貼方式。於形成高分子薄膜層506之後，全面施以 表面處理511 (例如棕化或黑棕化處理），其原理為粗糙化表面， 目的在於改善未被高分子薄膜層506遮蓋住而顯露出來的支撐基 503表面之黏著特性，以增強後續製程中與介電層之介面黏 鲁 + 於第五C圖所示的步驟中，將高分子薄膜層506除去。由於 肉刀子薄祺層506所覆蓋的表面沒有受到栋化或黑棕化處理，因 匕其介面黏著特性仍然很差。接下來，如第五D圖所示，以印刷、 &積、塗佈、熱壓合、或其它適當的技術形成第一介電層5〇4於 積體電路基板501與支撐基板503之上。其中，第一介電層504 的材質可以使用一般構裝所使用的材質，例如高分子材料。由於 支撐基板503的一部份表面沒有受到棕化或黑棕化處理，因此與 第一介電層504之介面黏著特性較差，自然形成了具有分離空間With a little flexibility, it can be applied to chip-type credit cards or smart cards. The fourth A diagram shows the arrangement of the wafer 420 and the crack in the wafer card 40; the fourth B shows a partial cross-sectional view, the back surface of the wafer 420 is cut with a crack structure, and the wafer 420 is formed in the hollowed-out portion of the card main body 410. The upper and lower layers are the polymer protective layer 430. The crack left by this 'method on the wafer may cause a drop in strength and make the wafer susceptible to cracking. In view of the shortcomings of traditional packaging technology, it is urgent to propose an electronic assembly structure and method for effectively releasing stress to improve stress concentration problems, warpage, or 1313915 bump contact reliability. SUMMARY OF THE INVENTION It is an object of the present invention to provide an electronic package structure and method capable of effectively releasing stress to improve stress concentration caused by mismatch of thermal expansion coefficients in a build-up layers architecture of a package. Problems, or tortuosity caused by changes in ambient temperature. Another object of the present invention is to provide a stress-releasing electronic structure and method for improving the reliability of bump contact between a circuit substrate and a package due to a mismatch in thermal expansion coefficient. Another object of the present invention is to provide a stress-releasing electronic structure structure and method, which has a simple process, low cost, high compatibility with a conventional structure or a semiconductor process, a large applicable range of the structure, and a material selection. The elasticity is large and the strength of the structure is large. In accordance with the above objects, the present invention discloses an electronically mounted architecture and method for stress relief. According to an embodiment of the invention, an electronic component having an electrode is carried on a support substrate, and the electronic component is covered with at least one dielectric layer, wherein the dielectric layer has a connection wire electrically connected to the electrode of the electronic component. A stress protection layer may be formed between the support substrate, the dielectric layer, or between adjacent dielectric layers, which may be a stress relief layer, a stress buffer layer, or a combination thereof. [Embodiment] The fifth to fifth figures show the stress-releasing electronic structure of the present invention and the double one of the card d. You (6)-a J-: rp rp Λ ώ ώ 夭 夭 皂 皂 皂 皂 皂 皂, knee-length; JL six-fee final 9 • 1313915 or fresh 塾 S〇 2 electronic components 5 〇 1 fixed or adhered to the support substrate 503. In this embodiment, the electronic component 501 may be an element for a buried structure, for example, a main circuit chip substrate (hereinafter referred to as an integrated circuit substrate 01) in the main # _ ^ L ^ Or a wafer plastic capacitor, resistor, inductor, etc. in the passive component; the support substrate can be 'hardened or a soft polymer substrate, or a metal substrate' such as one or more layers of printed electricity, then form a mask The cover is wide 506 on a part of the surface of the support substrate 503, as shown in the fifth B ~ Lutu. In the present embodiment, the mask layer is implemented by the polymer film layer 506. However, a film layer of another material or a general mask can also be applied. The formation of the polymer thin layer 5〇6 can be formed by printing, deposition, coating, hot pressing, β° or pasting. After forming the polymer film layer 506, a surface treatment 511 (for example, browning or black browning treatment) is applied, the principle of which is a roughened surface, in order to improve the support which is not covered by the polymer film layer 506. The adhesive layer on the surface of the base 503 is used to enhance the adhesion of the interface with the dielectric layer in the subsequent process to the step shown in the fifth C, and the polymer film layer 506 is removed. Since the surface covered by the meat knife thin layer 506 is not subjected to structuring or black browning, the interface adhesion property is still poor. Next, as shown in FIG. 5D, the first dielectric layer 5 is formed on the integrated circuit substrate 501 and the support substrate 503 by printing, & deposition, coating, thermocompression bonding, or other suitable technique. on. The material of the first dielectric layer 504 may be a material used in a general structure, such as a polymer material. Since a part of the surface of the support substrate 503 is not subjected to browning or black browning, the interface with the first dielectric layer 504 has poor adhesion characteristics, and naturally forms a separation space.
Cs、 10 1313915 區域之應力釋放層（stress releasing layer) 510A。如圖所示 的應力釋放層510A，其一端開口通常延伸至構裝的外側邊緣，並 與外界空氣接觸；此有助於防止内部的空氣膨脹，或者防止將濕 ' 氣儲存在構装内部。在第五E圖步驟中，先在第一介電層504上 - 需要作連線佈局的電極接點處開孔以暴露出電極5〇2,再以濺 鍍、無電極電鍍、沉積或電鍍等方式形成所需的連接導線5〇5而 與電極502電性連接。如第五f圖所示，以壓合、塗佈、沉積、 Φ 或其它適當的技術形成第二介電層507於第一介電層504之上。 於第五G圖所示的步驟中，先在第二介電層5〇7上需要作線路接 點處開孔以暴露出連接導線505,再形成導線及接點凸塊5〇8於 第二介電層5G7上而與連接導線5〇5電性連接q本實施例中， 應力釋放層51〇Α的一部份係垂直位於凸塊5〇8的下方（亦即， 這兩者有部分重疊），此對於應力的釋放會更有效果。至此，已大 致完成了構裝的製程。最後’將構裝體反置並固著於電路基板512 (例如電路板）上’如第五H圖所示。藉由上述本發明的構 裝製程及架構，所形成的應力釋放層51〇Α可以改善構裝體内部 •積I (build，layers)冑構中，因熱膨脹係數不匹配所產生的 -應力集中問題、或者因環境溫度變化所產生的魅曲現象；也可以 改善電路基板S12與構裝體之間因鮮规係數不匹配所造成凸塊 508之接點可靠度問題。在本實施例中，係以二介電層（5〇4、 507)作為例示，然'而，積層的層數並不限定於二層；另外，第一 1313915 介電層504與第二介電層507可以使用相同的材質（例如高分子 材料），也可以使用不同的材質。再者，積體電路基板501的位置 並不偈限於支撐基板503與第一介電層504之間，也可以置於其 , 它層級之間，或者多個積體電路基板501同時位於各個層級。 第六A圖之俯視圖顯示應力釋放層510A之形狀、配置，以及 和積體電路基板501之相對關係。應力釋放層510A係圍繞著積 φ 體電路基板501，但兩者沒有直接接觸。如前所述，應力釋放層 510A的外圍通常延伸至構裝體的外側邊緣，並與外界空氣接觸； 此有助於防止内部的空氣膨脹，或者防止將濕氣儲存在構裝内 部。第六B圖顯示另一種應力釋放層610之形狀。為了達成此種 應力釋放層610之形狀，所使用的高分子薄膜層506具有四個不 連續的長方形開孔；此種應力釋放層610所形成的空間區域是不 連續的，因此可以增加構裝體的接合強度。第六C圖顯示又一種 鲁應力釋放層620之形狀，其使用具有多個圓形開孔的高分子薄膜 層506，也同樣可以增加構裝體的強度。 第七圖顯示本發明之應力釋放電子構裝的第二實施例。由於 構裝製程與第一實施例類似，因此不予贅述，僅顯示出構裝的最 終剖面圖及描述與前實施例不同的地方；另外，相同的元件或層 級係以相同的符號表示。在本實施例中，除了在支撺基板503與 第一介電層504之間具有應力釋放層510A之外，於第一介電層 12 1313915 504與第二介電層507之間還具有另一應力釋放層510B。上層 應力釋放層510B的製程方法類似於下層應力釋放層510A的製 程；這兩個應力釋放層（510A、510B)的形狀不一定要相同， 且上下相對位置也不一定要對齊。第一實施例和第二實施例最大 的不同為，第一實施例係於支撐基板503與第一介電層504之間 形成應力釋放層510A，而第二實施例則是於介電層（504、507) 之間形成應力釋放層510B。第二實施例可以作一些變化，例如將 下層應力釋放層510A予以省略。 第八圖顯示本發明之應力釋放電子構裝的第三實施例。由於 構裝製程與前述各實施例類似，因此不予贅述，僅顯示出構裝的 最終剖面圖及描述與前實施例不同的地方；另外，相同的元件或 層級係以相同的符號表示。在本實施例中，除了在支撐基板503 與第一介電層504之間具有應力釋放層510A之外，於第一介電 層504與第二介電層507之間則具有一應力緩衝層810B。應力 緩衝層810B與應力釋放層510A的作法不同，其係形成高分子 材料層（例如具有低楊氏模數之高分子材料層）810B於第一介電 層504上面，但是並不加以除去，而是保留在介電層504表面， 作為應力緩衝層810B。應力緩衝層810B的形狀不一定要和應力 釋放層_.510A相同，且兩者的上下相對位置也不一定要對齊。第 二實施例和第三實施例最大的不同為，第二實施例使用的都是應 力釋放層（510 A、5 10B、，产笤三膏施例則是J定豆由的一個*力 13 (? 1313915 ' 釋放層以應力緩衝層810B來取代。當然，於第三實施例當中， 應力釋放層510A與應力緩衝層810B的上下位置可以互相對 調，亦即，應力釋放層位於上面（介電層504與介電層507之間）， 而應力緩衝層則位於下面（支撐基板503與第一介電層504之 . 間）。本實施例中的應力釋放層510A與應力緩衝層810B都是用 來改善構裝體内部應力集中問題、翹曲現象、或者改善電路基板 與構裝體之間的接點可靠度問題，因此，統稱為應力防護層 • ( shielding layer )。也就是說，本說明書及申請專利範圍中所稱 的應力防護層可以為應力釋放層、應力緩衝層、或其組合型態， 但不限於這兩種。 第九圖顯示本發明之應力釋放電子構裝的第四實施例。由於 構裝製程與前述實施例類似，因此不予贅述，僅顯示出構裝的最 終剖面圖及描述與前實施例不同的地方；另外，相同的元件或層 • 級係以相同的符號表示。此實施例為第三實施例（第八圖）的變 化型，於支撐基板503與第一介電層504之間具有應力缓衝層 810A，且於第一介電層504與第二介電層507之間也具有應力 . 緩衝層810B。 第十圖顯示本發明之應力釋放電子構裝的第五實施例。圖式 僅顯示出構裝的最終剖面圖及描述與前實施例不同的地方；另 外，相同的元件或層級係以相同的符號表示。在本實施例中，支 1313915 撐基板為一種軟硬接合電路板1120,係由硬式基板1122與軟式 基板1124所組成，其中硬式基板1122為中空框形，中空部分為 積體電路基板501的位置，其它部分則與軟式基板1124相連接； 軟式基板1124可以是一層或多層軟式印刷電路板。應力釋放層 510B位於第一介電層504與第二介電層507之間。本實施例可 以作一些變化，例如使用多層應力釋放層、應力緩衝層、或兩者 之組合。 » 第十一圖顯示本發明之應力釋放電子構裝的第六實施例。圖 式僅顯示出構裝的最終剖面圖及描述與前實施例不同的地方；另 外，相同的元件或層級係以相同的符號表示。在本實施例中，支 撐基板1203可以是軟式或硬式高分子基板，其具有一凹槽用以 容置積體電路基板501 ;應力釋放層510A位於支撐基板1203 與第一介電層504之間，而應力緩衝層810B則位於第一介電層 | 504與第二介電層507之間。當然，本實施例也可以僅使用一應 力緩衝層，或者使用一應力緩衝層、一應力釋放層之組合。 第十二圖顯示本發明之應力釋放電子構裝的第七實施例。圖 式僅顯示出構裝的最終剖面圖及描述與前實施例不同的地方；另 外，相同的元件或層級係以相同的符號表示。在本實施例中，支 撐基板503上面具有第一電子元件（例如積體電路基板）501A 與第二電子元件（例如另一積體電路基板）501B，第一電子元件 15 1313915 501A與第二電子元件501B分別連接於支撐基板503之上。應 力釋放層510A位於支撐基板503與第一介電層504之間，而另 一應力釋放層510B則位於第一介電層504與第二介電層507之 間。當然，本實施例也可以僅使用應力緩衝層，或者使用一應力 . 缓衝層、一應力釋放層之粗合。 上述之實施例僅係為說明本發明之技術思想及特點，其目的在使 熟悉此技藝之人士能了解本發明之内容並據以實施，當不能以之 _ 限定本發明之專利範圍，即凡其它未脫離本發明所揭示精神所完 成之各種等效改變或修飾都涵蓋在本發明所揭露的範圍内，均應 包含在下述之申請專利範圍内。 【圖式簡單說明】 第一圖顯示傳統使用保護蓋（protective cap)以增加構裝強度的 方法。 第二圖顯示傳統使用背對背（back to back)之對稱方式以降低晶 片之麵曲現象。 第三圖顯示傳統使用柔性層的内埋式構裝架構。 第四A圖、第四B圖顯示傳統在晶片背面增加切割裂縫使晶片具 ' 有可撓性。 ' 第五A圖至第五Η圖顯示本發明之應力釋放電子構裝架構及方法 的第一實施例，其具有一應力釋放層。 第六Α圖至第六C圖之俯視圖顯示各種應力釋放層之形狀、配 置，以及和積體電路基板之相對關係。 16 1313915 第七圖顯示本發明之應力釋放電子構裝的第二實施例，其具有二 應力釋放層。 第八圖顯示本發明之應力釋放電子構裝的第三實施例，其具有一 應力釋放層及一應力緩衝層。 第九圖顯示本發明之應力釋放電子構裝的第四實施例，其具有二 應力緩衝層。 第十圖顯示本發明之應力釋放電子構裝的第五實施例，其使用軟 B 硬接合電路板及具有一應力釋放層。 第十一圖顯示本發明之應力釋放電子構裝的第六實施例，其使用 凹槽式支撐基板及具有一應力釋放層、一應力緩衝層。 第十二圖顯示本發明之應力釋放電子構裝的第七實施例，其具有 多個積體電路基板且具有二應力釋放層。 【主要元件符號說明】 110 基板 120 晶片 130 保護蓋 210 基板 220 封膠材料 230 晶片 310 基板 320 晶片 330 晶片型電容 340 柔性層 350 金屬導線 360 高分子介電層 17 晶片卡 卡片主體 晶片 高分子保護層 積體電路基板（電子元件） 積體電路基板（電子元件） 積體電路基板（電子元件） 電極 支#基板 第一介電層 連接導線 高分子薄膜層（遮罩層） 第二介電層 凸塊 · 應力釋放層 應力釋放層 表®處理 電路基板 具長方形開孔的應力釋放層 具圓形開孔的應力釋放層 應力緩衝層 應力缓衝層 教硬接合電路板' 硬式基板 軟式基板 凹槽式支撐基板 18Cs, 10 1313915 region stress releasing layer 510A. As shown in the stress relief layer 510A, one end opening generally extends to the outer edge of the package and is in contact with the outside air; this helps prevent internal air from expanding or prevents the wet air from being stored inside the package. In the fifth step E, the first electrode layer 504 is first opened at the electrode contact where the wiring layout is required to expose the electrode 5〇2, and then sputtered, electroless plated, deposited or plated. The desired connecting wires 5〇5 are formed in an equal manner to be electrically connected to the electrodes 502. As shown in FIG. f, the second dielectric layer 507 is formed over the first dielectric layer 504 by lamination, coating, deposition, Φ, or other suitable technique. In the step shown in FIG. G, first, a hole is required to be formed on the second dielectric layer 5〇7 to expose the connecting wire 505, and then the wire and the contact bump 5〇8 are formed. The second dielectric layer 5G7 is electrically connected to the connecting wire 5〇5. In this embodiment, a portion of the stress relief layer 51〇Α is vertically below the bump 5〇8 (ie, both of them have Partially overlapping), this is more effective for stress release. At this point, the manufacturing process has been largely completed. Finally, the structure is reversed and fixed on the circuit substrate 512 (e.g., circuit board) as shown in the fifth H. With the above-described fabrication process and architecture of the present invention, the stress relief layer 51 can be formed to improve the internal stress and buildup of the structure, due to thermal expansion coefficient mismatch - stress concentration The problem, or the fascination phenomenon caused by the change of the ambient temperature, can also improve the reliability of the joint of the bump 508 caused by the mismatch of the fresh coefficient between the circuit board S12 and the package. In the present embodiment, the two dielectric layers (5〇4, 507) are exemplified, but the number of layers is not limited to the second layer; in addition, the first 1313915 dielectric layer 504 and the second dielectric layer The electric layer 507 can be made of the same material (for example, a polymer material) or a different material. Furthermore, the position of the integrated circuit substrate 501 is not limited to being between the support substrate 503 and the first dielectric layer 504, and may be placed between the layers, or between the plurality of integrated circuit substrates 501 at the same level. . The top view of the sixth graph shows the shape, configuration, and relative relationship of the stress relief layer 510A and the integrated circuit substrate 501. The stress relief layer 510A surrounds the φ body circuit substrate 501, but the two are not in direct contact. As previously mentioned, the periphery of the stress relief layer 510A generally extends to the outer edge of the body and is in contact with the outside air; this helps prevent internal air from expanding or prevents moisture from being stored inside the package. The sixth panel B shows the shape of another stress relief layer 610. In order to achieve the shape of the stress relief layer 610, the polymer film layer 506 used has four discontinuous rectangular openings; the space region formed by the stress relief layer 610 is discontinuous, so that the structure can be increased. The joint strength of the body. The sixth C-picture shows the shape of yet another type of stress relief layer 620 which uses a polymeric film layer 506 having a plurality of circular openings to also increase the strength of the structure. The seventh figure shows a second embodiment of the stress relieving electronic assembly of the present invention. Since the construction process is similar to that of the first embodiment, the detailed description of the structure and the description are different from the previous embodiment; the same elements or levels are denoted by the same reference numerals. In this embodiment, in addition to the stress relief layer 510A between the support substrate 503 and the first dielectric layer 504, there is another between the first dielectric layer 12 1313915 504 and the second dielectric layer 507. A stress relief layer 510B. The process of the upper stress relief layer 510B is similar to the process of the lower stress relief layer 510A; the shapes of the two stress relief layers (510A, 510B) are not necessarily the same, and the upper and lower relative positions are not necessarily aligned. The greatest difference between the first embodiment and the second embodiment is that the first embodiment forms a stress relief layer 510A between the support substrate 503 and the first dielectric layer 504, and the second embodiment is a dielectric layer ( A stress relief layer 510B is formed between 504, 507). The second embodiment can be modified, for example, by omitting the lower stress relief layer 510A. The eighth figure shows a third embodiment of the stress relieving electronic assembly of the present invention. Since the construction process is similar to the foregoing embodiments, the description will be omitted, and only the final cross-sectional view of the structure and the description will be different from the previous embodiment; in addition, the same elements or levels are denoted by the same reference numerals. In this embodiment, in addition to the stress relief layer 510A between the support substrate 503 and the first dielectric layer 504, there is a stress buffer layer between the first dielectric layer 504 and the second dielectric layer 507. 810B. The stress buffer layer 810B is different from the stress relief layer 510A in that a polymer material layer (for example, a polymer material layer having a low Young's modulus) 810B is formed on the first dielectric layer 504, but is not removed. Rather, it remains on the surface of dielectric layer 504 as stress buffer layer 810B. The shape of the stress buffer layer 810B does not have to be the same as that of the stress relief layer _.510A, and the relative positions of the upper and lower sides are not necessarily aligned. The biggest difference between the second embodiment and the third embodiment is that the second embodiment uses the stress relieving layer (510 A, 5 10B, and the glutinous three paste application is a * force 13 of J. (? 1313915 ' The release layer is replaced by the stress buffer layer 810B. Of course, in the third embodiment, the upper and lower positions of the stress relief layer 510A and the stress buffer layer 810B may be mutually adjusted, that is, the stress relief layer is located above (dielectric The layer 504 is between the dielectric layer 507 and the stress buffer layer is located below (between the support substrate 503 and the first dielectric layer 504.) The stress relief layer 510A and the stress buffer layer 810B in this embodiment are both It is used to improve the stress concentration problem inside the structure, warpage, or improve the reliability of the joint between the circuit board and the structure. Therefore, it is collectively referred to as a shielding layer. The stress protection layer referred to in the specification and the patent application scope may be a stress relief layer, a stress buffer layer, or a combination thereof, but is not limited to the two. The ninth diagram shows the fourth of the stress relief electronic assembly of the present invention. Since the construction process is similar to the foregoing embodiment, it will not be described again, and only the final sectional view of the structure and the description are different from the previous embodiment; in addition, the same components or layers are the same. The embodiment shows a variation of the third embodiment (eighth diagram), and has a stress buffer layer 810A between the support substrate 503 and the first dielectric layer 504, and the first dielectric layer 504 and the first dielectric layer 504 The second dielectric layer 507 also has a stress buffer layer 810B. The tenth figure shows a fifth embodiment of the stress relief electronic package of the present invention. The figure only shows the final cross-sectional view and description of the package and the previous embodiment. The same elements or levels are denoted by the same reference numerals. In the present embodiment, the support 1313915 support substrate is a soft and hard joint circuit board 1120 composed of a hard substrate 1122 and a flexible substrate 1124, wherein The rigid substrate 1122 has a hollow frame shape, the hollow portion is the position of the integrated circuit substrate 501, and the other portions are connected to the flexible substrate 1124; the flexible substrate 1124 may be one or more layers of flexible printed circuit boards. The force release layer 510B is located between the first dielectric layer 504 and the second dielectric layer 507. This embodiment may be modified, for example, using a multilayer stress relief layer, a stress buffer layer, or a combination of the two. The figure shows a sixth embodiment of the stress relief electronic assembly of the present invention. The drawings only show the final cross-sectional view of the configuration and the description is different from the previous embodiment; in addition, the same elements or levels are denoted by the same symbols In this embodiment, the support substrate 1203 may be a flexible or rigid polymer substrate having a recess for receiving the integrated circuit substrate 501; the stress relief layer 510A is located between the support substrate 1203 and the first dielectric layer 504. The stress buffer layer 810B is located between the first dielectric layer 504 and the second dielectric layer 507. Of course, this embodiment can also use only one stress buffer layer or a combination of a stress buffer layer and a stress relief layer. Figure 12 shows a seventh embodiment of the stress relieving electronic assembly of the present invention. The drawings show only the final cross-sectional views of the configuration and the description of the differences from the previous embodiment; the same elements or levels are denoted by the same reference numerals. In the present embodiment, the support substrate 503 has a first electronic component (for example, an integrated circuit substrate) 501A and a second electronic component (for example, another integrated circuit substrate) 501B, and the first electronic component 15 1313915 501A and the second electron. The elements 501B are respectively connected to the support substrate 503. The stress relief layer 510A is located between the support substrate 503 and the first dielectric layer 504, and the other stress relief layer 510B is located between the first dielectric layer 504 and the second dielectric layer 507. Of course, this embodiment can also use only the stress buffer layer, or use a stress, a buffer layer, and a stress relief layer. The above-mentioned embodiments are merely illustrative of the technical idea and the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the invention. All other equivalent changes or modifications that are made without departing from the spirit of the invention are intended to be included within the scope of the invention. [Simple description of the drawings] The first figure shows a conventional method of using a protective cap to increase the strength of the package. The second figure shows the traditional use of a back-to-back symmetry to reduce the curvature of the wafer. The third figure shows a buried architecture that traditionally uses a flexible layer. Figures 4A and 4B show that conventionally adding a cutting crack to the back side of the wafer makes the wafer 'flexible'. The fifth to fifth figures show a first embodiment of the stress relief electronic construction structure and method of the present invention having a stress relief layer. The top views of the sixth to sixth C charts show the shape, configuration, and relative relationship of the various stress relief layers and the integrated circuit substrate. 16 1313915 Figure 7 shows a second embodiment of the stress relief electronic assembly of the present invention having a two stress relief layer. The eighth figure shows a third embodiment of the stress relieving electronic assembly of the present invention having a stress relief layer and a stress buffer layer. The ninth diagram shows a fourth embodiment of the stress relief electronic package of the present invention having a two stress buffer layer. The tenth figure shows a fifth embodiment of the stress relief electronic package of the present invention which uses a soft B hard bonded circuit board and has a stress relief layer. The eleventh diagram shows a sixth embodiment of the stress relieving electronic package of the present invention which uses a grooved support substrate and has a stress relief layer and a stress buffer layer. Fig. 12 shows a seventh embodiment of the stress relieving electronic package of the present invention having a plurality of integrated circuit substrates and having two stress relief layers. [Main component symbol description] 110 substrate 120 wafer 130 protective cover 210 substrate 220 sealing material 230 wafer 310 substrate 320 wafer 330 wafer type capacitor 340 flexible layer 350 metal wire 360 polymer dielectric layer 17 chip card card body wafer polymer protection Laminated circuit board (electronic component) Integrated circuit board (electronic component) Integrated circuit board (electronic component) Electrode branch #Substrate first dielectric layer connection wire polymer film layer (mask layer) Second dielectric layer Bumps · Stress relief layer stress relief layer table ® processing circuit substrate stress relief layer with rectangular opening stress relief layer with circular opening stress buffer layer stress buffer layer teaching hard bonding circuit board 'hard substrate flexible substrate groove Support substrate 18