CN109755187B - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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CN109755187B
CN109755187B CN201810011009.0A CN201810011009A CN109755187B CN 109755187 B CN109755187 B CN 109755187B CN 201810011009 A CN201810011009 A CN 201810011009A CN 109755187 B CN109755187 B CN 109755187B
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trace
substrate
underfill
barrier element
semiconductor package
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CN109755187A (zh
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叶昶麟
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

在一或多个实施例中，一种半导体封装装置包含衬底、迹线、结构、屏障元件和底部填充胶。所述衬底具有包含由所述迹线包围的填充区的第一表面。所述结构安置于所述填充区上且电连接到所述衬底。所述屏障元件安置于所述迹线上。所述底部填充胶安置于所述填充区上。

Description

半导体封装装置及其制造方法
技术领域
本发明大体上涉及一种半导体封装装置及其制造方法，且涉及一种包含堆叠结构的半导体封装装置及其制造方法。
背景技术
在堆叠式半导体封装装置(其可包含上部衬底、下部衬底和插入件)中，底部填充胶可施加在电接触件周围用于保护。然而，归因于对应于底部填充胶的衬底的亲水性(例如衬底或衬底上的物质可在底部填充胶上施加吸引力)，底部填充胶可能渗出或溢出而覆盖其它电接触件，这可能对半导体封装装置的电特性产生影响。此外，溢出的底部填充胶可能占据应该容纳衬底上的其它组件的空间，且因此可提供额外空间，这可能增加半导体封装装置的大小。
发明内容
在一或多个实施例中，一种半导体封装装置包含衬底、迹线、结构、屏障元件和底部填充胶。衬底具有包含由迹线包围的填充区的第一表面。所述结构安置于填充区上且电连接到衬底。屏障元件安置于迹线上。底部填充胶安置于填充区上。
在一或多个实施例中，一种半导体封装装置包含衬底、迹线、结构、屏障元件和底部填充胶。衬底具有第一表面，其包含由迹线包围的填充区和与填充区分离的非填充区。所述结构安置于衬底上且电连接到衬底。屏障元件安置于迹线上。底部填充胶安置于填充区上。屏障元件的至少一部分突出超出结构的朝向衬底的第一表面的表面。
在一或多个实施例中，一种制造半导体封装装置的方法包含：(a)提供具有第一表面的衬底，所述第一表面包含填充区，所述衬底包含安置于第一表面上邻近于填充区的迹线，和安置于填充区上的垫片；(b)在共同操作中在迹线和垫片上沉积焊接材料以在迹线上形成屏障元件且在垫片上形成电接触件；(c)将结构安置在填充区上方，所述结构电连接到衬底；以及(d)将底部填充胶施加到填充区。
附图说明
图1A说明根据本发明的一些实施例的半导体封装装置的横截面图。
图1B说明根据本发明的一些实施例的半导体封装装置的俯视图。
图1C说明根据本发明的一些实施例的半导体封装装置的俯视图。
图1D说明根据本发明的一些实施例的迹线的透视图。
图1E说明根据本发明的一些实施例的迹线的透视图。
图1F说明根据本发明的一些实施例的半导体封装装置的俯视图。
图2A说明根据本发明的一些实施例的半导体封装装置的横截面图。
图2B说明根据本发明的一些实施例图2A中展示的半导体封装装置的一部分的放大视图。
图2C说明根据本发明的一些实施例的半导体封装装置的仰视图。
图2D说明根据本发明的一些实施例的半导体封装装置的仰视图。
图2E说明根据本发明的一些实施例的半导体封装装置的仰视图。
图2F说明根据本发明的一些实施例的半导体封装装置的仰视图。
图2G说明根据本发明的一些实施例的迹线的俯视图。
图2H说明根据本发明的一些实施例的迹线的俯视图。
图3A说明对比的半导体封装装置。
图3B说明对比的半导体封装装置。
图3C说明对比的半导体封装装置。
图4A、图4B、图4C、图4D、图4E、图4E'、图4F和图5说明根据本发明的一些实施例制造半导体封装的方法。
贯穿图式和详细描述使用共同参考标号指示相同或类似元件。根据以下结合附图作出的详细描述将容易理解本发明。
具体实施方式
图1A说明根据本发明的一些实施例的半导体封装装置1的横截面图。半导体封装装置1包含衬底10、电子组件11、屏障元件12和底部填充胶13。
衬底10可包含(例如)印刷电路板，例如，纸基铜箔层压物、复合铜箔层压物或聚合物浸渍的玻璃纤维基铜箔层压物。衬底10可包含互连结构，例如再分布层(RDL)。衬底 10可具有表面101和与第一表面101相对的表面102。在一些实施例中，衬底10的表面101被称作顶部表面或第一表面，且衬底10的表面102被称作底部表面或第二表面。
电子组件11安置于衬底10的顶部表面101上且电连接到衬底10。电子组件11可包含芯片或裸片，其中包含半导体衬底、一或多个集成电路装置和/或一或多个上覆互连结构。集成电路装置可包含例如晶体管等有源装置，和/或例如电阻器、电容器、电感器等无源装置，或其组合。在一些实施例中，电子组件11通过倒装芯片技术经由一或多个电接触件11c(例如，焊球)电连接到衬底10。
底部填充胶13可安置于衬底10的顶部表面101上以覆盖电子组件11和电接触件11c的有源表面。在一些实施例中，底部填充胶13包含环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底部填充胶13可以是毛细管底部填充胶(CUF) 或模制底部填充胶(MUF)，这取决于设计规格。衬底10的顶部表面101的被底部填充胶 13覆盖的部分可在本文中被称作填充区。
屏障元件12安置于迹线10t上，迹线10t安置于衬底10的顶部表面101上或邻近于衬底10的顶部表面101。在一些实施例中，迹线10t包围底部填充胶13或填充区。在一些实施例中，屏障元件12可以是或可包含焊料或可导电的其它合适的材料。在一些实施例中，由屏障元件12的材料和底部填充胶13的材料界定的接触角等于或大于约 25度(例如等于或大于约27度、等于或大于约29度、等于或大于约31度，或更大)。在一些实施方案中，屏障元件12可省略。然而，归因于对应于底部填充胶13的衬底10 的亲水性，底部填充胶13可能渗出而覆盖其它电接触件或占据应该容纳衬底10上的其它组件的空间。根据本发明的图1A中展示的实施例，通过形成屏障元件12(例如，焊坝) 以包围填充区或底部填充胶13，可避免渗出问题。此外，屏障元件12可在形成电接触件11c时形成。换句话说，屏障元件12和电接触件11c可在使用相同材料的共同过程(例如，包含印刷焊料的过程)中形成，且因此可省略额外过程，这可减少制造成本。在其它实施例中，电子组件11可经由包含铜、铜合金或另一金属的支柱电连接到衬底10，且屏障元件12可在形成其它元件(例如无源元件或有源元件)的电接触件时形成。
图1B和图1C说明根据本发明的一些实施例图1A中展示的半导体封装装置1的俯视图。如图1B和图1C中所示，迹线10t包含第一部分10t1和第二部分10t2。在用于形成底部填充胶13的过程期间，底部填充胶13注射或以其它方式施加在衬底10的顶部表面101上的预定位置(例如，注射区)处，且因此注射区处底部填充胶13的量超过另一区处的量。为避免从底部填充胶13渗出，注射区处迹线10t的宽度可设定成大于另一区处迹线10t的宽度。如图1B中所示，举例来说，注射区可位于迹线10t的第一部分 10t1处或邻近于迹线10t的第一部分10t1，且迹线10t的第一部分10t1的宽度大于迹线 10t的第二部分10t2的宽度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，迹线10t的第一部分10t1上的屏障元件12的高度大于迹线10t的第二部分10t2上的屏障元件12的高度(例如屏障元件12具有非均一高度)，例如大至少约1.1 倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，邻近于迹线10t的第一部分 10t1的底部填充胶13的高度大于邻近于迹线10t的第二部分10t2的底部填充胶13的高度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，迹线 10t大体上为环形。
根据本发明的一些实施例，图1D说明回焊工艺之前迹线10t的透视图，且图1E说明回焊工艺之后迹线10t和屏障元件12的透视图。如图1D中所示，迹线10t的第一部分10t1的宽度大于迹线10t的第二部分10t2的宽度，且迹线10t的第一部分10t1上的屏障元件12的高度与迹线10t的第二部分10t2上的屏障元件12的高度大体上相同。在回焊工艺之后，如图1E所示，迹线10t的第一部分10t1上的屏障元件12的高度大于迹线10t的第二部分10t2上的屏障元件12的高度。
图1F说明根据本发明的一些实施例图1A中展示的半导体封装装置1的俯视图。一般来说，通常在电子组件11的隅角处发生应力，而电子组件11的每一边缘的中间部分遭受相对低的应力。因此，为减少制造成本，底部填充胶13和在其上安置屏障元件12 的迹线10t可如图1F所示选择性地形成于电子组件11的隅角处，且可省略在电子组件 11的边缘的中间部分处或附近形成底部填充胶13和迹线10t(例如各自包含底部填充胶 13和迹线10t的结构可分别安置在电子组件11的隅角处且可隔开)。
图2A说明根据本发明的一些实施例的半导体封装装置2的横截面图。半导体封装装置2包含衬底20、电子组件21a、电子组件21b、封装主体22、插入件23、底部填充胶24和屏障元件25。
衬底20可包含(例如)印刷电路板，例如，纸基铜箔层压物、复合铜箔层压物或聚合物浸渍的玻璃纤维基铜箔层压物。衬底20可包含互连结构，例如RDL。衬底20可具有表面201和与第一表面201相对的表面202。衬底20的表面201可在本文中被称作顶部表面或第一表面，且衬底20的表面202可在本文中被称作底部表面或第二表面。
电组件21a、22b安置于衬底20的顶部表面201上。电组件21a可包含有源组件，例如集成电路(IC)芯片或裸片。电组件21b可包含无源电组件，例如，电容器、电阻器或电感器。每一电组件21a、21b可电连接到另一电组件21a、21b中的一或多者或电连接到衬底20(例如，电连接到衬底20的RDL)，且电连接可借助于倒装芯片或导线接合技术来实现。
封装主体22安置于衬底20的顶部表面201上且覆盖电子组件21a和21b。在一些实施例中，封装主体22包含例如有机材料(例如，模制化合物、双马来酰亚胺三嗪(BT)、聚酰亚胺(PI)、聚苯并噁唑(PBO)、阻焊剂、味之素堆积膜(ABF)、聚丙烯(PP)或环氧树脂基材料)、无机材料(例如，硅、玻璃、陶瓷或石英)、液体-膜材料和/或干燥-膜材料，或其组合。
插入件23安置于衬底20的底部表面202上且经由一或多个电接触件20c(例如，焊球)电连接到衬底20。插入件23可包含呈通孔23v的形式的至少一个互连，通孔23v穿透插入件23用于电连接(例如到一或多个外部装置)。衬底20的底部表面202上的暴露的迹线(例如迹线20t)和/或导电垫可经由电接触件20c电连接到插入件23的通孔23v。插入件23可包含(例如)印刷电路板，例如纸质铜箔层压物、复合铜箔层压物，或聚合物浸渍的玻璃纤维基铜箔层压物。插入件23和电接触件20c可布置在衬底20的底部表面 202的外围处或附近。在一些实施例中，插入件23界定腔23c，其暴露衬底的底部表面 202的一部分、底部填充胶24的一部分和屏障元件25。在一些实施例中，屏障元件25 可伸出超出插入件23的表面。
底部填充胶24可安置于衬底20的底部表面202和插入件23之间以覆盖电接触件20c。在一些实施例中，底部填充胶24包含环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底部填充胶23可以是CUF或MUF，这取决于设计规格。衬底20的底部表面202的被底部填充胶24覆盖的部分可在本文中被称作填充区。
屏障元件25如图2B所示安置于衬底20的底部表面202上的迹线20t上，图2B说明根据本发明的一些实施例图2A中展示的半导体封装装置2的一部分的放大视图。在一些实施例中，屏障元件25可以是或包含焊料或可导电的其它合适的材料。在一些实施例中，由屏障元件25的材料和底部填充胶24的材料界定的接触角等于或大于约25 度(例如等于或大于约27度、等于或大于约29度、等于或大于约31度，或更大)。在一些实施例中，屏障元件25可省略。然而，归因于对应于底部填充胶24的衬底20的亲水性，底部填充胶24可能渗出而覆盖其它电接触件或占据应该容纳衬底20上的其它组件的空间。根据本发明的图2A中展示的实施例，通过形成屏障元件25(例如，焊坝)以阻挡底部填充胶24，可防止底部填充胶24流动到衬底20的底部表面202的被插入件 23的腔23c暴露的部分。因此，插入件23的腔23c可具有足够空间来容纳额外电子组件。
图2C说明根据本发明的一些实施例图2A中展示的半导体封装装置2的仰视图。如图2C中所示，在其上安置屏障元件25的迹线20t安置于衬底20的底部表面202上以防止底部填充胶24流动到衬底20的底部表面202的被插入件23的腔23c暴露的部分。如图2C所示，迹线20t包围衬底20的底部表面202的从插入件23暴露的部分。举例来说，迹线20t安置于衬底20的底部表面202的暴露部分的四个边缘上。在一些实施例中，迹线20t可选择性地安置于衬底20的底部表面202的暴露部分的一个、两个或三个边缘上。举例来说，迹线20t可安置于衬底20的底部表面202的两个相对边缘上。举例来说，迹线20t可安置于衬底20的底部表面202的两个邻近边缘上(例如，呈L形布置)。举例来说，迹线20t可安置于衬底20的底部表面202的三个邻近边缘上(例如，呈U形布置)。
图2D和图2E说明根据本发明的一些实施例图2A中展示的半导体封装装置2的仰视图。图2D或2E中展示的结构类似于图2C中展示的结构，只是在图2C中，迹线20t 的宽度大体上均一，而在图2D或2E中，迹线20t的宽度非均一。
如图2D和图2E中所示，迹线20t包含第一部分20t1和第二部分20t2。在用于形成底部填充胶24的过程期间，底部填充胶24注射在衬底20的底部表面202上的预定位置(例如，注射区)处，且注射区处底部填充胶24的量超过其它区处的量。为避免渗出底部填充胶24，注射区处、附近或邻近于注射区的迹线20t的宽度可设定成大于另一区处迹线20t的宽度。举例来说，如图2D或2E所示，注射区可位于迹线20t的第一部分 20t1处或邻近于迹线20t的第一部分20t1，且迹线20t的第一部分20t1的宽度大于迹线 20t的第二部分20t2的宽度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，迹线20t的第一部分20t1上的屏障元件25的高度大于迹线20t的第二部分20t2上的屏障元件25的高度，例如大至少约1.1倍、大至少约1.2倍，或大至少约 1.3倍。在一些实施例中，邻近于迹线20t的第一部分20t1的底部填充胶24的高度大于邻近于迹线20t的第二部分20t2的底部填充胶24的高度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，迹线20t大体上为环形。在一些实施例中，迹线20t类似于图1D和图1E中展示的迹线10t。
图2F说明根据本发明的一些实施例图2A中展示的半导体封装装置2的仰视图。一般来说，通常在衬底20的隅角处发生应力，而衬底20的每一边缘的中间部分遭受相对低的应力。因此，为减少制造成本，底部填充胶24和在其上安置屏障元件的迹线20t 可如图2F所示选择性地形成于衬底20的隅角处，且可省略在衬底20的边缘的中间部分处或附近形成底部填充胶24和迹线20t(例如各自包含底部填充胶23和迹线20t的至少一部分的结构可分别安置在衬底20的隅角处且可隔开)。如图2F中所示，迹线20t 包含从插入件23暴露的第一部分20t1以及安置于衬底20和插入件23之间的第二部分 20t2。在一些实施例中，迹线20t的第二部分20t2的至少一部分从插入件23暴露。在一些实施例中，迹线20t的第一部分20t1的宽度大于迹线20t的第二部分20t2的宽度，例如大至少约1.1倍、大至少约1.2倍、或大至少约1.3倍。在一些实施例中，迹线20t的第一部分20t1上的屏障元件25的高度大于迹线20t的第二部分20t2上的屏障元件25 的高度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3倍。在一些实施例中，邻近于迹线20t的第一部分20t1的底部填充胶24的高度大于邻近于迹线20t的第二部分 20t2的底部填充胶24的高度，例如大至少约1.1倍、大至少约1.2倍，或大至少约1.3 倍。
在一些实施例中，如图2G和图2H所示，迹线20t可包含多个区段，且每一区段与另一区段分离。区段的数目可取决于设计规格来确定。
图3A说明对比的半导体封装装置。图3A中展示的结构类似于图2B中展示的结构，只是在图3A中，图2B中展示的电接触件20c和底部填充胶24被各向异性导电膜 (ACF)34代替。ACF 34施加或安置于衬底20和插入件23之间以在其间提供电连接。不同于底部填充胶24，ACF 34可避免渗出问题。然而，ACF 34具有与焊球(例如，电接触件20c)相比相对高的电阻和成本。此外，通过施加热和压力形成ACF 34，如果压力或热未得到良好控制可能会损坏半导体封装装置。
图3B说明对比的半导体封装装置。图3B中展示的结构类似于图2B中展示的结构，只是在图3B中，省略屏障元件25。如图3B中所示，为防止渗出问题，凹口20r形成于衬底20的底部表面202上以容纳溢出的底部填充胶24。然而，凹口20r的深度和宽度可较大以容纳溢出的底部填充胶24，这可能妨碍半导体封装装置的小型化。此外，底部填充胶24具有相对于衬底20或衬底20上的阻焊剂的高亲水性(以及例如，小于约25 度的接触角)，且因此使用凹口20r避免渗出问题并不始终有效。
图3C说明对比的半导体封装装置。图3C中展示的结构类似于图3B中展示的结构，只是在图3C中，衬底20的底部表面202进一步包含突出部分20p以阻挡溢出的底部填充胶24。与图3B中展示的结构相比，图3C中展示的结构可更有效地避免渗出问题。然而，可能具有挑战性的是实施充分高的衬底20的突出部分20p或衬底20的阻焊剂。
根据图2B中展示的实施例，屏障元件25可包含焊料。因为底部填充胶24相对于焊料的亲水性相对低(且接触角等于或大于约25度(例如等于或大于约27度、等于或大于约29度、等于或大于约31度或更大))，所以底部填充胶24不容易溢出超出屏障元件 25。此外，屏障元件25可在形成电接触件20c时形成。换句话说，屏障元件25和电接触件20c可在共同过程中(例如，通过印刷焊料)形成，且因此可省略额外过程，这可减少制造成本。
根据本发明的一些实施例，图4A、图4B、图4C、图4D、图4E和图4F是各个制造阶段处的半导体结构的横截面图，且图4E'是此半导体结构的仰视图。各图已经简化以较好地突显本发明的各方面。
参看图4A，提供包含多个衬底40的衬底条带，且多个衬底40的提供允许同时制造多个半导体封装装置。衬底40可包含(例如)印刷电路板，例如，纸基铜箔层压物、复合铜箔层压物或聚合物浸渍的玻璃纤维基铜箔层压物。
电子组件41a和电子组件41b形成或安置于衬底40的顶部表面401上，且通过例如倒装芯片、导线接合或表面安装件技术(SMT)而电连接到衬底40。电子组件41a、41b 中的每一者包含多个半导体装置，例如(但不限于)晶体管、电容器和电阻器，其由裸片互连结构一起互连成功能电路以借此形成集成电路。半导体裸片的装置侧包含有源部分，其包含集成电路和互连。
迹线10和一或多个垫片46可安置于衬底40的底部表面402上。迹线10可安置成邻近于底部表面402的填充区，且所述一或多个垫片46可安置于底部表面402的填充区中。
参看图4B，封装主体42形成于衬底40的顶部表面401上且囊封衬底40的顶部表面401的一部分以及电子组件41a和41b。在一些实施例中，封装主体42包含例如有机材料(例如，模制化合物、BT、PI、PBO、阻焊剂、ABF、PP或环氧树脂基材料)、无机材料(例如，硅、玻璃、陶瓷或石英)、液体-膜材料和/或干燥-膜材料，或其组合。封装主体42可以通过模制技术(例如，转移模制或压缩模制)形成。
参看图4C，图4B中展示的结构翻转，且焊膏印刷在预定位置处以形成焊球40c(例如在所述一或多个垫片46上)和屏障元件45(例如在迹线10上)。在一些实施例中，取决于设计规格，屏障元件45和在其上安置屏障元件45的迹线10与图2C到图2H中展示的那些中的任一者相同或类似。
参看图4D，插入件43安装在衬底40的底部表面402上且经由焊球40c电连接到衬底40。插入件43可包含穿透插入件43用于电连接的至少一个通孔43v。插入件43 可包含(例如)印刷电路板，例如纸质铜箔层压物、复合铜箔层压物，或聚合物浸渍的玻璃纤维基铜箔层压物。插入件43和电接触件40c可布置在衬底40的底部表面402的外围处或附近。在一些实施例中，插入件43界定腔43c，其暴露衬底的底部表面402的一部分和屏障元件45。随后实行回焊工艺。
参看图4E，底部填充胶44可形成或安置于衬底40的底部表面402和插入件43之间的间隙中以覆盖电接触件40c。在一些实施例中，底部填充胶44包含环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、包含分散在其中的硅酮的材料，或其组合。在一些实施例中，底部填充胶43可以是CUF或 MUF，这取决于设计规格。
在一些实施例中，底部填充胶44注射或施加在衬底40的底部表面402上的预定位置(例如，注射区)处，且因此注射区处的底部填充胶44的量超过另一区处的量。为避免渗出底部填充胶44，注射区上的屏障元件45的高度大于另一区上的屏障元件45的高度。在一些实施例中，邻近于注射部分的底部填充胶44的高度高于邻近于另一部分的底部填充胶44的高度。
图4E'说明根据本发明的一些实施例用于形成如图4E所示的底部填充胶44的操作的仰视图。如图4E'中所示，底部填充胶44注射或施加在衬底40的底部表面402上的预定位置(例如，注射区)处。衬底40可界定一或多个切割通道49c。
参看图4F，可执行单分以分离出个别半导体封装装置4。也就是说，穿过插入件43、包含衬底40的衬底条带和封装主体42执行单分。在一些实施例中，可沿着图4E'中展示的切割通道49c执行单分。可(例如)通过使用划片机、激光或其它适当的切割技术执行单分。在一些实施例中，半导体封装装置4与图2A中展示的半导体封装装置2相同。
图5说明根据本发明的一些实施例用于形成如图2F所示的底部填充胶24的操作的仰视图。如图5中所示，底部填充胶54注射或施加在衬底的底部表面上的预定位置(例如，注射区)处。随后，可沿着切割通道59c执行单分。
如本文中所使用，术语“近似”、“大体上”、“大体”和“约”用于描述和解释小的变化。当与事件或情形结合使用时，所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，所述术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同。举例来说，“大体上”平行可指代相对于0°的小于或等于±10°的角变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“大体上”垂直可指相对于90°的小于或等于±10°的角变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么可认为这两个表面是共面的或大体上共面。
如本文中所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”是指传输电流的能力。导电材料通常指示展现对于电流流动的极少或零对抗的那些材料。电导率的一个量度为西门子/米(S/m)。通常，导电材料是电导率大于近似104S/m(例如，至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外规定，否则材料的电导率在室温下测量。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含复数指示物。在一些实施例的描述中，提供于另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个介入组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述和说明本发明，但这些描述和说明并不限制本发明。所述说明可能未必按比例绘制。归因于制造工艺等的变化，本发明中的艺术再现与实际设备之间可存在区别。应将本说明书及图式视为说明性的而非限制性的。可进行修改，以使特定情形、材料、物质组成、方法或工艺适于本发明的目标、精神和范围。所有此类修改是既定在所附权利要求书的范围内。因此，除非本文中特别指示，否则操作的次序及分组并非本发明的限制。

Claims (13)

1.一种半导体封装装置，其包括：
衬底，其具有包括填充区的第一表面；
迹线，其安置成邻近于所述衬底的所述第一表面且包围所述衬底的所述第一表面的所述填充区；
结构，其安置于所述填充区上且电连接到所述衬底，其中所述结构包括第一侧边、与所述第一侧边相邻接的第二侧边和由所述第一侧边及所述第二侧边所构成的第一隅角，其中所述迹线至少从所述第一侧边延伸到所述第二侧边；
屏障元件，其安置于所述迹线上；以及
底部填充胶，其安置于所述填充区上；
其中所述迹线包括位于所述第一隅角处的第一部分和与所述第一部分相邻接的第二部分，且所述第一部分的宽度比所述第二部分的宽度大至少1.1倍；以及
其中所述第一部分上的所述屏障元件的高度比所述第二部分上的所述屏障元件的高度大至少1.1倍。
2.根据权利要求1所述的半导体封装装置，其中邻近于所述迹线的所述第一部分的所述底部填充胶的高度比邻近于所述迹线的所述第二部分的所述底部填充胶的高度大至少1.1倍。
3.根据权利要求1所述的半导体封装装置，其中从顶视图观看时，所述迹线的所述第一部分向所述迹线的所述第二部分渐缩。
4.根据权利要求3所述的半导体封装装置，其中所述迹线还包括第三部分，所述第一部分连接所述第二部分与所述第三部分，且从顶视图观看时，所述迹线的所述第一部分向所述迹线的所述第三部分渐缩。
5.根据权利要求1所述的半导体封装装置，其中所述迹线的所述第二部分沿着所述结构的所述第一侧边延伸且所述第二部分的所述宽度不变。
6.根据权利要求1所述的半导体封装装置，其中所述迹线包含多个彼此分离的区段，所述填充区包含多个彼此分离的子填充区，且其中每一区段在所述结构的一隅角处包围对应的所述子填充区。
7.一种半导体封装装置，其包括：
衬底，其具有第一表面、从所述第一表面曝露的垫片和从所述第一表面曝露的迹线；
电接触件，其安置于所述垫片上；
屏障元件，其安置于所述迹线上，其中所述屏障元件与所述电接触件为焊接材料；
插入件，其透过所述电接触件安置于所述第一表面上，其中所述插入件包围所述屏障元件；
以及底部填充胶，其安置于所述衬底与所述插入件之间且连接所述屏障元件，其中所述底部填充胶包围所述屏障元件；
其中所述底部填充胶曝露所述第一表面的部分，所述插入件与所述第一表面的部分界定腔，所述腔经组态以容纳电组件，且其中从顶视图观看时，所述迹线的宽度从所述腔的隅角处向所述腔的第一侧边渐缩。
8.根据权利要求7所述的半导体封装装置，其中所述底部填充胶接触所述插入件的侧表面。
9.根据权利要求7所述的半导体封装装置，其中从顶视图观看时，所述迹线的所述宽度从所述腔的所述隅角处向所述腔的第二侧边渐缩。
10.根据权利要求7所述的半导体封装装置，其中所述插入件的侧表面及所述底部填充胶的侧表面共平面，且所述插入件的所述侧表面与所述衬底的侧表面不共平面。
11.根据权利要求7所述的半导体封装装置，其中所述屏障元件突出超出所述插入件的朝向所述衬底的所述第一表面的第二表面。
12.一种半导体封装装置，其包括：
衬底，其具有第一表面、从所述第一表面曝露的垫片和从所述第一表面曝露的迹线；
电接触件，其安置于所述垫片上；
屏障元件，其安置于所述迹线上，其中所述屏障元件与所述电接触件为焊接材料；
插入件，其透过所述电接触件安置于所述第一表面上，其中所述插入件包围所述屏障元件；
以及底部填充胶，其安置于所述衬底与所述插入件之间且连接所述屏障元件，其中所述底部填充胶包围所述屏障元件；
其中所述屏障元件突出超出所述插入件的朝向所述衬底的所述第一表面的第二表面；
其中所述底部填充胶曝露所述第一表面的部分，所述插入件与所述第一表面的部分界定腔，所述腔经组态以容纳电组件，其中所述腔包括第一隅角、第二隅角和连接所述第一隅角与所述第二隅角的侧边，且所述迹线包括位于所述第一隅角处的第一部分、位于所述第二隅角处的第二部分和沿着所述侧边的第三部分，其中所述迹线的所述第一部分的宽度大于所述迹线的所述第三部分的宽度，且其中所述第一部分上的所述屏障元件突出超出所述插入件的朝向所述衬底的所述第一表面的所述第二表面。
13.根据权利要求12所述的半导体封装装置，其中所述迹线的所述第二部分的宽度大于所述迹线的所述第三部分的所述宽度，且其中所述第二部分上的所述屏障元件突出超出所述插入件的朝向所述衬底的所述第一表面的所述第二表面。
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