TWI614814B - 基於薄膜之扇出及多晶粒封裝平台 - Google Patents
基於薄膜之扇出及多晶粒封裝平台 Download PDFInfo
- Publication number
- TWI614814B TWI614814B TW105106863A TW105106863A TWI614814B TW I614814 B TWI614814 B TW I614814B TW 105106863 A TW105106863 A TW 105106863A TW 105106863 A TW105106863 A TW 105106863A TW I614814 B TWI614814 B TW I614814B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- polymer film
- film
- conductive pillar
- tapered
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 86
- 229920006254 polymer film Polymers 0.000 claims abstract description 79
- 239000010949 copper Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052802 copper Inorganic materials 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims abstract description 13
- 239000005022 packaging material Substances 0.000 claims abstract description 10
- 229920000642 polymer Polymers 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims description 25
- 229920006264 polyurethane film Polymers 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 10
- 239000004593 Epoxy Substances 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 238000000608 laser ablation Methods 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000010329 laser etching Methods 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 150000002736 metal compounds Chemical class 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 239000012778 molding material Substances 0.000 claims description 2
- 150000001409 amidines Chemical class 0.000 claims 1
- 239000004814 polyurethane Substances 0.000 claims 1
- 229920002635 polyurethane Polymers 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 20
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- UEJJHQNACJXSKW-UHFFFAOYSA-N 2-(2,6-dioxopiperidin-3-yl)-1H-isoindole-1,3(2H)-dione Chemical compound O=C1C2=CC=CC=C2C(=O)N1C1CCC(=O)NC1=O UEJJHQNACJXSKW-UHFFFAOYSA-N 0.000 description 1
- BVRDQVRQVGRNHG-UHFFFAOYSA-N 2-morpholin-4-ylpyrimido[2,1-a]isoquinolin-4-one Chemical compound N1=C2C3=CC=CC=C3C=CN2C(=O)C=C1N1CCOCC1 BVRDQVRQVGRNHG-UHFFFAOYSA-N 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本發明涉及基於薄膜的扇出及多晶粒封裝平台,其所揭示乃基於薄膜的扇出晶圓級封裝及其製造方法。具體實施例包括一種方法,該方法包括在聚合物膜的第一表面中形成錐形通孔;在半導體裝置的第一表面上形成導電柱;將導電銅柱的可焊接表面接合至該聚合物膜的第二表面上的金屬化物;以底部填充材料包覆該導電柱將該半導體裝置接合至該聚合物膜的該第一表面;以及在該半導體裝置及聚合物膜上方沉積封裝材料。
Description
本發明是關於後晶圓製作。本揭露尤其適用於基於薄膜的扇出(fan out)晶圓級封裝及其製造方法。
半導體遠後端裝配及封裝產業需要低成本封裝解決方案,使移動與物聯網(internet-of-things,IoT)應用及其它應用的互連密度更高且形成因子更小。一種現有解決方案是扇出晶圓級芯片尺度封裝(fan out wafer level chip scale packaging,FOWLCSP)。此解決方案雖已在有限基礎上使用,仍有成本高且可擴展性有限的問題。此解決方案旨在為求降低成本而從330毫米(mm)直徑左右的基板移向500x500mm的正方形基板。然而,此解決方案在處理大型薄板方面和跨板材的運行模式也存在固有缺點。這兩項缺點促使製造工具的成本更高,而且與此解決方案相關聯的潛在節省效果也極低。
第1A圖中繪示層疊封裝(package on package,PoP)組態中習知的FOWLCSP的一個例子。PoP晶圓級扇出封裝包括堆疊封裝101及晶圓級扇出封裝103。
諸如存儲器或芯片尺寸封裝的堆疊封裝101可耦合至晶圓級扇出封裝103的導電圖案105。堆疊封裝101包括第一與第二半導體晶粒107、109、基板111、封裝劑113及焊球115。焊球115耦合至導電圖案105。晶圓級扇出封裝103更包括導電通孔117、半導體晶粒119及焊球121。芯片供應商及移動產品製造商想要藉由增加矽芯片彼此間的矽容量及互連件來提升產品的功能,同時仍要維持低成本,生產具有小占位面積(footprint)封裝的薄型產品。
第1B圖是習知扇入晶圓級封裝的一個例子,其具有矽晶粒121、凸塊或背緣連接物129及金屬導體127。第1C圖是晶圓級扇出封裝的一個例子,其包括矽晶粒121,該矽晶粒一般乃封裝於基於環氧樹脂的熱固性材料123中。第1B圖的習知晶圓級封裝中,由此封裝至諸如系統級或模組級的下一級互連件的連接物全都必須內含於矽晶粒121本身的表面的區域中,不同的是,第1C圖的習知扇出晶圓級芯片尺度封裝將封裝材料123當作延展物使用,可在該延展物上圖案化介電材料125及金屬導體127,使互連件延展至在連接物彼此間具有大量凸塊或背緣連接物129及/或更大間距的下一級。
因此,需要能夠利用基於成熟的膜的技術,藉由使用更低成本製程設備以更低成本產生更薄封裝的方法,而且該方法不可依靠基於板材的處理過程,此種基於板材的處理過程促使製程的設備成本更高,並且導致總製造成本超過市場能接受的負擔。
本揭露的一態樣是一種形成諸如聚亞醯胺(polyimide)膜的圖案化聚合物膜的方法,用以從一芯片至另一芯片、或從芯片至外部接合點產生高密度互連件。
本揭露的另一態樣是一種諸如聚亞醯胺膜的圖案化聚合物膜,用以從一芯片至另一芯片、或從芯片至外部接合點產生高密度互連件。
本揭露的另外的態樣及其它特徵將會在以下說明中提出,並且對於審查以下內容的所屬領域具有普通技術者部分將會顯而易見,或可經由實踐本揭露來學習。可如隨附申請專利範圍第書中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露,可藉由一種製作半導體裝置的方法部分達到一些技術功效,該方法包括在聚合物膜的第一表面中形成錐形通孔(tapered via hole);在半導體裝置的第一表面上形成導電柱;將該導電銅柱的可焊接表面接合至該聚合物膜的第二表面上的金屬化物(metallization);以底部填充(underfill)材料包覆該導電柱將該半導體裝置接合至該聚合物膜的該第一表面;以及在該半導體裝置及聚合物膜上方沉積封裝材料。
本揭露的態樣包括以雷射剝蝕(ablation)或蝕刻在該聚合物膜的該第一表面中形成該錐形通孔。其它態樣包括該聚合物膜包含聚亞醯胺。另一態樣包括該聚合物膜的該第二表面上的該金屬化物包含該聚合物膜的該第
二表面上的導電圖案;該錐形通孔終止於該導電圖案;該導電柱在該半導體裝置的該第一表面上的位置對應於該錐形通孔在該聚合物膜的該第一表面上的位置;該半導體裝置使用該錐形通孔電連接至該聚合物膜的該第二表面上的該導電圖案,以安置該半導體裝置並使該半導體裝置與對應的通孔對準。又其它態樣包括使該聚合物膜的該第二表面經受銅圖案化;以及在該銅圖案化後,於該聚合物膜的該第二表面上形成焊塊。另一態樣包括該焊塊包含錫(Sn)及銀(Ag)。進一步態樣包括該底部填充材料,其包括無流動底部填充材料。其它態樣包括在接合該半導體裝置後,固化該無流動底部填充材料。又其它態樣包括封裝該半導體裝置的四個面露出該半導體裝置的該第二表面,或封裝該半導體裝置的五個面涵蓋該半導體裝置的該第二表面。其它態樣包括將該錐形通孔形成為具有貼近該半導體裝置的第一直徑、及遠離該半導體裝置的第二直徑,該第一直徑大於該第二直徑。該導電柱具有比該錐形通孔的該第一與第二直徑更小的第三直徑,該導電柱包括含有Sn-Ag的可焊接材料,該可焊接材料位在該柱的表面上而未與該半導體裝置接觸,該導電柱及可焊接材料的高度類似於該聚合物膜的厚度,使得當該半導體裝置接合至該聚合物膜時,介於該半導體裝置的該第一表面與該聚合物膜的該第一表面之間的距離等於底部填充材料的所欲厚度。另一態樣包括在形成該焊塊前,先於該聚合物膜的該第二表面上沉積並圖案化介電層。
本揭露的另一態樣是一種裝置,該裝置包括:內有形成錐形通孔的聚合物膜;具有導電柱的半導體裝置,該導電柱在與該半導體裝置相對的表面上有沉積的焊料,而且底部填充材料包覆該導電柱將該導電柱接合至該聚合物膜的第一表面;以及沉積於該半導體裝置及聚合物膜上方的封裝材料,其中該底部填充材料將該半導體裝置的表面接合至該聚合物膜的該第一表面而容許在溫度循環期間移動。
態樣包括該封裝材料,其包含環氧塑模(epoxy molding)。其它態樣包括該底部填充材料,其包含已固化無流動底部填充材料。又其它態樣包括該導電柱,其包含Cu。進一步態樣包括該聚合物膜,其包含聚亞醯胺。
其它態樣包括多個聚合物膜層及多個圖案化導體層的使用,其中多個導體層可藉由使用介於兩相鄰導體層之間、或介於非相鄰導體層之間的導電通孔來連接。藉由添加多個聚合物膜層及導電圖案,可增加芯片彼此間的互連件密度、或從一芯片至其下一個接合點的互連件密度。
其它態樣包括一種方法,該方法包括:以雷射剝蝕或蝕刻在聚亞醯胺膜的第一表面中形成錐形通孔,該錐形通孔具有貼近該聚亞醯胺膜的該第一表面的第一直徑、及遠離該第一表面的第二直徑,該第一直徑大於該第二直徑;在各該錐形通孔中形成導電柱,各導電柱包覆(clad)該聚亞醯胺膜、或黏著地附接至該聚亞醯胺膜;以
無流動底部填充材料包覆該導電銅柱將該半導體裝置接合至該聚亞醯胺膜的該第一表面;以及在該半導體裝置及聚亞醯胺膜上方沉積環氧塑模材料作為封裝劑。
態樣包括在該半導體裝置接合後,固化該無流動底部填充材料。其它態樣包括使該聚合物膜的第二表面經受銅圖案化;以及在該銅圖案化後,於該聚合物膜的該第二表面上形成焊塊。進一步態樣包括在形成該焊塊前,先於該聚亞醯胺膜的該第二表面上沉積並圖案化介電層。
本揭露的另外的態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變為顯而易見,其中本揭露的具體實施例單純地藉由經深思用以實行本揭露的最佳模式的說明來描述。如將會瞭解的是,本揭露能夠是其它及不同的具體實施例,而且其數項細節能夠在各種明顯方面進行修改,全都不會脫離本揭露。因此,圖式及說明本質上要視為說明性,而不是作為限制。
101‧‧‧堆疊封裝
103‧‧‧晶圓級扇出封裝
105‧‧‧導電圖案
107‧‧‧第一半導體晶粒
109‧‧‧第二半導體晶粒
111‧‧‧基板
113‧‧‧封裝劑
115‧‧‧焊球
117‧‧‧導電通孔
119‧‧‧半導體晶粒
121‧‧‧焊球、矽晶粒
123‧‧‧熱固性材料、封裝材料
125‧‧‧介電材料
127‧‧‧金屬導體
129‧‧‧凸塊或背緣連接物
201‧‧‧聚合物膜
203‧‧‧通孔
205‧‧‧圖案化銅膜
207‧‧‧半導體裝置
209‧‧‧導電柱、Cu柱
210‧‧‧可焊接材料/覆蓋體
211‧‧‧黏著劑
213‧‧‧銅墊
401‧‧‧環氧塑模化合物
501‧‧‧焊塊
601‧‧‧穿孔
701‧‧‧聚合物膜層
703‧‧‧導體層、導電圖案
705‧‧‧導電通孔
707‧‧‧黏著劑
本揭露是在隨附圖式的附圖中舉例來說明,但非作為限制,圖中相同的參考元件符號是指類似的元件,並且其中:第1A圖繪示PoP組態的習知FOWLCSP的截面圖;第1B圖繪示習知扇入晶圓級封裝的截面
圖,而第1C圖繪示習知扇出晶圓級封裝的截面圖;第2A圖至第5圖根據一例示性具體實施例,示意性繪示用以產生基於薄膜的扇出與多晶粒封裝的程序流程的截面圖;第6A圖至第6C圖根據一例示性具體實施例,分別是薄膜結構的俯視圖、側視圖及仰視圖;以及第7圖繪示具有多個聚合物膜層及多個圖案化導體層的結構的截面圖。
在以下說明中,為了闡釋目的,提出許多特定細節以便透徹瞭解例示性具體實施例。然而,應顯而易知的是,沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中,眾所周知的結構及裝置是以方塊圖形式來展示,為的是要避免不必要地混淆例示性具體實施例。另外,除非另有所指,本說明書及申請專利範圍第書中用來表達成分、反應條件等等的量、比率、及數值特性的所有數字都要瞭解為在所有實例中是以“約”一語來修飾。
本揭露處理並解決目前大型薄板材、及扇出WLCSP基於板材的處理所帶來的跨板材的運行模式圖案的問題,扇出WLCSP在處理方面存在固有缺點。根據本揭露的具體實施例,基於成熟的膜的技術用於以更低成本產生更薄的封裝。
根據本揭露的具體實施例的方法,包括在
聚合物膜的第一表面中形成錐形通孔。導電柱是在各該錐形通孔中形成。以底部填充材料包覆該導電柱將該半導體裝置接合至該聚合物膜的該第一表面。封裝材料是在該半導體裝置及聚合物膜上方形成。
經由以下的詳細說明,其它態樣、特徵及技術功效對所屬技術領域中具有通常知識者將會輕易地顯而易見,其中較佳具體實施例是單純地藉由經深思的最佳模式的說明來展示並且描述。本揭露能夠是其它及不同的具體實施例,而且其數項細節能夠在各種明顯方面進行修改。因此,圖式及說明本質上要視為說明性,而不是作為限制。
言及第2A圖,所示乃聚合物膜201。聚合物膜201具有高熱穩定性(例如:高耐熱性)。膜中所用聚合物的一實施例是聚亞醯胺,聚亞醯胺是一種亞醯胺單體聚合物。聚亞醯胺已知具備熱穩定性、良好的耐化學性及優異的機械特性。聚亞醯胺膜具有良好的機械伸長率及抗拉強度,也有助於該聚亞醯胺膜與已沉積金屬化物之間的黏附力。在第2A圖中,該聚合物膜含有藉由蝕刻或雷射剝蝕在該膜中形成的通孔203。該聚合物膜具有50μm或更小的厚度。在形成通孔203前,銅層黏附至聚合物膜201,並且經圖案化以產生圖案化銅膜205。通孔203為錐形通孔。
在第2B圖中,導電柱209是在半導體裝置207上形成。該導電柱具有在與該導電柱附接至該半導體
裝置處相對的表面上形成的可焊接材料/覆蓋體210。該導電柱包括Cu柱本體及例如為鎳(Ni)、錫(Sn)或銀(Ag)的可焊接材料/覆蓋體210。Cu柱與覆蓋體的高度約與該聚合物膜的高度一樣。如第2C圖所示,黏著劑211的薄層,例如厚度為5μm至20μm的一層,是在半導體裝置207上的Cu柱209彼此間形成,將會作用為最終封裝的底部填充體。該底部填充體是在該最終封裝中用來進行應變管理。最終封裝所具有的厚度可達到小於100μm。
第3圖繪示接合至聚合物膜201的半導體裝置(例如:半導體芯片)207,該聚合物膜具有在錐形通孔203中突出的Cu柱209。在接合前,銅墊213可透過聚合物膜201中的通孔203外露,且其表面可塗布有阻障物(barrier)與諸如Ni、Sn或Ag的可焊接材料。由於通孔203的形狀為錐形,接合期間因而得以改良Cu柱209的對準。形狀為錐形的通孔203有助於Cu柱209在接合期間自對準。聚合物膜中的該錐形通孔將會為了使接合速度更快且置放設備成本更低而進行自對準。Cu柱209在焊接至圖案化Cu膜205時,將突入通孔203以產生導電通孔。黏著劑211是一種無流動底部填充材料,其將該半導體裝置表面接合至聚合物膜201,並且容許在溫度循環期間於被塗敷的焊塊與該半導體裝置之間移動。Cu柱209具有的高度大約等於聚合物膜201的厚度。半導體裝置207安置成使得Cu柱209突入聚合物膜201中的該通孔,而且Cu柱209的焊料覆蓋體與圖案化銅膜205的可焊接塗料接觸。Cu柱209
與圖案化銅膜205乃藉由將Cu柱209的該焊料覆蓋體加熱至該焊料覆蓋體的熔點而焊接在一起,同時與Cu柱209及圖案化銅膜205接觸。黏著劑211(即無流動底部填充材料)經熱固化以將聚合物膜201固定至半導體裝置207的表面。黏著劑211是一種基於環氧樹脂的材料。
如第4圖所示,環氧塑模化合物401是在聚合物膜201及半導體裝置207上方形成以將兩者封裝。該封裝包括封裝該半導體裝置的四個面露出該半導體裝置的該第二表面,或封裝該半導體裝置的五個面涵蓋該半導體裝置的該第二表面。言及第5圖,焊塊501塗敷至具有圖案化銅膜205的聚合物膜201的表面。焊塊501作用為用以將半導體裝置207嵌裝至諸如印刷電路板(PCB)的外部電路系統或另一半導體裝置/芯片或晶圓的匹配接墊的途徑。該焊塊可由Sn與Ag及其它元件製成。
在第6A圖、第6B圖及第6C圖中,分別展示的是薄膜聚合物結構的俯視圖、側視圖及仰視圖。聚合物膜201展示為內有形成錐形通孔203且具有塗敷至聚合物膜201的表面的圖案化Cu膜205。圖案化介電層(圖未示)可設於圖案化Cu膜205上方。可塗敷該介電層以防止焊接錫球吸濕(wicking)並防止電氣短路。如第6A圖、第6B圖及第6C圖中所示的聚合物膜沿著側邊設於具有穿孔601的膠捲(film roll)中。當聚合物隨著換模(tooling change)而剝除/繞卷時,可於現有製造設備上完成裝配。
第7圖繪示多個聚合物膜層701及多個圖案
化導體層703的一使用實施例,其中多個導體層703可藉由使用介於兩相鄰導體層703之間、或介於非相鄰導體層703之間的導電通孔705來連接。黏著劑707乃置於相鄰的聚合物膜層701之間。藉由添加多個聚合物膜層701及導電圖案703,可增加芯片彼此間的互連件密度、或從一芯片至其下一個接合點的互連件密度。
本揭露的具體實施例可達成數種技術功效,例如:以更低成本及更小占位面積封裝的矽芯片使彼此間增加矽內容物及互連件。單一金屬層(或多於一層)可經圖案化而具有細線及空間。相較於其它在半導體封裝時用的常見材料,在膜中形成通孔的成本較省。Cu柱技術是一種成熟且具有成本效益的技術,而且產生柱子/柱體所需的鍍覆時間低於經接種(seeded)側壁填充等效通孔的時間。本申請案中的膜厚可以等於或小於25μm,比任何其它封裝基板材料還薄,並且僅稍厚於FO-WLCSP中習知的積累(build up)圖案。以Cu柱當作通孔使用,能使最終封裝達到可能的最薄厚度(即小於100μm),非常符合需求。此外,利用本申請案,當附有換模的條體或卷盤至卷盤線(reel to reel line)可用於達到最低成本時,可在現有製造設備上完成裝配,類似於RFID標簽。如以上所述,膜通孔的斜度用來進行自對準,並且用來使接合速度更快且置放設備成本更低。另外,藉由使用大量採購用以支持所欲最終產品數量的市售膜,將會降低與基於板材的FO-WLP解決方案相關聯的資本風險,該FO-WLP解決方案取決於更
昂貴的製造設備及其相關聯的固定成本,該固定成本不因給定機器上生成的產品數量而改變。
根據本揭露的具體實施例所形成的裝置符合各種產業應用的利用性要求,例如微處理器、智慧型手機、行動電話、手機、機上盒、DVD錄影機與播放器、汽車導航、印表機與周邊裝置、網路連結與電信設備、遊戲系統及數位相機。本揭露因此符合使用基於薄膜的扇出與多晶粒封裝平台的各類高度整合半導體裝置中任一者在製造方面的產業利用性。
在前述說明中,本揭露是參照其例示性具體實施例來說明。然而,將會證實可對其進行各種修改及變更,但不會脫離本揭露的更廣泛精神與範疇,如申請專利範圍中所提。本說明書及圖式從而要視為說明性而非作為限制。瞭解的是,本揭露能夠使用各種其它結合及具體實施例,並且在如本文中所表達的本發明概念的範疇內能夠有任何變更或修改。
201‧‧‧聚合物膜
207‧‧‧半導體裝置
401‧‧‧環氧塑模化合物
501‧‧‧焊塊
Claims (20)
- 一種封裝半導體的方法,該方法包含:在聚合物膜的第一表面中形成錐形通孔,該聚合物膜的第二表面有金屬化物;在半導體裝置的第一表面上形成導電柱;將該導電柱的可焊接表面接合至該聚合物膜的該第二表面上的該金屬化物;以底部填充材料包覆該導電柱將該半導體裝置接合至該聚合物膜的該第一表面;以及在該半導體裝置及聚合物膜上方沉積封裝材料。
- 如申請專利範圍第1項所述的方法,其包含:以雷射剝蝕或蝕刻在該聚合物膜的該第一表面中形成該錐形通孔。
- 如申請專利範圍第2項所述的方法,其中,該聚合物膜包含聚亞醯胺。
- 如申請專利範圍第1項所述的方法,其中:該聚合物膜的該第二表面上的該金屬化物包括該聚合物膜的該第二表面上的導電圖案;該錐形通孔終止於該導電圖案;該導電柱在該半導體裝置的該第一表面上的位置對應於該錐形通孔在該聚合物膜的該第一表面上的位置;以及該半導體裝置使用該錐形通孔電連接至該聚合物膜的該第二表面上的該導電圖案,以安置該半導體裝 置並使該半導體裝置與對應的通孔對準。
- 如申請專利範圍第4項所述的方法,其中,該聚合物膜的該第二表面包括銅圖案化;以及在該銅圖案化後,於該聚合物膜的該第二表面上形成焊塊。
- 如申請專利範圍第5項所述的方法,其中,該焊塊包含錫(Sn)及銀(Ag)。
- 如申請專利範圍第1項所述的方法,其中,該底部填充材料包含無流動底部填充材料。
- 如申請專利範圍第7項所述的方法,更包含:在接合該半導體裝置後,固化該無流動底部填充材料。
- 如申請專利範圍第1項所述的方法,更包含:封裝該半導體裝置的四個面露出該半導體裝置的該第二表面,或封裝該半導體裝置的五個面涵蓋該半導體裝置的該第二表面。
- 如申請專利範圍第1項所述的方法,其包含將該錐形通孔形成為具有貼近該半導體裝置的第一直徑、及遠離該半導體裝置的第二直徑,該第一直徑大於該第二直徑,其中,該導電柱具有比該錐形通孔的該第一與第二直徑更小的第三直徑,該導電柱包括含有錫(Sn)-銀(Ag)的可焊接材料,該 可焊接材料位在該導電柱的表面上而未與該半導體裝置接觸,該導電柱及可焊接材料的高度類似於該聚合物膜的厚度,該厚度為50μm或更小,使得當該半導體裝置接合至該聚合物膜時,介於該半導體裝置的該第一表面與該聚合物膜的該第一表面之間的距離等於底部填充材料的所欲厚度。
- 如申請專利範圍第5項所述的方法,更包含:在形成該焊塊前,先於該聚合物膜的該第二表面上沉積並圖案化介電層。
- 一種半導體封裝裝置,其包含:內有形成錐形通孔的聚合物膜;具有導電柱的半導體裝置,該導電柱在與該半導體裝置相對的表面上有沉積的焊料,而且底部填充材料包覆該導電柱將該導電柱接合至該聚合物膜的第一表面;以及沉積於該半導體裝置及聚合物膜上方的封裝材料,其中,該底部填充材料將該半導體裝置的表面接合至該聚合物膜的該第一表面而容許在溫度循環期間移動。
- 如申請專利範圍第12項所述的半導體封裝裝置,其中,該封裝材料包含環氧塑模。
- 如申請專利範圍第12項所述的半導體封裝裝置,其 中,該底部填充材料包含已固化無流動底部填充材料。
- 如申請專利範圍第12項所述的半導體封裝裝置,其中,該導電柱包含銅(Cu),並且該聚合物膜包含聚亞醯胺。
- 如申請專利範圍第12項所述的半導體封裝裝置,更包含藉由在兩相鄰圖案化導體層之間、或非相鄰圖案化導體層之間的導電通孔連接多個聚合物膜層及多個圖案化導體。
- 一種封裝半導體的方法,該方法包含:以雷射剝蝕或蝕刻在聚亞醯胺膜的第一表面中形成錐形通孔,該錐形通孔具有貼近該聚亞醯胺膜的該第一表面的第一直徑、及遠離該第一表面的第二直徑,該第一直徑大於該第二直徑;在各該錐形通孔中形成導電柱,各導電柱包覆該聚亞醯胺膜、或黏著地附接至該聚亞醯胺膜;以無流動底部填充材料包覆該導電柱將半導體裝置接合至該聚亞醯胺膜的該第一表面;以及在該半導體裝置及聚亞醯胺膜上方沉積環氧塑模材料作為封裝劑。
- 如申請專利範圍第17項所述的方法,更包含:在該半導體裝置接合後,固化該無流動底部填充材料。
- 如申請專利範圍第17項所述的方法,其包含:使該聚亞醯胺膜的第二表面經受銅圖案化;以及 在該銅圖案化後,於該聚亞醯胺膜的該第二表面上形成焊塊。
- 如申請專利範圍第19項所述的方法,更包含:在形成該焊塊前,先於該聚亞醯胺膜的該第二表面上沉積並圖案化介電層。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/718,314 US9786574B2 (en) | 2015-05-21 | 2015-05-21 | Thin film based fan out and multi die package platform |
US14/718,314 | 2015-05-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201709353A TW201709353A (zh) | 2017-03-01 |
TWI614814B true TWI614814B (zh) | 2018-02-11 |
Family
ID=57231723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105106863A TWI614814B (zh) | 2015-05-21 | 2016-03-07 | 基於薄膜之扇出及多晶粒封裝平台 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9786574B2 (zh) |
CN (1) | CN106169427B (zh) |
DE (1) | DE102016205559B4 (zh) |
TW (1) | TWI614814B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102615701B1 (ko) | 2018-06-14 | 2023-12-21 | 삼성전자주식회사 | 관통 비아를 포함하는 반도체 장치, 반도체 패키지 및 이의 제조 방법 |
TWI731260B (zh) * | 2018-08-30 | 2021-06-21 | 奕力科技(開曼)股份有限公司 | 半導體基板結構及其製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140339696A1 (en) * | 2011-06-28 | 2014-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure for Wafer Level Package |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7259448B2 (en) * | 2001-05-07 | 2007-08-21 | Broadcom Corporation | Die-up ball grid array package with a heat spreader and method for making the same |
US6926190B2 (en) * | 2002-03-25 | 2005-08-09 | Micron Technology, Inc. | Integrated circuit assemblies and assembly methods |
US7049170B2 (en) * | 2003-12-17 | 2006-05-23 | Tru-Si Technologies, Inc. | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
US8710402B2 (en) * | 2007-06-01 | 2014-04-29 | Electro Scientific Industries, Inc. | Method of and apparatus for laser drilling holes with improved taper |
JP5289832B2 (ja) * | 2008-06-17 | 2013-09-11 | 新光電気工業株式会社 | 半導体装置および半導体装置の製造方法 |
CN201667333U (zh) * | 2009-06-26 | 2010-12-08 | 江阴长电先进封装有限公司 | 新型圆片级扇出芯片封装结构 |
US10297550B2 (en) | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8552556B1 (en) | 2011-11-22 | 2013-10-08 | Amkor Technology, Inc. | Wafer level fan out package |
JP5662551B1 (ja) * | 2013-12-20 | 2015-01-28 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
-
2015
- 2015-05-21 US US14/718,314 patent/US9786574B2/en not_active Expired - Fee Related
-
2016
- 2016-03-07 TW TW105106863A patent/TWI614814B/zh not_active IP Right Cessation
- 2016-04-05 DE DE102016205559.3A patent/DE102016205559B4/de active Active
- 2016-05-20 CN CN201610342168.XA patent/CN106169427B/zh active Active
-
2017
- 2017-08-29 US US15/689,701 patent/US10192802B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140339696A1 (en) * | 2011-06-28 | 2014-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure for Wafer Level Package |
Also Published As
Publication number | Publication date |
---|---|
DE102016205559A1 (de) | 2016-11-24 |
US20170365537A1 (en) | 2017-12-21 |
US20160343633A1 (en) | 2016-11-24 |
US9786574B2 (en) | 2017-10-10 |
TW201709353A (zh) | 2017-03-01 |
CN106169427A (zh) | 2016-11-30 |
US10192802B2 (en) | 2019-01-29 |
DE102016205559B4 (de) | 2022-03-24 |
CN106169427B (zh) | 2019-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107978583B (zh) | 封装结构及其制造方法 | |
CN104752367B (zh) | 晶圆级封装结构及其形成方法 | |
CN109755187B (zh) | 半导体封装装置及其制造方法 | |
US9865548B2 (en) | Polymer member based interconnect | |
US8367473B2 (en) | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof | |
US11139281B2 (en) | Molded underfilling for package on package devices | |
KR101809521B1 (ko) | 반도체 패키지 및 그 제조방법 | |
US9117698B2 (en) | Fabrication method of semiconductor package | |
US9859130B2 (en) | Manufacturing method of interposed substrate | |
TW201804575A (zh) | 整合扇出型封裝 | |
CN104505382A (zh) | 一种圆片级扇出PoP封装结构及其制造方法 | |
CN113809059A (zh) | 衬底结构和其形成方法以及半导体封装结构 | |
US11322471B2 (en) | Semiconductor package structures, semiconductor device packages and methods of manufacturing the same | |
US11854961B2 (en) | Package substrate and method of fabricating the same and chip package structure | |
TW201517187A (zh) | 具有嵌入在延伸基板和底部基板之間的半導體晶粒的半導體裝置 | |
KR101944007B1 (ko) | 반도체 패키지 및 그 제조방법 | |
KR101494414B1 (ko) | 반도체패키지, 반도체패키지유닛 및 반도체패키지 제조방법 | |
TWI614814B (zh) | 基於薄膜之扇出及多晶粒封裝平台 | |
US20230017445A1 (en) | Scalable Extreme Large Size Substrate Integration | |
KR101819558B1 (ko) | 반도체 패키지 및 그 제조방법 | |
CN113299626B (zh) | 一种多芯片封装用的导电组件及其制作方法 | |
CN217183541U (zh) | 高密度线路结构与低密度线路结构组成的多层线路结构 | |
US20230420391A1 (en) | Electronic package and manufacturing method thereof | |
JP2014026997A (ja) | 半導体装置 | |
CN115483179A (zh) | 焊球、倒装芯片结构、堆叠式封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |