CN112864104A - 半导体设备封装和其制造方法 - Google Patents
半导体设备封装和其制造方法 Download PDFInfo
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- CN112864104A CN112864104A CN202010104956.1A CN202010104956A CN112864104A CN 112864104 A CN112864104 A CN 112864104A CN 202010104956 A CN202010104956 A CN 202010104956A CN 112864104 A CN112864104 A CN 112864104A
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Abstract
本公开提供一种半导体设备封装。所述半导体设备封装包含:电子组件;第一钝化层,其具有包围所述电子组件的内表面;以及导电层,其安置在所述第一钝化层的所述内表面上。所述电子组件具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面。所述导电层具有相对粗糙的表面。还公开了一种制造半导体设备封装的方法。
Description
技术领域
本公开大体上涉及一种半导体设备封装和其制造方法,且涉及一种具有导电层的半导体设备封装和其制造方法。
背景技术
半导体设备封装可包含安置在载体上的一些半导体设备(如芯片或裸片)。一些设备可移动或嵌入到载体中以缩小半导体设备封装的大小。
随着技术的进步,需要将相对较多的组件嵌入到载体中以实现小型化,这必然会减小组件与限定用以收纳组件的空间(例如空腔或空位)的侧壁之间的距离。上文所提及的距离的缩小可以是在将介电材料或钝化材料填充到空间中时的巨大挑战。此外,如果将更多的组件集成到载体中,那么散热问题可能变得严重。
发明内容
在一或多个实施例中,一种半导体设备封装包含电子组件;第一钝化层,其具有包围所述电子组件的内表面以及导电层,其安置在第一钝化层的所述内表面上。所述电子组件具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面。所述导电层具有相对粗糙的表面。
在一或多个实施例中,一种半导体设备封装包含电子组件,所述电子组件具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面。所述半导体设备封装进一步包含第一钝化层,所述第一钝化层具有第一表面、与所述第一表面相对的第二表面以及包围电子组件的内表面。所述半导体设备封装进一步包含安置在第一钝化层的内表面上的导电层。所述内表面包含第一部分和在所述第一部分上的第二部分。第一钝化层的内表面的第一部分具有第一宽度,且第一钝化层的内表面的第二部分具有第二宽度。所述第二宽度大于所述第一宽度。
在一或多个实施例中,一种用于制造半导体设备封装的方法包含设置第一钝化层。所述第一钝化层具有第一表面和与所述第一表面相对的第二表面。所述方法进一步包含形成穿透第一钝化层的凹部。在凹部形成之后限定在第一表面与第二表面之间延伸的内表面。所述方法进一步包含将导电层安置在第一钝化层的内表面上。所述方法进一步包含对导电层执行表面处理。
附图说明
当结合附图阅读时,从以下具体实施方式容易理解本公开的各方面。应注意,各种特征可能并未按比例绘制。各种特征的尺寸可出于论述清楚起见而任意地增大或减小。
图1说明根据本公开的一些实施例的半导体设备封装的横截面视图。
图2A说明根据本公开的一些实施例的半导体设备封装的一部分的放大视图。
图2B说明根据本公开的一些实施例的半导体设备封装的一部分的放大视图。
图3说明根据本公开的一些实施例的半导体设备封装的一部分的放大横截面视图。
图4说明根据本公开的一些实施例的半导体设备封装的俯视图。
图5A说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5B说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5C说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5D说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5E说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5F说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5G说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5H说明根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
贯穿图式和具体实施方式使用共同参考标号来指示相同或类似元件。本公开将根据以下结合附图所作出的具体实施方式而更加显而易见。
具体实施方式
以下公开提供用于实施所提供的主题的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例。当然,这些组件和布置仅仅是实例且并不意欲为限制性的。在本公开中,在以下描述中,对在第二特征上方或在第二特征上形成第一特征的参考可包含第一特征与第二特征直接接触地形成的实施例,并且还可包含在第一特征与第二特征之间可形成额外特征,使得第一特征与第二特征可不直接接触的实施例。此外,本公开可以在各个实例中重复参考标号和/或字母。此重复是出于简化和清晰起见,且本身并不指示所论述的各种实施例和/或配置之间的关系。
下文详细论述本公开的实施例。然而,应了解,本公开提供可在各种具体上下文中体现的许多适用概念。所论述的具体实施例仅仅是说明性的且并不限制本公开的范围。
图1说明根据本公开的一些实施例的半导体设备封装1的横截面视图。
参看图1,半导体设备封装1可包含:互连结构10、另一互连结构11、电子组件12、另一电子组件13、包封层14、电接点15、电子组件20、载体21、导电层22以及钝化层23。
载体21可包含表面211和与表面211相对的表面212。载体21可包含在表面211与表面212之间延伸的空腔或空间。载体21可包含表面213(或内表面)和与表面213相对的表面214(或外表面)。表面213可称作所述空腔或空间的侧壁或侧面。
在一些实施例中,载体21可包含互连结构,如导电迹线(如部分22a)或穿孔。载体21可包含芯层或芯基板(core substrate)。在一些实施例中,载体21的芯基板可包含(例如但不限于)模制原料、双马来酰亚胺三嗪(BT)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、防焊剂、味之素堆积膜(ABF)、聚丙烯(PP)、基于环氧的材料或其中两个或多个的组合。
电子组件20可安置在由载体21的表面213限定的空间中。电子组件20可收纳在由载体21的表面213限定的空间中。电子组件20可由载体21的表面213包围。
电子组件20可包含表面201、与表面201相对的表面202以及在表面201与表面202之间延伸的表面203(或侧面)。表面203可面对载体21的表面213。
由于需要将更多的组件(如多个电子组件20)收纳在载体(如载体21)中所限定的空腔或空间中以实现小型化,因此可必然地减小组件与空间的侧面之间的距离(如载体21的表面213与电子组件20的表面203之间的距离),使得在空间中的介电材料(如钝化层23的介电材料)的后续填充操作(如在图5F中说明的操作)中出现处理难题。此外,如果将更多的组件集成到载体中,那么散热问题可能变得严重。
通过在载体21的表面213上设置导电层22并且对导电层22执行表面处理以调整导电层22的表面粗糙度,可促进待在空间中填充的钝化层23的介电材料的流动性且可获得导电层22与钝化层23之间的良好粘着力。此外,导电层22可帮助促进半导体设备封装1中的散热。
如图1中所展示,电子组件20可由钝化层23、导电层22以及载体21包围。钝化层23可包围电子组件20且由导电层22包围。导电层22可包围钝化层23且由载体21包围。
导电层22可安置在载体21的内表面213上。导电层22可与载体21的内表面213直接接触。
导电层22可连接到载体21的部分22a。在一些实施例中,部分22a可具有与导电层22相同的材料。在一些实施例中,部分22a可以是导电层22的延伸部。举例来说,部分22a可朝向外表面214延伸。导电层22的延伸部分(如部分22a)可帮助增强导电层22的粘着力。导电层22的延伸部分(如部分22a)可帮助防止导电层22的分层。
在一些实施例中,导电层22可包含(例如但不限于)铝(Al)、铜(Cu)、铬(Cr)、锡(Sn)、金(Au)、银(Ag)、镍(Ni)或不锈钢或混合物或它们的其它组合。在一些实施例中,部分22a可具有与导电层22不同的材料。
钝化层23可安置在导电层22与电子组件20之间。钝化层23可与电子组件20直接接触。钝化层23可与导电层22直接接触。
在一些实施例中,钝化层23可包含(例如但不限于)介电材料,如预浸复合纤维(例如预浸体)、味之素堆积膜、树脂、基于环氧的材料或它们中的两个或更多个的组合。
钝化层23可包含可填充到载体21的空间中(如在图5F中说明的填充操作)的可流动介电材料。
在一些实施例中,空间可设置有较宽开口以促进钝化层23的介电材料的流动性。在一些实施例中,较宽开口可在不将空隙引入空间中的情况下帮助将介电材料填充于空间中。
举例来说,载体21的表面213可包含具有第一宽度“w1”的部分(其也可称作表面213的第一部分)和具有第二宽度“w2”的另一部分(其也可称作表面213的第二部分)。所述第二部分可紧邻载体21的表面211。所述第二部分可由与表面211连接的载体21的侧壁21s1(如图2B中指示)限定。
第一宽度w1可与第二宽度w2不同。举例来说,如图1中所说明,第一宽度w1小于第二宽度w2。第二宽度w2大于第一宽度w1。
在一些实施例中,电子组件20的表面201的高度可与载体21的表面211的高度不同。举例来说,如图1中所说明,电子组件20的表面201低于载体21的表面211。载体21的表面211高于电子组件20的表面201。
互连结构10和11可安置在载体21的表面(例如顶面和底面)上。互连结构10和11可包含重布层(RDL),且可包含导电单元(如衬垫、电线和/或通孔)和介电层。导电单元的一部分由介电层覆盖或包封,而导电单元的的另一部分从介电层暴露以针对载体21(和嵌入于载体21中的电子组件20)、电子组件12和13以及电接点15提供电连接。
电子组件12和13可安置在背对载体21的互连结构10的表面上。
包封层14可安置在互连结构10上以覆盖或包封电子组件12和13。在一些实施例中,包封层14可包含(例如但不限于)具有填充剂的环氧树脂、模制原料(例如环氧模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、使硅酮分散在其中的材料或其组合。
电接点15(例如焊料球)可安置在背对载体21的互连结构11的表面上,且可在半导体封装设备1与外部组件(例如外部电路或电路板)之间提供电连接。在一些实施例中,电接点15可包含可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)或连接盘网格阵列(LGA)。
电子组件12、13以及20中的每一个可包含芯片或裸片,所述芯片或裸片中包含半导体基板、一或多个集成电路设备以及一或多个上覆互连结构。集成电路设备可包含如晶体管的主动设备和/或如电阻器、电容器、电感器或其组合的被动设备。
在一些实施例中,视产品规格而定,在半导体设备封装1中可存在任何数目的电子组件。举例来说,可存在嵌入于载体21中的任何数目的电子组件。举例来说,可存在安置在互连结构10上的任何数目的电子组件。
图2A说明根据本公开的一些实施例的半导体设备封装的一部分的放大视图。举例来说,图1中的虚线框2A中的部分可以是图2A中所说明的部分。
如图2A中所展示,导电层22可包含与载体21的表面213接触的表面和与钝化层23接触的相对表面223。导电层22的表面223可以是相对粗糙的(或相对不平坦的)表面。
举例来说,与钝化层23直接接触的表面223的一部分的粗糙度可大于表面223的其它部分的粗糙度。举例来说,导电层22的表面223的粗糙度可大于与表面223相对的导电层22的表面的粗糙度。
在一些实施例中,导电层22的表面223的粗糙度可小于载体21的表面213的粗糙度。
在一些实施例中,导电层22的表面223具有介于约0.3微米(μm)到约1.0μm的范围内的算术平均粗糙度(Ra)。在一些实施例中,导电层22的表面223具有介于约3.0μm到约10.0μm的范围内的十点平均粗糙度(Rz)。
在一些实施例中,可将导电层22的表面223的粗糙度设计成小于或等于用以促进钝化层23的介电材料的流动性的数值。在一些实施例中,可将导电层22的表面223的粗糙度设计成高于或等于用以避免钝化层23与导电层22分层的数值。
在一些实施例中,钝化层23可具有与电子组件20接触的表面233和与导电层22接触的相对表面。与导电层22接触的钝化层23的表面可以是相对粗糙的或相对不平坦的表面。
钝化层23可与导电层22接合。举例来说,与导电层22接触的钝化层23的表面可与导电层22的相对粗糙的表面223接合,这增强了导电层22与钝化层23之间的粘着力。
图2B说明根据本公开的一些实施例的半导体设备封装的一部分的放大视图。举例来说,图1中的虚线框2B中的部分可以是图2A中所说明的部分。
如图2B中所展示,载体21的表面213包含侧壁21s1、顶面21t以及侧壁21s2。侧壁21s1可与表面211大体上垂直。顶面21t可与表面211大体上共面。表面211可经由侧壁21s1与顶表面21t连接。表面211、侧壁21s1以及顶面21t可限定在载体21的表面213上的阶梯(或阶梯式特征或阶梯式结构)。
导电层22覆盖或包封载体的表面211的一部分。导电层22覆盖或包封载体21的表面213上的阶梯。导电层22覆盖或包封载体21的侧壁21s1和顶面21t。
导电层22与载体的表面211的一部分直接接触。导电层22与载体21的表面213上的阶梯直接接触。导电层22与载体21的侧壁21s1和顶面21t直接接触。
在阶梯上方的导电层22的表面223可以是倾斜或弯曲表面。举例来说,导电层22填充于由表面21s1和表面21t限定的角度中。举例来说,导电层22覆盖由表面21s1和表面21t限定的角度。
在一些实施例中,在阶梯上方的导电层22的倾斜或弯曲表面可帮助将钝化层23的介电材料引导到载体21的空间中。
图3说明根据本公开的一些实施例的半导体设备封装的结构3的放大横截面视图。在一些实施例中,可用图3中的结构3替代图1中的虚线框2中的结构。
图3中的结构3与图1中的虚线框2内的结构类似,且下文对这两个结构之间的差异进行了描述。
导电层22可与载体21中的锥形部分22b连接。在一些实施例中,锥形部分22b可以是延伸到载体21中的导电层22的一部分。举例来说,导电层22的部分22b可从载体21的表面213朝向载体21的表面214逐渐收窄。在一些实施例中,锥形结构可帮助增强载体21与导电层22之间的粘着力。
尽管图式说明具体形状,但本公开不限于此。延伸到载体21中的导电层的延伸部分可具有任何形状。
图4说明根据本公开的一些实施例的半导体设备封装的俯视图。在一些实施例中,图1中的半导体设备封装1的俯视图可与图4中的俯视图类似。
出于清楚和简明起见,在图4中为了简明起见省略了如图1中所展示的导电层22和钝化层23。
如图4中所展示,载体21包含外表面214、表面211以及内表面213(包含侧壁21s1、侧壁21s2以及顶面21t)。侧壁21s1可与表面211大体上垂直。侧壁21s2可与表面211大体上垂直。顶面21t可与表面211大体上共面。表面211可经由侧壁21s与顶面21t连接。
由侧壁21s1限定的空间具有宽度w2。由侧壁21s2限定的空间具有宽度w1。宽度w2可紧邻表面211。在一些实施例中,由侧壁21s1限定的空间可具有任何合适的形状,且本发明不限于图式中所说明的具体实施例。
在图4中,存在收纳在载体21中的空间中的多于一个的电子组件(如电子组件20A、20B、20C以及20D)。如所提及的,在将具有表面粗糙度的导电层设置在载体21的表面213上的情况下,可促进介电材料到空间中的流动性。因此,可增加半导体设备封装中的电子组件的容量。
图5A、图5B、图5C、图5D、图5E、图5F、图5G以及图5H是根据本公开的一些实施例的在各个制造阶段处的布线结构的横截面视图。为了更好地理解本公开的各个方面,已经简化了这些图式中的至少一些。
参看图5A,可设置载体21。载体21可包含表面211、与表面211相对的表面212以及在表面211与表面212之间延伸的表面214。载体21可包含互连结构,如多个导电迹线21a或穿孔。
参看图5B,可在载体21中形成空间或凹部21r。凹部21r可穿透载体21。凹部21r可具有在表面211与表面212之间延伸的表面213。
可在凹部21r形成之后暴露载体21中的导电迹线21a的表面21a1。
参看图5C,阶梯形成在表面213上。在一些实施例中,阶梯可由路由器(routermachine)、激光或其它切割或塑形构件形成。阶梯可在后续操作中促进介电材料的流动性。
可在切割或塑形操作之后形成侧壁21s1和顶面21t。
参看图5D,导电层22可设置于表面213上。阶梯可由导电层22覆盖。
载体21中的导电层22和导电迹线21a可接合以增强导电层22的粘着力。
可对导电层22执行表面处理以调整导电层22的表面粗糙度。在一些实施例中,表面处理可通过(例如)蚀刻剂或经由其它合适的表面处理来执行。
在表面处理之后,导电层22可包含包围凹部21r的相对粗糙的表面。相对粗糙的表面可在导电层22与在后续操作中形成的介电材料之间维持良好的粘着力。
参看图5E,从图5D中的操作所获得的结构可安置在临时载体或粘着层20a上。电子组件20可设置于粘着层20a上。
电子组件20可收纳在如图5D中所展示的凹部21r中。电子组件20可由载体21的表面213上的导电层22包围。在凹部21r中收纳了电子组件20之后,剩余空间21r1可限定在电子组件20与导电层22之间。
电子组件20可包含表面201、与表面201相对的表面202以及在表面201与表面202之间延伸的表面203(或侧面)。电子组件20可包含表面201上的导电衬垫20c1和表面202上的导电衬垫20c2。
参看图5F,可在如图5E中所展示的剩余空间21r1中填充介电材料,从而形成钝化层23。在一些实施例中,填充操作可由(例如)喷墨打印工艺进行。电子组件20的表面201的高度可低于载体21的表面211的高度以促进填充介电材料。在介电材料填充于剩余空间21r1中之后,可去除如图5E中所展示的粘着层20a。
参看图5G,介电层101可设置于载体21和钝化层23上。在一些实施例中,介电层101可由(例如)涂布、层叠或其它合适的工艺形成。随后,光阻膜(或掩模)可形成在介电层101上,且可经由掩模使介电层101图案化以形成空腔且暴露导电衬垫20c1的一部分。导电材料可安置在介电层101和导电衬垫20c1的暴露表面上,从而形成电连接到导电衬垫20c1的导电迹线和通孔。
与介电层101类似,可在载体21和钝化层23上设置介电层111并使其图案化。导电材料可安置在介电层111和导电衬垫20c2的暴露表面上,从而形成电连接到导电衬垫20c2的导电迹线和通孔。
上文针对形成介电层101与111以及导电迹线和通孔所描述的操作可反复地执行两次或更多次以形成多层介电层和导电迹线,且在图5H中展示了所得结构。
参看图5H,互连结构10和11可安置在载体21的表面(例如顶面和底面)上。
在一些实施例中,一或多个电子组件(如图1中所说明的电子组件12和13)可安置在通过毛细管或经由其它工具背对载体21的互连层10的表面上。在一些实施例中,电子组件可安置在粘着层、胶合或用于裸片附接的其它中间层上。在一些实施例中,包封层(如图1中所说明的包封层14)可安置在互连层10上以覆盖或包封电子组件。在一些实施例中,包封层可由模制技术(如转移模制或压缩模制)形成。在一些实施例中,可在背对载体21的互连层11的表面上设置一或多个电接点(如图1中所说明的电接点15)。所得结构可与如图1中所说明的半导体设备封装1类似。
为易于描述,本文中可使用如“下方”、“在……之下”、“下部”、“在……之上”、“上部”、“左侧”、“右侧”等的空间相对术语来描述如图式中所说明的一个元件或特征与另一元件或特征的关系。除了图式中所描绘的定向之外,空间相对术语还意欲涵盖设备在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词可同样相应地进行解释。应理解,当元件称作“连接到”或“联接到”另一元件时,所述元件可直接连接或联接到另一元件,或可存在中介元件。
如本文中所使用,术语“近似”、“大体上”、“实质”以及“约”用于描述和解释较小变化。当结合事件或情况使用时,术语可指事件或情况精确出现的例子,以及事件或情况极为近似出现的例子。如在本文中相对于给定值或范围所使用,术语“约”通常意指在给定值或范围的±10%、±5%、±1%或±0.5%内。范围可在本文中表示为自一个端点到另一端点或在两个端点之间。除非另外指定,否则本文中所公开的所有范围包含端点。术语“大体上共面”可指在几微米(μm)内沿着同一平面定位(如在10μm内、5μm内、1μm内或0.5μm内沿着同一平面定位)的两个表面。当参考“大体上”相同的数值或特性时,术语可指处于值的平均值的±10%、±5%、±1%或±0.5%内的值。
前文概述本公开的若干实施例和细节方面的特征。本公开中所描述的实施例可易于用作设计或修改用于执行本文中所引入的实施例的相同或类似目的和/或获得相同或类似优势的其它工艺和结构的基础。此类等效构造不脱离本公开的精神和范围,并且可在不脱离本公开的精神和范围的情况下进行各种改变、替代和变更。
Claims (20)
1.一种半导体设备封装,其包括:
电子组件,其具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面;
第一钝化层,其具有包围所述电子组件的内表面;
导电层,其安置在所述第一钝化层的所述内表面上且具有相对粗糙的表面。
2.根据权利要求1所述的半导体设备封装,其中所述导电层具有延伸到所述第一钝化层中的第一部分。
3.根据权利要求1所述的半导体设备封装,其中所述第一钝化层的所述内表面具有阶梯。
4.根据权利要求3所述的半导体设备封装,其中所述阶梯与所述导电层直接接触。
5.根据权利要求3所述的半导体设备封装,其中所述导电层具有倾斜表面。
6.根据权利要求3所述的半导体设备封装,其中所述导电层具有弯曲表面。
7.根据权利要求1所述的半导体设备封装,其中所述导电层的所述相对粗糙的表面具有介于约0.3微米(μm)到约1.0μm的范围内的算术平均粗糙度(Ra)。
8.根据权利要求1所述的半导体设备封装,其中所述导电层的所述相对粗糙的表面具有介于约3.0μm到约10.0μm的范围内的十点平均粗糙度(Rz)。
9.根据权利要求1所述的半导体设备封装,其进一步包括:
第二钝化层,其在所述电子组件(20)与所述导电层之间。
10.根据权利要求9所述的半导体设备封装,其中所述第二钝化层与所述导电层直接接触。
11.根据权利要求1所述的半导体设备封装,其中所述第一钝化层包含限定空间的芯基板,且所述电子组件收纳在所述空间中。
12.根据权利要求11所述的半导体设备封装,其进一步包括:
第二钝化层,其安置在由芯层限定的所述空间中。
13.一种半导体设备封装,其包括:
电子组件,其具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面;以及
第一钝化层,其具有第一表面、与所述第一表面相对的第二表面以及包围绕所述电子组件的内表面,其中所述内表面包含第一部分和在所述第一部分上的第二部分;以及
导电层,其安置在所述第一钝化层的所述内表面上;
其中所述第一钝化层的所述内表面的所述第一部分具有第一宽度,且所述第一钝化层的所述内表面的所述第二部分具有第二宽度,且所述第二宽度大于所述第一宽度。
14.根据权利要求13所述的半导体设备封装,其中所述内表面具有阶梯。
15.根据权利要求14所述的半导体设备封装,其中所述阶梯与所述导电层直接接触。
16.根据权利要求15所述的半导体设备封装,其中所述导电层具有倾斜表面。
17.根据权利要求13所述的半导体设备封装,其中所述导电层具有进入所述第一钝化层的延伸部。
18.一种用于制造半导体设备封装的方法,其包括:
设置第一钝化层,所述第一钝化层具有第一表面和与所述第一表面相对的第二表面;
形成穿透所述第一钝化层的凹部,其中在所述凹部形成之后限定在所述第一表面与所述第二表面之间延伸的内表面;
将导电层安置于所述第一钝化层的所述内表面上;以及
对所述导电层执行表面处理。
19.根据权利要求18所述的方法,其进一步包括:
在所述第一钝化层的所述内表面上形成阶梯式特征。
20.根据权利要求19所述的方法,其进一步包括:
用所述导电层覆盖所述阶梯式特征。
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