JP2009252916A - 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法 - Google Patents
多層配線基板、半導体パッケージ、および半導体パッケージの製造方法 Download PDFInfo
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- 239000011810 insulating material Substances 0.000 description 2
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Abstract
【解決手段】半導体パッケージに含まれる多層配線基板100は、上面および下面にそれぞれ配線層が設けられた第1の絶縁層104および第2の絶縁層106と、第1の絶縁層104および第2の絶縁層106の間に設けられたコア層102と、を含む。第1の絶縁層104と第2の絶縁層106とは、異なる材料により構成される。
【選択図】図1
Description
多層配線基板と、前記多層配線基板上に搭載された半導体チップと、前記半導体チップを封止する封止樹脂と、を含む半導体パッケージであって、
前記多層配線基板は、上面および下面にそれぞれ配線層が設けられた第1の絶縁層と第2の絶縁層と、前記第1の絶縁層および前記第2の絶縁層の間に設けられたコア層と、を含み、
前記第1の絶縁層は、前記第2の絶縁層と異なる材料により構成された半導体パッケージが提供される。
上面および下面にそれぞれ配線層が設けられた第1の絶縁層と第2の絶縁層と、
前記第1の絶縁層および前記第2の絶縁層の間に設けられたコア層と、
を含み、
前記第1の絶縁層は、前記第2の絶縁層と異なる材料により構成された多層配線基板が提供される。
上面および下面にそれぞれ配線層が設けられた2つの絶縁層と、当該絶縁層の間に設けられたコア層とを含む多層配線基板と、前記多層配線基板上に搭載された半導体チップと、前記半導体チップを封止する封止樹脂と、を含む半導体パッケージの製造方法であって、
所望の所定温度において前記半導体パッケージに上または下に凸の反りが生じる場合に、前記所定温度において、前記多層配線基板に前記半導体パッケージに生じる反りと反対側に反りが生じるように、前記2つの絶縁層をそれぞれ異なる材料により構成する工程を含む半導体パッケージの製造方法が提供される。
図5は、半導体パッケージ400を製造する手順を示す工程断面図である。
まず、多層配線基板300上に半導体チップ110を搭載し(図5(a)、図5(b))、半導体チップ110と多層配線基板300とをボンディングワイヤ112等で電気的に接続する(図5(c))。つづいて、半導体チップ110およびボンディングワイヤ112を封止樹脂120で埋め込む(図5(d))。封止樹脂120は、たとえばエポキシ樹脂等により構成することができる。これにより、半導体パッケージ400が形成される。その後、多層配線基板300の裏面に半田ボール130を形成して、マザーボード等(不図示)に搭載する(図5(e))。
図10は、多層配線基板300上に半導体チップ110および封止樹脂120を積層させた半導体パッケージ400の構成の一例を模式的に示す図である。
ここで、反りとは、図14に示すように、基板やパッケージ等の対象物150の中心部の突出した方の底面と、端部底面との高さの差Δhのことをいう。
本実施の形態において、多層配線基板100は、コア層102と、コア層102の上下にそれぞれ設けられた第1の絶縁層104および第2の絶縁層106とを含む。ここで、第1の絶縁層104と第2の絶縁層106とは、異なる材料により構成される。
ここで、本実施の形態におけるパッケージの製造手順は、所望の所定温度において半導体パッケージに上または下に凸の反りが生じる場合に、当該所定温度において、多層配線基板100に半導体パッケージに生じる反りと反対側に反りが生じるように、多層配線基板100のコア層102上下の絶縁層をそれぞれ異なる材料により構成する工程を含む。
半導体パッケージ200と半導体パッケージ400と同様の半導体パッケージの温度に対する反り発生のシミュレーションを行った。結果を図12および13に示す。
図8および図9を参照して説明したように、コア層302の上下に同じ材料により構成された絶縁層を形成した多層配線基板300を用いた半導体パッケージを想定した。このときのシミュレーション結果を図12(a)に示す。
図8および図9を参照して説明したように、コア層302の上下に同じ材料により構成された絶縁層を形成した多層配線基板300を用いた半導体パッケージを想定した。ただし、例1で用いた絶縁層よりも、線膨張係数が低い樹脂材料を用いる想定とした。このときのシミュレーション結果を図12(b)に示す。
図1および図2を参照して説明したように、コア層102の上下に異なる材料により構成された絶縁層をそれぞれ形成した多層配線基板100を用いた半導体パッケージを想定した。ここで、コア層102の下側の絶縁層は例1と同様のものを用い、上側の絶縁層のみ、下側の絶縁層も、線膨張係数が低い樹脂材料を用いる想定とした。このときのシミュレーション結果を図13(a)に示す。
図1および図2を参照して説明したように、コア層102の上下に異なる材料により構成された絶縁層をそれぞれ形成した多層配線基板100を用いた半導体パッケージを想定した。ここで、コア層102の上側の絶縁層は例1と同様のものを用い、下側の絶縁層のみ、上側の絶縁層とは、ガラスクロス材料、樹脂材料、およびプライ数が異なる絶縁層を用いる想定とした。このときのシミュレーション結果を図13(b)に示す。
100a 多層配線基板
100b 多層配線基板
100c 多層配線基板
100d 多層配線基板
102 コア層
104 第1の絶縁層
106 第2の絶縁層
110 半導体チップ
110a 半導体チップ
110b 半導体チップ
112 ボンディングワイヤ
112a ボンディングワイヤ
120 封止樹脂
120a 封止樹脂
120b 封止樹脂
130 半田ボール
130a 半田ボール
130b 半田ボール
140 ランド
150 対象物
200 半導体パッケージ
300 多層配線基板
300a 多層配線基板
300b 多層配線基板
302 コア層
304a 絶縁層
304b 絶縁層
400 半導体パッケージ
400a 半導体パッケージ
400b 半導体パッケージ
Claims (11)
- 多層配線基板と、前記多層配線基板上に搭載された半導体チップと、前記半導体チップを封止する封止樹脂と、を含む半導体パッケージであって、
前記多層配線基板は、上面および下面にそれぞれ配線層が設けられた第1の絶縁層と第2の絶縁層と、前記第1の絶縁層および前記第2の絶縁層の間に設けられたコア層と、を含み、
前記第1の絶縁層は、前記第2の絶縁層と異なる材料により構成された半導体パッケージ。 - 請求項1に記載の半導体パッケージにおいて、
前記第1の絶縁層は、前記第2の絶縁層と略等しい膜厚を有する半導体パッケージ。 - 請求項1または2に記載の半導体パッケージにおいて、
前記第1の絶縁層の上面および下面に設けられた前記配線層と、前記第2の絶縁層の上面および下面に設けられた前記配線層における配線が前記絶縁層の平面積に占める存在比率の差が20%以下である半導体パッケージ。 - 請求項1から3いずれかに記載の半導体パッケージにおいて、
前記第1の絶縁層は、前記第2の絶縁層と線膨張係数が1ppm/℃以上異なる半導体パッケージ。 - 請求項1から4いずれかに記載の半導体パッケージにおいて、
前記多層配線基板は、250℃において、反りを有する半導体パッケージ。 - 上面および下面にそれぞれ配線層が設けられた第1の絶縁層と第2の絶縁層と、
前記第1の絶縁層および前記第2の絶縁層の間に設けられたコア層と、
を含み、
前記第1の絶縁層は、前記第2の絶縁層と異なる材料により構成された多層配線基板。 - 請求項6に記載の多層配線基板において、
前記第1の絶縁層は、前記第2の絶縁層と略等しい膜厚を有する多層配線基板。 - 請求項6または7に記載の多層配線基板において、
前記第1の絶縁層の上面および下面に設けられた前記配線層と、前記第2の絶縁層の上面および下面に設けられた前記配線層における配線が前記絶縁層の平面積に占める存在比率の差が20%以下である多層配線基板。 - 請求項6から8いずれかに記載の多層配線基板において、
前記第1の絶縁層は、前記第2の絶縁層と線膨張係数が1ppm/℃以上異なる多層配線基板。 - 請求項6から9いずれかに記載の多層配線基板において、
250℃において、反りを有する多層配線基板。 - 上面および下面にそれぞれ配線層が設けられた2つの絶縁層と、当該絶縁層の間に設けられたコア層とを含む多層配線基板と、前記多層配線基板上に搭載された半導体チップと、前記半導体チップを封止する封止樹脂と、を含む半導体パッケージの製造方法であって、
所望の所定温度において前記半導体パッケージに上または下に凸の反りが生じる場合に、前記所定温度において、前記多層配線基板に前記半導体パッケージに生じる反りと反対側に反りが生じるように、前記2つの絶縁層をそれぞれ異なる材料により構成する工程を含む半導体パッケージの製造方法。
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JP2008097815A JP2009252916A (ja) | 2008-04-04 | 2008-04-04 | 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法 |
US12/382,546 US7986035B2 (en) | 2008-04-04 | 2009-03-18 | Multilayer wiring substrate, semiconductor package, and method of manufacturing semiconductor package |
CN2009101329693A CN101552254B (zh) | 2008-04-04 | 2009-04-03 | 多层布线基板、半导体封装以及制造半导体封装的方法 |
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Cited By (2)
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JP2010192545A (ja) * | 2009-02-16 | 2010-09-02 | Ngk Spark Plug Co Ltd | 補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板 |
KR101767381B1 (ko) * | 2010-12-30 | 2017-08-11 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 포함하는 반도체 패키지 |
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US8546932B1 (en) | 2012-08-15 | 2013-10-01 | Apple Inc. | Thin substrate PoP structure |
US8963311B2 (en) | 2012-09-26 | 2015-02-24 | Apple Inc. | PoP structure with electrically insulating material between packages |
CN104637824A (zh) * | 2013-11-08 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | 硅片的临时键合和解离工艺方法 |
CN110140433B (zh) * | 2016-12-15 | 2021-10-12 | 株式会社村田制作所 | 电子模块以及电子模块的制造方法 |
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JP2005038906A (ja) | 2003-07-15 | 2005-02-10 | Dainippon Printing Co Ltd | コア層を持たない薄型の配線板 |
JP4764731B2 (ja) * | 2006-01-30 | 2011-09-07 | 富士通株式会社 | 多層構造のプリント配線基板 |
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JP2001217514A (ja) * | 2000-02-03 | 2001-08-10 | Denso Corp | 多層配線基板 |
JP2007294620A (ja) * | 2006-04-24 | 2007-11-08 | Denso Corp | 半導体装置 |
JP2008294387A (ja) * | 2007-04-24 | 2008-12-04 | Hitachi Chem Co Ltd | 半導体装置用ビルドアップ配線板 |
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CN101552254A (zh) | 2009-10-07 |
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