JP4783843B2 - 電子部品内蔵型プリント基板 - Google Patents
電子部品内蔵型プリント基板 Download PDFInfo
- Publication number
- JP4783843B2 JP4783843B2 JP2009120657A JP2009120657A JP4783843B2 JP 4783843 B2 JP4783843 B2 JP 4783843B2 JP 2009120657 A JP2009120657 A JP 2009120657A JP 2009120657 A JP2009120657 A JP 2009120657A JP 4783843 B2 JP4783843 B2 JP 4783843B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thickness
- circuit board
- printed circuit
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010410 layer Substances 0.000 claims description 147
- 229920005989 resin Polymers 0.000 claims description 49
- 239000011347 resin Substances 0.000 claims description 49
- 239000012790 adhesive layer Substances 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000004593 Epoxy Substances 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910002808 Si–O–Si Inorganic materials 0.000 claims description 3
- 125000003118 aryl group Chemical group 0.000 claims description 3
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 3
- 125000004185 ester group Chemical group 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 24
- 238000000034 method Methods 0.000 description 23
- 239000011889 copper foil Substances 0.000 description 14
- 238000002474 experimental method Methods 0.000 description 9
- 239000011888 foil Substances 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 241001122767 Theaceae Species 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
130 キャリアホイル
150 下部回路層
300 第2銅箔
330 キャリアホイル
350 上部回路層
500 電子部品
530 接着層
600 プリプレグ
700 絶縁樹脂層
730 樹脂層
Claims (13)
- 絶縁樹脂層及び回路層を持つベース基板;及び
前記絶縁樹脂層の内部に埋め込まれた電子部品;
を含み、
前記絶縁樹脂層は前記電子部品の厚さの1.3倍〜3倍の厚さを持つことを特徴とする、電子部品内蔵型プリント基板。 - 前記回路層は、前記絶縁樹脂層の上に形成された上部回路層と前記絶縁樹脂層の下に形成された下部回路層を含み、
前記絶縁樹脂層は前記上部回路層の厚さの3倍〜22倍の厚さを持ち、前記上部回路層は前記下部回路層の厚さの1.1倍〜2.6倍の厚さを持つことを特徴とする、請求項1に記載の電子部品内蔵型プリント基板。 - 前記電子部品と前記下部回路層の間に介在された接着層をさらに含み、
前記絶縁樹脂層は前記接着層の厚さの3倍〜9倍の厚さを持つことを特徴とする、請求項1に記載の電子部品内蔵型プリント基板。 - 前記上部回路層及び前記下部回路層は銅でなり、前記絶縁樹脂層は、O−H、N−H、C−H、C−O、及びエステル基(ester group)を含むエポキシ系の樹脂でなることを特徴とする、請求項1に記載の電子部品内蔵型プリント基板。
- 前記電子部品はシリコン半導体素子であることを特徴とする、請求項1に記載の電子部品内蔵型プリント基板。
- 前記接着層は、ダイアッタチフィルム(DAF)、異方性導電膜(ACF;Anisotropic Conductive Film)、導電粒子を除去した非導電膜(NCF;Non−Conductive Film)、異方性導電接着剤(ACA;Anisotropic Conductive Adhesive)、及び非導電接着剤(NCA;Non−Conductive Adhesive)のいずれか1種であることを特徴とする、請求項3に記載の電子部品内蔵型プリント基板。
- 電子部品実装用貫通部が形成されたプリプレグ及び前記プリプレグの上に積層され前記貫通部に充填された樹脂層を持つ絶縁層、及び回路層を持つベース基板;及び
前記貫通部に埋め込まれた電子部品;
を含み、
前記プリプレグは前記電子部品の厚さの1.1倍〜2.5倍の厚さを持ち、前記プリプレグの上に積層された前記樹脂層の厚さは前記電子部品の厚さの0.2倍〜2.5倍であることを特徴とする、電子部品内蔵型プリント基板。 - 前記回路層は、前記絶縁層の上に形成された上部回路層と前記絶縁層の下に形成された下部回路層を含み、
前記絶縁層は前記上部回路層の厚さの3倍〜22倍の厚さを持ち、前記上部回路層は前記下部回路層の厚さの1.1倍〜2.6倍の厚さを持つことを特徴とする、請求項7に記載の電子部品内蔵型プリント基板。 - 前記電子部品と前記下部回路層の間に介在された接着層をさらに含み、
前記絶縁層は前記接着層の厚さの3倍〜9倍の厚さを持つことを特徴とする、請求項7に記載の電子部品内蔵型プリント基板。 - 前記樹脂層は、NH、CH、SiH、芳香環(aromatic ring)、CO、Si−O−Si、Si−O−Cが含まれたシリコンエポキシハイブリッドタイプまたはエポキシであることを特徴とする、請求項7に記載の電子部品内蔵型プリント基板。
- 前記電子部品はシリコン半導体素子であることを特徴とする、請求項7に記載の電子部品内蔵型プリント基板。
- 前記絶縁層は前記プレプレグの厚さの1.2倍〜2倍の厚さを持つことを特徴とする、請求項7に記載の電子部品内蔵型プリント基板。
- 前記接着層は、ダイアッタチフィルム(DAF)、異方性導電膜(ACF;Anisotropic Conductive Film)、導電粒子を除去した非導電膜(NCF;Non−Conductive Film)、異方性導電接着剤(ACA;Anisotropic Conductive Adhesive)、及び非導電接着剤(NCA;Non−Conductive Adhesive)のいずれか1種であることを特徴とする、請求項9に記載の電子部品内蔵型プリント基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090023449A KR101055509B1 (ko) | 2009-03-19 | 2009-03-19 | 전자부품 내장형 인쇄회로기판 |
KR10-2009-0023449 | 2009-03-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010226069A JP2010226069A (ja) | 2010-10-07 |
JP4783843B2 true JP4783843B2 (ja) | 2011-09-28 |
Family
ID=42736507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009120657A Active JP4783843B2 (ja) | 2009-03-19 | 2009-05-19 | 電子部品内蔵型プリント基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8552305B2 (ja) |
JP (1) | JP4783843B2 (ja) |
KR (1) | KR101055509B1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101253514B1 (ko) * | 2011-10-27 | 2013-04-11 | 아페리오(주) | 열팽창수축률 차이로 인한 기판 휨 문제 해결방법 및 이를 적용한 전자부품 내장형 인쇄회로기판 |
JP2014038890A (ja) * | 2012-08-10 | 2014-02-27 | Ibiden Co Ltd | 配線板及び配線板の製造方法 |
CN104982097A (zh) * | 2013-02-12 | 2015-10-14 | 名幸电子有限公司 | 内置有零件的基板及其制造方法 |
JP2015028986A (ja) * | 2013-07-30 | 2015-02-12 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
US9613933B2 (en) | 2014-03-05 | 2017-04-04 | Intel Corporation | Package structure to enhance yield of TMI interconnections |
EP3091822A1 (en) * | 2015-05-08 | 2016-11-09 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for the production of an electronic module as well as corresponding electronic module |
JP6712764B2 (ja) * | 2015-05-25 | 2020-06-24 | パナソニックIpマネジメント株式会社 | 伸縮性フレキシブル基板およびその製造方法 |
US10231338B2 (en) | 2015-06-24 | 2019-03-12 | Intel Corporation | Methods of forming trenches in packages structures and structures formed thereby |
EP3148300B1 (en) | 2015-09-24 | 2023-07-26 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Connection system for electronic components |
CN107295746B (zh) | 2016-03-31 | 2021-06-15 | 奥特斯(中国)有限公司 | 器件载体及其制造方法 |
KR102366970B1 (ko) | 2017-05-16 | 2022-02-24 | 삼성전자주식회사 | 반도체 패키지 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996005614A1 (en) * | 1994-08-12 | 1996-02-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Flip chip bonding with non-conductive adhesive |
JP2842378B2 (ja) * | 1996-05-31 | 1999-01-06 | 日本電気株式会社 | 電子回路基板の高密度実装構造 |
TW459032B (en) * | 1998-03-18 | 2001-10-11 | Sumitomo Bakelite Co | An anisotropic conductive adhesive and method for preparation thereof and an electronic apparatus using said adhesive |
EP1990833A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
JP2002009110A (ja) * | 2000-06-16 | 2002-01-11 | Nec Corp | 半導体装置 |
EP1321980A4 (en) * | 2000-09-25 | 2007-04-04 | Ibiden Co Ltd | SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD |
JP3888578B2 (ja) * | 2002-01-15 | 2007-03-07 | ソニー株式会社 | 電子部品ユニット製造方法 |
JP4346333B2 (ja) * | 2003-03-26 | 2009-10-21 | 新光電気工業株式会社 | 半導体素子を内蔵した多層回路基板の製造方法 |
MY142246A (en) * | 2003-06-10 | 2010-11-15 | Hitachi Chemical Co Ltd | Adhesive film and process for preparing the same as well as adhesive sheet and semiconductor device |
FI20031341A (fi) * | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Menetelmä elektroniikkamoduulin valmistamiseksi |
DE102004005300A1 (de) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Verfahren zum Behandeln von Trägermaterial zur Herstellung von Schltungsträgern und Anwendung des Verfahrens |
JP4298559B2 (ja) * | 2004-03-29 | 2009-07-22 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP4575071B2 (ja) * | 2004-08-02 | 2010-11-04 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
KR100598275B1 (ko) * | 2004-09-15 | 2006-07-10 | 삼성전기주식회사 | 수동소자 내장형 인쇄회로기판 및 그 제조 방법 |
JP4792749B2 (ja) | 2005-01-14 | 2011-10-12 | 大日本印刷株式会社 | 電子部品内蔵プリント配線板の製造方法 |
JP2007142355A (ja) * | 2005-10-18 | 2007-06-07 | Matsushita Electric Ind Co Ltd | 電子部品内蔵モジュール |
JP5117692B2 (ja) * | 2006-07-14 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5100081B2 (ja) * | 2006-10-20 | 2012-12-19 | 新光電気工業株式会社 | 電子部品搭載多層配線基板及びその製造方法 |
JP2008159819A (ja) * | 2006-12-22 | 2008-07-10 | Tdk Corp | 電子部品の実装方法、電子部品内蔵基板の製造方法、及び電子部品内蔵基板 |
KR100832653B1 (ko) | 2007-06-08 | 2008-05-27 | 삼성전기주식회사 | 부품 내장형 인쇄회로기판 및 그 제조방법 |
CN101822132B (zh) * | 2007-10-16 | 2012-12-26 | 住友电木株式会社 | 搭载半导体元件的基板 |
KR101067109B1 (ko) * | 2010-04-26 | 2011-09-26 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
-
2009
- 2009-03-19 KR KR1020090023449A patent/KR101055509B1/ko active IP Right Grant
- 2009-05-19 JP JP2009120657A patent/JP4783843B2/ja active Active
- 2009-06-24 US US12/491,043 patent/US8552305B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20100236821A1 (en) | 2010-09-23 |
JP2010226069A (ja) | 2010-10-07 |
US8552305B2 (en) | 2013-10-08 |
KR101055509B1 (ko) | 2011-08-08 |
KR20100104805A (ko) | 2010-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4783843B2 (ja) | 電子部品内蔵型プリント基板 | |
KR101248713B1 (ko) | 배선판 및 그의 제조 방법 | |
KR100987688B1 (ko) | 프린트 배선 기판 및 프린트 배선 기판의 제조 방법 | |
KR101342031B1 (ko) | 다층 배선 기판 및 그 제조 방법 | |
JP5703010B2 (ja) | 半導体パッケージ及びその製造方法 | |
US20100224397A1 (en) | Wiring board and method for manufacturing the same | |
JP2006173388A (ja) | 多段構成半導体モジュールおよびその製造方法 | |
JP2008085089A (ja) | 樹脂配線基板および半導体装置 | |
US8186042B2 (en) | Manufacturing method of a printed board assembly | |
US20130161085A1 (en) | Printed circuit board and method for manufacturing the same | |
JP2011071315A (ja) | 配線基板及び配線基板の製造方法 | |
CN111524863A (zh) | 半导体器件及其制造方法 | |
JP2017034059A (ja) | プリント配線板、半導体パッケージおよびプリント配線板の製造方法 | |
US20100214752A1 (en) | Multilayer wiring board and method for manufacturing the same | |
KR101701380B1 (ko) | 소자 내장형 연성회로기판 및 이의 제조방법 | |
JP2011187912A (ja) | 電子素子内蔵型印刷回路基板及びその製造方法 | |
US10111335B2 (en) | Printed wiring board | |
JP2009272435A (ja) | 部品内蔵基板及びその製造方法 | |
JP4324732B2 (ja) | 半導体装置の製造方法 | |
JP2009004813A (ja) | 半導体搭載用配線基板 | |
JP2012186270A (ja) | 半導体パッケージの製造方法 | |
JP2008098202A (ja) | 多層配線基板、多層配線基板構造体 | |
JP5206217B2 (ja) | 多層配線基板及びそれを用いた電子装置 | |
JP2007221117A (ja) | 部品内蔵基板およびその製造方法 | |
JP2006080356A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110705 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110711 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140715 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4783843 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |