CN101315939A - 具有晶粒接收开孔的芯片尺寸影像传感器及其制造方法 - Google Patents

具有晶粒接收开孔的芯片尺寸影像传感器及其制造方法 Download PDF

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CN101315939A
CN101315939A CNA2008100977980A CN200810097798A CN101315939A CN 101315939 A CN101315939 A CN 101315939A CN A2008100977980 A CNA2008100977980 A CN A2008100977980A CN 200810097798 A CN200810097798 A CN 200810097798A CN 101315939 A CN101315939 A CN 101315939A
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crystal grain
substrate
perforation
image sensor
zone
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杨文焜
张瑞贤
许献文
林殿方
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Yupei Science & Technology Co Ltd
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Abstract

本发明公开了一种具有晶粒接收开孔的芯片尺寸影像传感器及其制造方法,影像传感器包含具有晶粒接收穿孔以及接触穿孔的基板,其中终端接触垫形成于接触穿孔之下,接触垫形成于基板上表面。具微透镜区域的晶粒通过黏胶材料配置于晶粒接收穿孔内。厚介电层形成于上述晶粒主动表面以及除微透镜区域外的基板上表面。输出入焊垫形成于晶粒与基板上,用以电性连接的连接线耦合至晶粒的接合垫及基板的接触垫。核心材质填充进入晶粒边缘、晶粒背部、穿孔侧壁间的缝隙。透明罩利用黏胶置于晶粒与介电层之上产生一空隙介于透镜与透明罩之间。导电凸块选择性耦合到终端垫。本发明公开的产品和方法可广泛应用于半导体技术领域中。

Description

具有晶粒接收开孔的芯片尺寸影像传感器及其制造方法
技术领域
本发明涉及面板级封装(panel level package,PLP),尤其涉及一种具有晶粒接收开孔的基板以容置影像传感器晶粒的面板级封装。
背景技术
随着半导体技术的快速发展,半导体晶粒密度提升以及微小化已经成为趋势。因此对于如此高密度的封装技术及内联机技术也提升以适用上述的状态。传统的覆晶结构中,锡球数组形成于晶粒的表面,透过传统的锡膏通过锡球罩幕制作以形成所想要的图案。封装功能包含散热、讯号传输、电源分配、保护等,当芯片更加复杂,传统的封装如导线架封装、软式封装、刚性封装、无法满足高密度小尺寸芯片的需求。
再者,由于一般封装技术必须先将晶圆上的晶粒分割为个别晶粒,再将晶粒分别封装,因此上述技术的制作过程十分费时。因为晶粒封装技术与集成电路的发展有密切关联,因此封装技术对于电子组件的尺寸要求越来越高。基于上述理由,现今的封装技术已逐渐趋向采用球门阵列封装(BGA)、覆晶球门阵列封装、芯片尺寸封装、晶圆级封装的技术。应可理解「晶圆级封装(WLP)」指晶圆上所有封装及交互连接结构,如同其它制程步骤,于切割为个别晶粒之前进行。一般而言,在完成所有配装制程或封装制程之后,由具有复数半导体晶粒的晶圆中将个别半导体封装分离。上述晶圆级封装具有极小的尺寸及良好的电性。
晶圆级封装(WLP)技术为高级封装技术,其晶粒于晶圆上加以制造及测试,且接着通过切割而分离以用于在表面黏着生产线中组装。因晶圆级封装技术利用整个晶圆作为目标,而非利用单一芯片或晶粒,因此于进行分离程序之前,封装及测试皆已完成。此外,采用晶圆级封装(WLP)技术,线接合、晶粒黏着及底部填充的程序可予以省略。通过利用晶圆级封装技术,可减少成本及制造时间且晶圆级封装的最后结构尺寸可相当于晶粒大小,故此技术可满足电子装置的微型化需求。
虽晶圆级封装技术具有上述优点,然而仍存在一些影响晶圆级封装技术的接受度的问题。例如,虽利用晶圆级封装技术可减少集成电路与互连基板间的热膨胀系数(CTE)不匹配,然而当组件尺寸缩小,晶圆级封装结构的材料间的热膨胀系数差异变为另一造成结构的机械不稳定的关键因素。再者,于此晶圆级芯片尺寸封装中,形成于半导体晶粒上的数个接合垫透过牵涉到重分布层(RDL)的常用重分布程序予以重分布进入数个区域数组形式的金属垫。焊锡球直接熔接于金属垫上,而金属垫采用重分布程序以区域数组形式形成。一般而言,所有经堆栈的重分布层系形成于晶粒上的增层上。因此,封装的厚度会增加。这与缩小芯片尺寸的需求相抵触。
因此,本发明提出一种FO-WLP结构无须采上述的堆栈增层以及RDL以降低芯片的厚度,克服上述封装问题以及提供较佳性能、热循环可靠度测试。
发明内容
本发明提供的封装包含具有晶粒接收穿孔以及接触穿孔的基板,其中终端接触垫形成于接触穿孔之下,以及接触垫形成于基板上表面。具微透镜区域的晶粒通过黏胶材料配置于晶粒接收穿孔内。厚介电层形成于上述晶粒主动表面以及除微透镜区域外的基板上表面。输出入焊垫形成于晶粒与基板上,用以电性连接的连接线耦合至晶粒的接合垫及基板的接触垫。核心材质(core paste)填充进入晶粒边缘、晶粒背部、穿孔侧壁间的缝隙。透明罩利用黏胶置于晶粒与介电层之上产生一空隙介于透镜与透明罩之间。导电凸块选择性耦合到终端垫。
本发明公开一种制作影像传感器的方法,包含:提供一基材,该基板具有晶粒穿孔以及接触穿孔形成于其中,终端垫形成于该接触穿孔之下侧以及接触垫配置于该基板的上表面;使用为对位检放系统重分布已知良好传感器晶粒于一制具上;填充核心材质于该晶粒、晶粒穿孔侧壁之间,以及该晶粒背面;形成介电层于该晶粒以及该基板之上,除该微透镜区域、接合垫区域以及接触垫区域;形成接合导线于该晶粒与该基板之上,用以耦合该晶粒以及接触垫;接合透明罩于一面板上,其位于该介电层之上;自终端金属侧切割该面板;延着切割道分离该透明罩以形成封装单体。其中还包含制作保护层于该微透镜区域以保护微透镜以防粒子污染。还包含印刷锡膏于该终端垫以及回流该锡膏以形成导电凸块。
一种影像传感器模块,包含:软性电路板,具有电路、接触垫、连接器形成其中;锡膏接合该连接垫以及基板终端垫;其中该基板,具有晶粒穿孔以及接触穿孔形成于其中,终端垫形成于该接触穿孔之下侧以及接触垫配置于该基板的上表面;影像传感器晶粒,置于该晶粒穿孔中,其中该影像传感器晶粒具有微透镜区域;介电层,形成于该晶粒以及该基板之上,除该微透镜区域、接合垫区域以及接触垫区域;接合导线,形成于该晶粒与该基板之上,用以耦合该晶粒以及接触垫;核心材质,填充于该晶粒、晶粒穿孔侧壁之间,以及该晶粒背面;透明罩,配置于该晶粒以及该介电层之上,且产生一间隙位于该透明罩与该微透镜之间;及透镜支撑架,固定于该软性电路板上,使光得以穿过该微透镜。其中还包含被动组件焊于该软性电路板上。
其中还包含保护层形成于该微透镜以避免微粒污染。保护层材质包含二氧化硅、三氧化二铝或氟聚合物(fluoro-polymer),保护层具有防水、防油特性。且最好具有0.1至0.3微米的厚度及接近1(空气反射系数)的反射系数。可以利用旋涂玻璃(SOG)技术予以制作,且可以硅晶圆形式或面板形式进行。保护层的材料可为二氧化硅、三氧化二铝或氟聚合物。
基板材质包含环氧树脂型FR5、FR4、BT、PCB、玻璃、硅、陶瓷、合金或金属。Fe-Ni合金包含42%的Ni与58%的Fe。Fe-Ni-Co合金包含Kovar(29Ni%、17%Co、54%Fe)。
保护层材质包含硅高分子为基础的材质、高分子(polyimide)为基础的材质、硅胶、环氧树脂、弹性材质或感光材质。
附图说明
图1为本发明实施例中CIS-CSP影像传感器的示意图。
图2为本发明实施例中CIS-CSP影像传感器的示意图。
图3为本发明实施例中CIS-CSP影像传感器的示意图。
图4为本发明实施例中面板级封装制造方法的概要示意图。
图5为本发明实施例中CIS模块的示意图。
具体实施方式
本发明某些类似的实施例将不详细描述其细节。然而,应理解者为本发明中所有的较佳实施例仅为例示之用,并非用以限制,因此除文中的较佳实施例外,本发明亦可广泛地应用在其它实施例中。不同组件的构成间并不特别描述其尺寸,放大某些相关组件的维度并省略无意义部分,以明白叙述并强调本发明的内容。
本发明公开了一种PLP采用具有预设晶粒穿孔以及接触(内连接)穿孔于基板,接触金属垫位于基板上方,终端接触垫位于基板下方,透过穿孔内金属连接两者。复数穿孔穿过基板。接合导线连接形成影像传感器晶粒上的垫以及预设的接触金属垫。
如图1所示为本发明CIS-CSP(CMOS Image Sensor-Chip Scale Package)截面图。PLP封装结构包含基板2,其具有形成于其内的晶粒接收穿孔10以接收晶粒以及接触(内连)穿孔6。晶粒为影像感测晶粒。复数接触穿孔6自基板上侧穿透至下侧形成,其中接触穿孔形成于四周。导电材质填充于上述接触穿孔6中,以利于电性连络。导电终端垫8形成于基板下方,且与接触穿孔金属连接,接触垫22位于基板上侧,且与接触穿孔连接。终端导电30配置于基板底侧,以利于与外部装置接合。接合导线24连接于金属垫22及接合垫20之间,且因此透过接合垫与晶粒保持电性连接。厚介电层38例如硅高分子基础材质,形成于上表面除接合导线区域、微透镜、接触垫区域外,以利于黏合透明罩。核心材质(core paste)50填充进入晶粒边缘、晶粒背部、穿孔侧壁间的缝隙。透明罩利用黏胶置于晶粒与介电层之上产生一空隙介于透镜与透明罩之间。在一实施例中,介电层38包含硅高分子型、polyimide型、硅胶型、环氧树脂型、弹性材质、感光材质。具感旋光性的介电层38可通过涂布、印刷方法制作。
晶粒置于晶粒接收穿孔10内,以核心材质(core paste)50固定,最为保护晶粒背部的材质。核心材质(core paste)50可为化合物、环氧树脂、硅胶。晶粒穿孔的尺寸稍大于晶粒16,每边约为100微米。接触垫20由电镀方式制作于晶粒表面。核心材质50为弹性材质、感光材料、环氧树脂、硅胶填充进入晶粒边缘、晶粒背部、穿孔侧壁间的缝隙。此外、阻障层32利用电镀方式制作于基板的侧壁以利于黏合核心材质50。金属接合线24形成于晶粒16接合线24透过I/O垫20、接触垫22与晶粒16维持电性接触,以形成内连接结构与终端垫8接触。介电层38位于封装上部通过微影制程以产生预设图案(第三图虚线所示)。其可允许打开I/O垫20、接触垫22以利于接合线以及微透镜区域。图3所示为本发明CIS-CSP的俯视图,透明屏蔽36黏于介电层38以形成间隙与透明罩36与微透镜区域42之间。上述构成LGA(接触垫位于封装周边)型装。
须注意,开孔46形成于晶粒16与保护层40之间,用以曝露晶粒微透镜区域42,以利于CMOS-CIS。保护层40可以形成于微透镜区域42的微透镜上。保护层40形成于微透镜上,微透镜则配置于晶粒16方。保护层40具有防水防油特性以防止微透镜受到粒子污染,且最好具有0.1至0.3微米的厚度及接近1(空气反射系数)的反射系数。可以利用旋涂玻璃(SOG)技术予以制作,且可以硅晶圆形式或面板形式进行。保护层40的材料可为二氧化硅、三氧化二铝或氟聚合物。
最后,具有IR过滤膜的透明罩36形成于微透镜区域42上用以保护微透镜,其材质可为玻璃、石英等等。
另一实施例可参阅图2,导电凸块30制作于接触垫8下方,此型式称为BGA,以内连接接触穿孔6,以半球形位于切割道区域穿过基板。也可形成于内连穿孔侧壁区域,其余部分与第一图相仿。因此,不再赘述。接触穿孔6位于切割道区域,因此切割后,每一个封装具有半个接触穿孔6此可以提升锡接合质量以及减少所占面积(foot print)。基板材质可为具有预设开孔或alloy 42导线的FR5、FR4、BT、PCB基板。具有高玻璃转换温度的基板如环氧树脂型FR5、BT。金属合金基材的材质包含Fe-Ni合金包含42%的Ni与58%的Fe。Fe-Ni-Co合金包含Kovar(29Ni%、17%Co、54%Fe)。玻璃、陶瓷、硅基于低热膨胀系数可以被用来最为基板。
基板可以为矩形如面板形式尺寸适合于导线接合机。如第一与第二图所示,接合线由晶粒向外扇出,与接触垫22以及I/O垫20连接。与公知技术不同,公知技术具有多层迭层位于晶粒之上,也因此增加了封装的厚度。相反的,本发明终端垫8位于晶粒垫相反的表面,讯号传递的路径穿透基板通过内连结构引导至终端垫8。因此可以显著缩小本发明封装的厚度。本发明的封装可以远薄于先前技术。此外,本发明基板暂封装之前预先备置。晶粒穿孔10以及接触穿孔6预先制作。因此,产能将大幅提升,本发明公开一种无堆栈积层位于接合在线的PLP。
制作面板式的CIS的步骤包含涂布具有防水防油保护层,厚度约为0.1-0.3微米。然后固化该保护层。保护层以电浆(plasma)蚀刻或湿蚀刻,以穿孔罩幕作为屏蔽以形成接合垫区域。晶圆随后薄化,并分离晶粒,如通过于切割道上切割基板,以形成复数独立单元。切割道位于每一待分离单元之间。
随后,通过捡放装置将待加工的晶粒进行挑选并置于具有黏胶图案的制具上。具有晶粒、接触穿孔的基板随后黏合于制具之上。晶粒黏着材质如核心黏胶配置于介于晶粒与穿孔侧壁间缝隙,及晶粒背面。最后,“面板”自制具上分离。然后清理CIS芯片封装的主动面。
本发明中,厚介电层38形成于面板表面通过印刷或涂布形成黏着图案。最佳为光感式以产生一区域用以曝露出微透镜区域。需注意的是,厚介电层38环绕微透镜区域用以曝露出微透镜区域46、接合垫20区域以及接触垫22区域,因此,透明罩36可以保护微透镜防止污染。
图4a-图4e为制作CIS封装的步骤流程。本发明步骤包含提供定位工具(芯片分布工具)91,其具有定位图案位于其上。然后,图案胶(弹性黏着材质)印刷(涂布)于制具91上(用来黏合晶粒主动表面,未图示)。随后采用捡放微对位工具具有接合功能以分布良好晶粒,具有适当间距位于制具91上。图案胶会将晶粒黏着于制具91上,随后,具有晶粒穿孔、接触穿孔及接触垫位于基板上侧、终端垫位于基板下侧的基板置于制具91上,如图4a。导电材质填充于穿孔以利电性联系。之后,具有微透镜的晶粒98如图1、图2的晶粒随后以图案胶黏着于基板的晶粒接收穿孔之上。核心材质95形成于晶粒与侧壁间,与晶粒背面,随后将其固化,之后分离制具与面板。随后步骤为清洁晶粒表面与面板表面。以及热接合于支撑载具90上,如图4b。随后,涂布厚介电层38以及使用曝光显影制程以开启微透镜区域46、接合区域20、以及接触垫区域22,参考图3以及图4b。接合线然后形成以连接晶粒垫以及基板的接触垫,如图4c所示。CIS封装的晶粒主动表面随后被清洁,之后,与面板尺寸相当具有切割道的玻璃100接合于具有介电层38的面板,采用对位与真空接合技术。切割道以钻石切割器切割。厚介电层38随后固化以粘合玻璃与面板。面板支撑载具以真空固化技术后自面板分离。
自置放导电凸块或锡膏涂布于终端垫之后,执行回流程序以回流基板侧以形成导体球(BGA形式),之后执行测试。面板式最终测试采用垂直探针方式测试。测试后,面板将备置于蓝带(blue tape)上并自终端金属侧切割面板,其只切割自基板底部切割基板。然后,自切割道将玻璃以外力折裂以分离独立单体,如图4e所示。然后,封装各自被捡放于托盘或卷带上。
参阅图5,所示为CIS封装单体,以CIS-CSP制程制作。晶粒包含CMOS或CCD影像传感器,其终端垫30通过连接器124接至(表面黏着技术)软性电路板120的连接垫,以联系母板。CIS-CSP116为图1、图2的单体。然后,透镜128置于透明罩上使得光可以穿透。同时,微透镜可以形成于微透镜区域,间隙形成于晶粒16与透明罩36之间。透镜支撑器126固定于印刷电路板120之上,以支撑透镜128。滤片130如IR滤光片固定于支撑器126之上。同理,滤片可以为滤膜、形成于透明罩的上侧或下侧。IR滤片包含二氧化钛或光CATALYZER组成。透明罩36可以防止微透镜污染。使用者可以采用液态或气态去除污染微粒而不伤及微透镜。此外,被动组件122可以置于印刷电路板120之上
本发明的有益效果包含:基板预设穿孔以及电路,以利于形成超薄封装,厚度小于200微米(自传感器表面)。可作为应力释放缓冲区域,通过填入硅胶、或液态化合材料以降低热应力,其因介于硅(CTE 2.3)与基板(FR5/BT-CTE-16)间热膨胀系数不匹配所产生的问题。基于采用简易制程,封装产能得以提升:晶粒接合、导线接合、保护层以及切割。基于影像传感器较少的接脚数。终端垫置于与主动面的反侧,晶粒配置方法与目前制程兼容,制程过程中无污染,基于具有一玻璃罩配置于晶圆上。晶粒与基板的表面均等,本封装可被清洁,基于具有玻璃罩位于透镜上。芯片尺寸约为每边0.5厘米,封装的信赖度较传统佳。特别是可以做板级温度循环测试,主要基于基板与PCB母板热膨涨系数相当,不会导致应力施加于球体。成本低廉且制程简易。全程可采自动化制程且采表面黏着技术。易制作混式封装。LGA形式具有边缘终端垫以利表面黏着。其具有高良率以及无微粒污染、制程简易以及全自动化制程。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应所述以权利要求的保护范围为准。

Claims (10)

1.一种影像传感器,包含基材,其特征在于,该基材具有晶粒穿孔以及接触穿孔形成于其中,终端垫形成于所述的接触穿孔之下侧以及接触垫配置于该基板的上表面;
影像传感器晶粒,置于该晶粒穿孔中,其中该影像传感器晶粒具有微透镜区域;
介电层,形成于该晶粒以及该基板之上,并露出该微透镜区域、接合垫区域以及接触垫区域;
接合导线,形成于该晶粒与该基板之上,用以耦合该晶粒以及接触垫;
核心材质,填充于该晶粒与该晶粒穿孔侧壁之间,以及该晶粒背面;及
透明罩,配置于该晶粒以及该介电层之上,且产生一间隙位于该透明罩与该微透镜之间。
2.根据权利要求1所述的影像传感器,其特征在于,还包含导电凸块耦合所述的终端垫。
3.根据权利要求1所述的影像传感器,其特征在于,还包含阻障层形成于所述的晶粒穿孔的侧壁。
4.根据权利要求1所述的影像传感器,其特征在于,还包含保护层形成于所述的微透镜区域以避免微粒污染。
5.根据权利要求4所述的影像传感器,其特征在于,所述的保护层材质包含二氧化硅、三氧化二铝或氟聚合物。
6.一种制作影像传感器的方法,包含一基材,其特征在于,提供该基材置于一制具上,所述的基板具有晶粒穿孔以及接触穿孔形成于其中,终端垫形成于接触穿孔的下侧以及接触垫配置于该基板的上表面;
使用为对位检放系统重分布已知良好传感器晶粒于该制具上;
填充核心材质于该晶粒、晶粒穿孔侧壁之间,以及该晶粒背面并分离该制具;
形成介电层于该晶粒以及该基板之上,并露出该微透镜区域、接合垫区域以及接触垫区域;
形成接合导线于该晶粒与该基板之上,用以耦合该晶粒以及接触垫;
接合透明罩于一面板上,其位于该介电层之上;
自终端金属侧切割该面板;以及
延着切割道分离该透明罩以形成封装单体。
7.根据权利要求6所述的制作影像传感器的方法,其特征在于,还包含制作保护层于该微透镜区域以保护微透镜以防粒子污染。
8.根据权利要求6所述的制作影像传感器的方法,其特征在于,还包含印刷锡膏于该终端垫以及加热该锡膏以形成导电凸块。
9.一种影像传感器模块,包含软性电路板,其特征在于,该软性电路板具有电路、接触垫、连接器形成其中;
锡膏接合该连接垫以及基板终端垫;
其中所述的基板,具有晶粒穿孔以及接触穿孔形成于其中,终端垫形成于所述的接触穿孔的下侧以及接触垫配置于该基板的上表面;
影像传感器晶粒,置于所述的晶粒穿孔中,其中所述的影像传感器晶粒具有微透镜区域;
介电层,形成于所述的晶粒以及该基板之上,并露出该微透镜区域、接合垫区域以及接触垫区域;
接合导线,形成于所述的晶粒与该基板之上,用以耦合该晶粒以及接触垫;
核心材质,填充于所述的晶粒与所述的晶粒穿孔侧壁之间,以及该晶粒背面;
透明罩,配置于所述的晶粒以及该介电层之上,且产生一间隙位于该透明罩与该微透镜之间;及
透镜支撑架,固定于该软性电路板上,使光得以穿过该微透镜。
10.根据权利要求9所述的影像传感器模块,其特征在于,还包含被动组件焊于所述的软性电路板上。
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Cited By (10)

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Publication number Priority date Publication date Assignee Title
CN102593116A (zh) * 2011-01-12 2012-07-18 陈淑姿 薄化的影像撷取模组及其制作方法
CN102034768B (zh) * 2008-09-25 2012-09-05 金龙国际公司 具有晶粒埋入式以及双面覆盖重增层的基板结构及其方法
CN103219253A (zh) * 2012-01-20 2013-07-24 东琳精密股份有限公司 芯片尺寸封装结构及其芯片尺寸封装方法
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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100794660B1 (ko) * 2006-07-14 2008-01-14 삼성전자주식회사 이미지 센서 패키지 및 그 제조 방법
US7964945B2 (en) * 2007-09-28 2011-06-21 Samsung Electro-Mechanics Co., Ltd. Glass cap molding package, manufacturing method thereof and camera module
US8912654B2 (en) * 2008-04-11 2014-12-16 Qimonda Ag Semiconductor chip with integrated via
US8004602B2 (en) * 2008-05-16 2011-08-23 Kingpak Technology Inc. Image sensor structure and integrated lens module thereof
TW200952142A (en) * 2008-06-13 2009-12-16 Phoenix Prec Technology Corp Package substrate having embedded semiconductor chip and fabrication method thereof
JP5264332B2 (ja) * 2008-07-09 2013-08-14 ラピスセミコンダクタ株式会社 接合ウエハ、その製造方法、及び半導体装置の製造方法
TWI474447B (zh) * 2009-06-29 2015-02-21 Advanced Semiconductor Eng 半導體封裝結構及其封裝方法
TWM382505U (en) * 2010-01-15 2010-06-11 Cheng Uei Prec Ind Co Ltd Video device
US20110221018A1 (en) * 2010-03-15 2011-09-15 Xunqing Shi Electronic Device Package and Methods of Manufacturing an Electronic Device Package
US8460971B2 (en) * 2010-05-06 2013-06-11 Ineffable Cellular Limited Liability Company Semiconductor device packaging structure and packaging method
CN102254834B (zh) * 2010-05-18 2016-04-27 异基因开发有限责任公司 半导体封装结构与方法
US20120098080A1 (en) * 2010-10-26 2012-04-26 Jabil Circuit, Inc Method and package for an electro-optical semiconductor device
EP2575175B1 (de) * 2011-09-30 2017-04-26 First Sensor Microelectronic Packaging GmbH Bildsensor mit großer Chipfläche
TWI482271B (zh) * 2011-11-04 2015-04-21 King Dragon Internat Inc 一種具有雙層基板之影像感測器封裝結構及方法
CN103378016A (zh) * 2012-04-28 2013-10-30 鸿富锦精密工业(深圳)有限公司 芯片组装结构、芯片组装方法及光纤耦合模块
US8921759B2 (en) * 2012-07-26 2014-12-30 Optiz, Inc. Integrated image sensor package with liquid crystal lens
CN205453874U (zh) * 2013-03-07 2016-08-10 株式会社村田制作所 相机模块及电子设备
US9219091B2 (en) 2013-03-12 2015-12-22 Optiz, Inc. Low profile sensor module and method of making same
CN104051489B (zh) * 2013-03-12 2017-09-08 奥普蒂兹公司 小轮廓图像传感器
JP2014187160A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 固体撮像装置および携帯情報端末
KR20140126598A (ko) * 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9111846B1 (en) * 2014-04-16 2015-08-18 Gloval Unichip Corp. Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
CN105261602A (zh) 2015-09-16 2016-01-20 京东方科技集团股份有限公司 一种显示面板的封装结构、转接板、封装方法及显示装置
US9769398B2 (en) 2016-01-06 2017-09-19 Microsoft Technology Licensing, Llc Image sensor with large-area global shutter contact
US20170333700A1 (en) * 2016-02-22 2017-11-23 The Charles Stark Draper Laboratory, Inc. Method of manufacturing an implantable neural electrode interface platform
US10103191B2 (en) * 2017-01-16 2018-10-16 Semiconductor Components Industries, Llc Semiconductor die and method of packaging multi-die with image sensor
US10276441B2 (en) 2017-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Protected chip-scale package (CSP) pad structure
US10763293B2 (en) * 2017-11-29 2020-09-01 China Wafer Level Csp Co., Ltd. Image sensing chip package and image sensing chip packaging method
US11037970B2 (en) 2018-11-01 2021-06-15 Semiconductor Components Industries, Llc Semiconductor package structure and related methods
US11252821B2 (en) * 2019-08-13 2022-02-15 CoreLed Systems, LLC Optical surface-mount devices
JP2021093429A (ja) * 2019-12-09 2021-06-17 ソニーセミコンダクタソリューションズ株式会社 撮像素子パッケージおよび撮像素子パッケージの製造方法
TWI766296B (zh) * 2020-06-18 2022-06-01 勝麗國際股份有限公司 感測器封裝結構
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US11584638B2 (en) * 2020-07-30 2023-02-21 Invensense, Inc. Reducing delamination in sensor package
US11837518B2 (en) * 2020-08-26 2023-12-05 Texas Instruments Incorporated Coated semiconductor dies
TWI800793B (zh) * 2021-02-08 2023-05-01 同欣電子工業股份有限公司 感測器封裝結構
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WO2017140138A1 (zh) * 2016-02-17 2017-08-24 上海伊诺尔信息技术有限公司 芯片的超薄嵌入式封装方法及封装体
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US11297210B2 (en) 2018-01-30 2022-04-05 Vivo Mobile Communication Co., Ltd. Camera module, method for assembling camera module, and mobile terminal
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