CN101312203A - 具有晶粒接收开孔之芯片尺寸影像传感器及其制造方法 - Google Patents

具有晶粒接收开孔之芯片尺寸影像传感器及其制造方法 Download PDF

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CN101312203A
CN101312203A CNA2008100974018A CN200810097401A CN101312203A CN 101312203 A CN101312203 A CN 101312203A CN A2008100974018 A CNA2008100974018 A CN A2008100974018A CN 200810097401 A CN200810097401 A CN 200810097401A CN 101312203 A CN101312203 A CN 101312203A
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crystal grain
substrate
layer
perforation
encapsulation
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杨文焜
张瑞贤
许献文
林殿方
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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  • Solid State Image Pick-Up Elements (AREA)
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Abstract

本发明提供的封装结构包含：基板，具有晶粒接收穿孔、接触穿孔及第一接触垫；晶粒，置于晶粒接收穿孔中，其中晶粒具有微透镜区域。透明盖覆盖微透镜区域。周围材质，形成于晶粒之下并填充进入晶粒与晶粒接收穿孔侧壁间的缝隙。介电层，形成于晶粒以及基板之上。重分布层，形成于介电层上用以耦接第一接触垫。保护层，形成于重分布层上。第二接触垫，形成于基板下表面及接触穿孔之下。以及，透明基底，形成于保护层之上。

Description

具有晶粒接收开孔之芯片尺寸影像传感器及其制造方法
技术领域
本发明涉及晶圆级封装(wafer level package；WLP)结构，尤其涉及具有晶粒接收穿孔与内联机穿孔的基板以提升可靠度以及降低组件尺寸的扩散型(fan-out)晶圆级封装。
背景技术
半导体技术快速发展，且半导体晶粒密度提升以及微小化的趋势。也因此对于如此高密度的封装技术及内联机技术也提升以适用上述的状态。传统的覆晶结构中，锡球数组形成于晶粒的表面，透过传统的锡膏藉由锡球罩幕制作以形成所欲的图案。封装功能包含散热、讯号传输、电源分配、保护等，当芯片更加复杂，传统的封装如导线架封装、软式封装、刚性封装、无法满足高密度小尺寸芯片的需求。
再者，由于一般封装技术必须先将晶圆上的晶粒分割为个别晶粒，再将晶粒分别封装，因此上述技术的制程十分费时。因为晶粒封装技术与集成电路的发展有密切关联，因此封装技术对于电子组件的尺寸要求越来越高。基于上述的理由，现今的封装技术已逐渐趋向采用球门阵列封装(BGA)、覆晶球门阵列封装、芯片尺寸封装、晶圆级封装的技术。应可理解晶圆级封装(WLP)指晶圆上所有封装及交互连接结构，如同其它制程步骤，系于切割为个别晶粒之前进行。一般而言，在完成所有配装制程或封装制程之后，由具有复数半导体晶粒的晶圆中将个别半导体封装分离。上述晶圆级封装具有极小的尺寸及良好的电性。
晶圆级封装(WLP)技术系为高级封装技术，藉其晶粒系于晶圆上加以制造及测试，且接着藉切割而分离以用于在表面黏着生产线中组装。因晶圆级封装技术利用整个晶圆作为目标，而非利用单一芯片或晶粒，因此于进行分离程序之前，封装及测试皆已完成。此外，晶圆级封装(WLP)系如此的高级技术，因此打线接合、晶粒黏着及底部填充的程序可予以省略。藉利用晶圆级封装技术，可减少成本及制造时间且晶圆级封装的最后结构尺寸可相当于晶粒大小，故此技术可满足电子装置的微型化需求。
虽晶圆级封装技术具有上述优点，然而仍存在一些影响晶圆级封装技术接受度的问题。例如，虽利用晶圆级封装技术可减少集成电路与互连基板间的热膨胀系数(CTE)不匹配，然而当组件尺寸缩小，晶圆级封装结构的材料间的热膨胀系数差异变为另一造成结构的机械不稳定的关键因素。美国第6,271,469号专利所揭露的封装结构即具有热膨胀系数(CTE)不匹配的问题。其系由于现有技术中利用铸模化合物封装硅晶粒所造成。硅材料的热膨胀系数约为2.3，而铸模化合物的热膨胀系数约为40～80。由于固化化合物及介电层材料的温度较高，导致芯片所配置的位置偏移以及内连接垫偏移，结果造成良率及效能的问题。温度循环期间难以回复到原来的位置(若固化温度接近或超过转移温度Tg，则环氧树脂性质造成此现象)。亦即传统封装结构不能大尺寸制作，其将造成较高的制作成本。
再者，某些技术涉及晶粒的使用直接形成于基板上表面上。众所周知，形成于半导体晶粒上的数个接合垫系透过包含重分布层(RDL)的重分布制程予以重分布进入数个区域数组形式的金属垫。一般而言，所有经堆栈的重分布层系形成于晶粒上的增层上。增层将增加封装大小。封装厚度因此增加。其可能与缩小芯片尺寸的需求相抵触。
此外，现有技术经由复杂程序使其得以形成面板型态封装。其需要铸模工具以压合及注入铸模材料。由于其需热固化该铸模材料，却因此可能导致翘曲而使得晶粒表面与铸模材料难以达到同一水平的需求，以及需要以化学机械研磨方法研磨不平的表面，因此亦难以节省制造成本。
因此，本发明提出一种扩散型晶圆级封装(FO-WLP)结构，具有良好的热膨胀系数性能及缩小化尺寸，克服上述封装问题以及提供较佳板级热循环可靠度测试。
发明内容
本发明目的在于提供具有优良热膨胀系数(CTE)效能以及缩小化尺寸的扩散型晶圆级封装。
本发明另一目的在于提供具有晶粒接收穿孔与接触穿孔的基板以提升可靠度以及降低组件尺寸的扩散型晶圆级封装。
本发明再一目的在于提供具有透明基板(玻璃)覆盖微透镜区域以进一步保护微透镜的CIS-CSP(CMOS Image Sensor-Chip Scale Package)。
本发明提供的封装包含具有晶粒接收穿孔、接触穿孔以及第一接触焊垫的基板。具微透镜区域的晶粒系配置于晶粒接收穿孔内。透明罩覆盖微透镜区域。周围材质(surrounding paste)填充进入晶粒与晶粒接收穿孔侧壁间的缝隙及晶粒底部。介电层形成于上述晶粒以及基板之上。重分布层(RDL)形成于介电层上并耦接第一接触焊垫。保护层形成于重分布层上。第二接触焊垫形成于基板下表面及接触穿孔之下。透明基底形成于保护层之上。
基板材质包含环氧树脂型FR5、FR4、BT、PCB、玻璃、硅或陶瓷。此外，基板材质亦包含合金或金属，较佳地系基板热膨胀系数接近母基板热膨胀系数大约16至20。介电层材质包含弹性介电层、感光材质、硅橡胶介电层为基础的材质、高分子(poly imide)为基础的材质、硅胶(SINR)、弹性材质或硅树脂材质。
本发明实施例封装结构具有下述的优点：本发明BGA或LGA封装结构可以防止微透镜受到粒子污染。此外，CMOS/CCD影像传感器封装模块结构可以直接清理以移除粒子污染。本发明BGA或LGA封装结构的制作程序相当简单。
本发明揭露一种制作半导体组件封装的方法，包含：提供一基板，该基板具有晶粒接收穿孔、接触穿孔以及第一接触焊垫形成于其中；印刷图案胶于晶粒重分布制具(具有对位图案)；使用对位检放系统重分布具有微透镜区域的复数已知良好晶粒于晶粒重分布制具上，且使其保持所需间距；黏着基板至晶粒重分布制具上；填充核心材质(最好为弹性材料)于该晶粒与晶粒穿孔侧壁之间以及该晶粒背面；分离晶粒重分布制具以形成面板(panel)；形成介电层于该晶粒主动表面以及该基板的上表面；并于该介电层形成开口以裸露微透镜、晶粒接触垫区域；形成至少一导电增层(built up layer)于介电层上；形成接触结构于至少一导电增层上；制作保护层于至少一导电增层上；裸露微透镜区域；附着(真空接合)透明基底于保护层上并固化(curing)保护层以粘附透明基板；切割含线的该透明基底以定义透明基底上的覆盖区域；贴附(mounting)具透明基板区域的面板于(框型)蓝带(blue tape)上；自基板(面板)下表面切割该基板至透明基板的表面或其表面之前；使用打孔器(puncher)分裂透明基底；自蓝带移除该芯片尺寸封装体并置放于盘上。
本发明实施例半导体组件封装的方法的优点包含：形成面板式晶圆型态的方法简易，并且容易控制面板表面的粗糙度。面板厚度容易控制，制作期间晶粒偏移问题得到解决。省略铸模制具，亦无需化学机械研磨制程。藉由晶圆级封装制程使得面板晶圆制作容易。
附图说明
图1为本发明实施例扩散型晶圆级封装结构(LGA型态)的剖面示意图；
图1A为本发明实施例微透镜结构的剖面示意图；
图2为本发明实施例扩散型晶圆级封装结构(BGA型态)的剖面示意图；
图3为本发明实施例基板的剖面示意图；
图4为本发明实施例基板及玻璃载具结合的剖面示意图；
图5为本发明实施例基板的上视图；
图6为本发明实施例CIS模块的剖面示意图；
图7为本发明实施例玻璃附着于带上的示意图；
图8为本发明实施例制作流程的示意图。
【主要组件符号说明】
基板2；终端金属接触垫3；晶粒接收穿孔4；晶粒6；接触垫10；介电层12；重分布层14；第二终端接触导电垫18；导电凸块(球)20；核心材质21；接触穿孔22；导电层24；保护层26；切割线28；制具40；附着材料42；边缘区域50；微透镜区域60；第二保护层62；透明基底68；透镜架70；印刷电路板72；导线74；接触金属垫75；连接器76；透镜78；被动组件80；滤波器82；组件封装100；基板200；玻璃202；切割线204；覆盖区域206。
具体实施方式
本发明某些类似的实施例将不详细描述其细节。然而，应理解者为本发明中所有的较佳实施例仅为例示之用，并非用以限制，因此除文中的较佳实施例外，本发明亦可广泛地应用在其它实施例中。不同组件的构成间并不特别描述其尺寸，放大某些相关组件的维度并省略无意义部分，使叙述明白并强调本发明的内容。
本发明揭露一种扩散型WLP采用具有预设终端金属接触垫3以及已形成晶粒接收穿孔4于其上的基板2。晶粒配置于基板2的晶粒接收穿孔4内并附着于核心材质(core paste)上，举例而言，弹性核心材质填入晶粒边缘以及基板的晶粒接收穿孔侧壁之间，及/或晶粒之下。感光材质涂布于晶粒以及已预制基板(包含核心材质区域)上。感光材质的材料最好由弹性材质形成。
图1显示为根据本发明第一实施例的扩散型晶圆级封装截面图。如图1所示，扩散型晶圆级封装结构包含基板(有机基板)2，其具有形成于其内的晶粒接收穿孔4以接收晶粒6以及第一终端接触导电垫3。复数晶粒接收穿孔4自基板上表面穿透至下表面形成。其中晶粒接收穿孔4预先形成于基板之内。核心材质21透过真空印刷或涂布于晶粒6下表面之下，并封住晶粒6。核心材质21亦可填充进入晶粒6边缘、穿孔4侧壁间的缝隙。导电层(金属)24可以选择性地涂布于晶粒接收穿孔4侧壁上以提升晶粒6与基板2之间附着力。
晶粒6置于基板2上的晶粒接收穿孔4内。接触垫(焊垫)10形成于晶粒6之上。感光层或介电层12形成于晶粒6之上以及基板的上表面。复数个开孔藉由微影制程或曝光及显影程序而形成于介电层12之中。上述复数个开孔分别对准接触垫(I/0垫)10及基板上表面之上的第一终端接触导电垫3。重分布层14，亦称为导电线14，藉由移除部份所选定的介电层12上的金属层而形成于介电层12上，其中重分布层14透过I/O垫10及第一终端接触导电垫3保持电性连接晶粒6。基板2还包含接触穿孔22形成于基板2中。第一终端接触导电垫3形成于接触穿孔22上。导电材料填充进入接触穿孔22以利于电性连接。第二终端接触导电垫18形成于基板2的下表面及接触穿孔22下方，并连接基板的第一终端接触导电垫3。切割线28定义于封装单元之间以利于分离每一个封装单元，为了较佳的切割质量可以选择切割在线无介电层存在。保护层26用于覆盖重分布层14。
须注意，晶粒6包含微透镜区域60形成于晶粒6上。微透镜区域60具有第二保护层62形成于其中，请参考图1A，第二保护层62系藉由涂布制程所形成，第二保护层62具有防水及防油的性质以保护制作过程中受到粒子污染。
介电层12及核心材质21作为缓冲区域，基于介电层12具有弹性使得于热循环期间缓冲区域得以吸收晶粒6及基板2间的热机械应力。上述结构构成LGA(接触垫位于封装周边)型封装。
透明基底68，例如玻璃盖，形成于保护层26上以覆盖微透镜区域60上的第二保护层62，结果产生透明基底68及微透镜区域60间的间隙(凹洞)。透明基底68可以与封装体尺寸(所占面积(foot print))相同或者比封装体(基板切割后)尺寸稍大。保护层62较佳为弹性材料以利于附着至透明基底68。
如图2所示另一实施例中，导电凸块(球)20形成于第二终端接触导电垫18上，此型式称为BGA型态，其中接触穿孔22位于基板边缘区域中。其它部份类似图1，因此详细描述省略之。在BGA结构的情况之下，终端导电垫18可以作为球下金属(UBM)。复数接触导电垫3形成于基板2上表面上及重分布层14之下。
基板2材质可为有机基板，例如具有预设开孔的环氧型态FR5、BT、PCB基板或电路蚀刻前的铜金属。其热膨胀系数最好与母板(PCB)之丨相同。具有高玻璃转换温度(Tg)的有机基板为环氧型态FR5或BT(Bismaleimide Triazine)型态基板；铜金属(热膨胀系数大约16)亦可以使用；玻璃、陶瓷以及硅亦可以作为基板。弹性核心材质可以藉由硅橡胶或树脂弹性材质形成。
基板可以为圆型态例如晶圆型态，其直径例如为200、300微米或更大；或者是长方形形态例如面板形式。基板2可以预制具有晶粒接收穿孔4。切割线28定义于封装单元之间以利于分离每一个封装单元。请参照图3，其显示基板2包含复数预制晶粒接收穿孔4以及接触穿孔22。导电材质填充进入接触穿孔22中，结果构成接触穿孔结构。
在本发明一实施例中，介电层12较佳为弹性介电层，其可以由硅介电基础材料所制成，包含SINR、Dow Corning公司所制造WL 5000系列或者是其组合物。在另一实施例中，介电层可以由PI(polimides)或硅橡胶材料制成。此外，为了简化制程可以利用感光层。
在本发明的一实施例中，弹性介电层系一种热膨胀系数大于100(ppm/℃)、延伸率大约40百分比(较佳为30～50百分比)以及硬度介于塑料与橡胶之间的材质。弹性介电层12厚度端视温度循环测试期间累积于重分布层与介电层之界面间的应力而定。
图4显示提供(玻璃或铜面积层板)载具及基板之制具40。附着材料42例如暂时附着材料形成于制具40周边区域处。在此例子中，制具可以藉由具面板形式之玻璃或铜面积层板(Copper Clad Laminate)构成。基板边缘无接触穿孔结构形成于其中。图4的底下部分图示制具与基板之组合。面板与(玻璃或铜面积层板)载具黏合，制作期间该载具可以黏住及支撑面板。
图5显示具有晶粒接收穿孔4的基板的上视图。基板的边缘区域50无接触穿孔结构，该区域系于晶圆级封装制作期间用于黏住或附着(玻璃或铜面积层板)载具。晶圆级封装制作完成之后，基板2将从(玻璃或铜面积层板)载具沿着记号线(dot line)切割(释放)，亦即记号线的内部区域将进行切割程序以分离封装体。
请参照图6，前述的组件封装可以整合至具有透镜架70的CIS模块中，该透镜架置于具有导线74的印刷电路板72上。连接器76形成于印刷电路板72的一端。印刷电路板72最好包括软性印刷电路板(FPC)。组件封装100透过印刷电路板上的接触金属垫75而形成于印刷电路板72上，其系透过于透镜架70内藉由表面黏着制程(SMT)中利用焊接(膏或球)而成。透镜78形成于透镜架70的最上方，红外线滤波器82可选择性地配置于透镜架70之内及组件100与透镜之间。至少一被动组件80可以形成于透镜架70内的印刷电路板上，或者形成于透镜架70外部。
硅晶粒(热膨胀系数大约2.3)被封装于封装体之内。FR5或BT有机环氧型态材料(热膨胀系数大约16)用于作为基板，其热膨胀系数与印刷电路板或母板(mother board)相同。晶粒及基板之间的空间(空隙)填入填充材料(较佳为弹性核心材质)以吸收(晶粒与环氧型态FR5/BT间)由于热膨胀系数不匹配所产生的热机械应力。再者，介电层12包括弹性材料以吸收晶粒垫及印刷电路板之间的应力。重分布层金属为铜/金材料，其热膨胀系数与印刷电路板及有机基板相同约为16；接触凸块的UBM结构18位于基板的终端接触金属垫3之下。印刷电路板的金属区块为铜组合金属，铜的热膨胀系数约为16以匹配任一印刷电路板。从以上叙述，本发明可以提供优良的热膨胀系数(X/Y方向完全匹配)以解决晶圆级封装的问题。
很显然地，于增层结构(印刷电路板及基板)下的热膨胀系数匹配问题藉由本发明方法解决，其提供更佳的可靠度(基板于印刷电路板期间，其终端垫于X/Y方向无热应力)，并且弹性介电层用于吸收Z方向的应力。芯片边缘与基板穿孔的侧壁之间的空间(空隙)可以填入弹性介电材料以吸收机械/热应力。
在本发明的一实施例中，重分布层的材料包括钛/铜/金合金或钛/铜/镍/金合金，重分布层的厚度为2至15微米之间。钛/铜合金藉由溅镀技术形成以作为种子金属层，铜/金或铜/镍/金合金可以藉由电镀形成，利用电镀制程以形成重分布层可以使得重分布层有足够厚度及较好的机械性质以解消热循环期间造成的热膨胀系数不匹配。金属垫可以为铝或铜或其组合物。若扩散型晶圆级封装结构利用SINR作为弹性介电层以及铜作为重分布层，根据应力分析(此处不显示)，累积于重分布层/介电层界面的应力可以降低。
如图1及图2所示，重分布层从晶粒扩散出，并且沟通朝向向下的第二终端垫。与现有技术不同之处在于晶粒6被接收于基板的预制晶粒接收穿孔之内，结果降低了晶粒封装体的厚度。现有技术违反了降低晶粒封装体厚度的规则。本发明的封装体将比现有技术者更薄。再者，基板系于封装之前预制。穿孔4系预先决定。因此，生产量将比以前提升改善。本发明提供了降低厚度以及好的热膨胀系数匹配效能的扩散型WLP。
本发明包括预备一基板(最好是有机基板FR4/FR5/BT)及接触金属垫形成于上表面上。晶粒接收穿孔的形成大小大于晶粒大小加上100微米/边，其深度与晶粒厚度相同(或比其厚大约25微米)。
微透镜的保护层形成于预制硅晶圆上，其可以避免粒子污染以提升扩散型WLP制程的良率。下一步骤系藉由背面研磨以研磨晶圆至所要求的厚度。晶圆引进切割程序以分离晶粒。
之后，本发明的方法包括提供具有对准图案形成于其上的晶粒重分布(对位)制具。然后，图案胶印制于制具上(以粘合晶粒及基板表面)，接着利用具覆晶功能的检放微对位系统以重分布已知良好晶粒于具有已知间距的制具上。图案胶黏着芯片(主动表面边)至重分布制具上。随后，基板(具有晶粒接收穿孔)黏附至制具上(藉由图案胶黏着)，接着印刷弹性核心材质于基板(FR5/BT)穿孔侧壁及晶粒背面与晶粒之间的空间(空隙)上。最好保持核心材质表面与基板于相同高度。之后，利用固化制程以固化核心材料及利用黏着材料以黏着(玻璃或CCL)载具。利用面板黏(贴)附机以黏着基座至基板及晶粒背面上。执行真空黏附，然后制具从面板晶圆分离。
一旦晶粒重分布于基板(面板基础)上，然后藉由湿式及/或干式清洁以执行清洁程序而清洁晶粒表面。接下来，涂布介电材料于面板表面。随后，执行微影制程以开孔导通层(接触金属垫)、铝焊垫及微透镜区域或切割线(选择性)。之后，执行电浆清除步骤以清洁导通洞与铝焊垫表面。接下来，溅镀钛/铜作为种子金属层，然后涂布光阻层于介电层与种子金属层上以形成重分布金属层图案。之后，执行电镀制程以形成铜/金或铜/镍/金作为重分布金属，然后去除光阻及金属湿式蚀刻以形成重分布金属导线。接下来步骤，涂布或印刷上部介电层及开孔于微透镜区域或切割线(选择性)。
微透镜区域可以暴露于介电层形成之后及保护层形成之后。
本发明提供无需利用微影制程以形成透明基底(玻璃)的方法，例如图1与图2的玻璃盖68。请参照图7及图8，玻璃利用具有约50微米对位精准度的面板黏附机(于真空情况)以黏着玻璃与面板。该制程最好藉由真空接合方法执行，因此产生开孔，请参照步骤300。玻璃202可以为圆形或方形型态。玻璃可以选择性地涂布红外线涂层，其厚度约为50-200微米。
在图8的步骤305中，该步骤系划线玻璃202使其具切割线204于玻璃上，如图7所示。由水平线及垂直线构成的切割线形成棋盘图案，结果藉由每一切割线形成覆盖区域206。
然后，在步骤310中，印刷植球或焊膏于第二接触金属18上，执行热回流程序以回流锡球边上(对于BGA型态)。然后执行测试。藉由垂直式或环氧型探针卡接触金属导通层(via)以执行晶圆级面板最终测试。测试之后，在步骤315中，贴附面板(具有透明基底-玻璃)于蓝带框型上，基板200从下表面进行切割以分离基板为个别单元。
在步骤320中，藉由橡胶打孔机或滚筒从基板下表面分裂玻璃。接着，在步骤325中，分别检放封装体的封装单元于盘子、胶带或卷筒上。
在个别CIS封装模块中，具有透明基底的感应组件封装体附着于扩散型晶圆级封装的上表面上，并且藉由表面黏着技术(SMT)将封装体焊接于印刷电路板上。透镜架可以固定于印刷电路板上以支撑透镜。滤波器，例如IR滤光片(CART)，固定于透镜架上。另一方面，滤波器可以包括滤波层，例如IR滤波膜，形成于玻璃上或下表面以作为滤波器。在一实施例中，IR滤波膜包括二氧化钛、光触媒。玻璃可以防止微透镜受到粒子污染。使用者可以利用液体或吹气方式以移除玻璃上的粒子而不会损害微透镜。
根据本发明，前述封装结构具有下述的优点：本发明BGA或LGA封装结构可以防止微透镜受到粒子污染。此外，CMOS/CCD影像传感器封装模块结构可以直接清理以移除粒子污染。本发明BGA或LGA封装结构的制作程序相当简单。
本发明的优点包含：
形成面板式晶圆型态的方法简易，并且容易控制面板表面的粗糙度。面板厚度容易控制，制作期间晶粒偏移问题得到解决。省略铸模制具，亦无需化学机械研磨制程。藉由晶圆级封装制程使得面板晶圆制作容易。
基板预设晶粒接收穿孔、内连接穿孔及终端接触金属垫(对于有机基板)；穿孔大小约等于晶粒大小加上约100微米/边；藉由填入核心材质作为缓冲区域以吸收硅晶粒及基板(FR5/BT)间的热膨胀系数不匹配所产生热应力；由于应用简单的增层形成于晶粒上表面使得封装产能得以提升(制作时间缩短)；终端垫形成于晶粒主动表面的对边上。
晶粒置放方式与之前的方法相同。弹性核心材质(树脂、环氧化合物、硅胶等)填入晶粒边缘及穿孔侧壁间的空间，然后应用真空热固化使其作为本发明热应力缓冲层。面板形式制作期间，热膨胀系数不匹配所产生的问题得以克服(利用匹配的热膨胀系数及接近基板的载具)。仅有硅橡胶介电材料(最好为SINR)涂布于主动表面上及基板(最好为FR4或BT)表面上。利用光罩制程以开孔接触垫，基于介电层(SINR)为光敏感层因此得以打开接触开孔。晶粒及基板利用载具彼此贴附。封装及板级的可靠度较传统佳，特别是可以做板级温度循环测试，主要基于基板与PCB母板热膨涨系数相当，不会导致应力施加于球体。板上温度循环测试期间，失效模式(焊接球破裂)不明显。成本低廉且制程简易。易制作多芯片封装。
对熟悉此领域技艺者，本发明虽以较佳实例阐明如上，然其并非用以限定本发明的精神。在不脱离本发明的精神与范围内所作的修改与类似的配置，均应包含在下述的申请专利范围内，此范围应覆盖所有类似修改与类似结构，且应做最宽广的诠释。

Claims (10)

1.一种半导体组件封装结构，包含基板，其特征在于该基板具有晶粒接收穿孔、接触穿孔及第一接触垫；
晶粒，置于该晶粒接收穿孔中，其中该晶粒具有微透镜区域；
周围材质，形成于该晶粒之下并填充进入该晶粒与该晶粒接收穿孔侧壁间的缝隙；
介电层，形成于该晶粒以及该基板之上，并露出该微透镜区域以及该第一接触垫；
重分布层，形成于该介电层上用以耦接该第一接触垫；
保护层，形成于该重分布层上；
第二接触垫，形成于该基板下表面及该接触穿孔之下；以及
透明基底，形成于该保护层之上。
2.如权利要求1所述的半导体组件封装结构，其特征在于还包含导电凸块耦合该第二接触垫。
3.如权利要求1所述的半导体组件封装结构，其特征在于该基板材质包含环氧树脂型FR5或FR4、BT、PCB、玻璃、硅、陶瓷、合金或金属。
4.如权利要求1所述的半导体组件封装结构，其特征在于还包含第二保护层形成于该微透镜区域上。
5.如权利要求1所述的半导体组件封装结构，其特征在于该半导体组件封装形成于具导线的印刷电路板上，透镜架配置于该印刷电路板上，透镜位于该透镜架的上方，滤波器形成于该透镜及该半导体组件封装之间。
6.如权利要求5所述的半导体组件封装结构，其特征在于还包含被动组件形成于该印刷电路板上及该透镜架之内或外部。
7.一种制作半导体组件封装的方法，包含一基板，其特征在于提供该基板，该基板具有晶粒接收穿孔、接触穿孔以及接触金属垫形成于其中；
印刷图案胶于晶粒重分布制具；
使用对位检放系统重分布具有微透镜区域的复数已知晶粒于该具有已知间距的晶粒重分布制具上；
黏着该基板至该晶粒重分布制具；
填充核心材质于该晶粒与该晶粒穿孔侧壁之间及该晶粒背面；
分离该晶粒重分布制具；
形成介电层于该晶粒主动表面及该基板之上；
形成开口以裸露微透镜、该晶粒接触垫及该基板；
形成至少一导电增层于该介电层上；
形成接触结构于该至少一导电增层上；
形成保护层于该至少一导电增层上；
裸露该微透镜区域；
附着透明基底于该保护层上；
形成切割线于该透明基底以定义该透明基底上的覆盖区域；
贴附具该透明基板区域的面板于带型框上；
自该基板下表面切割该基板；
使用打孔器分裂该透明基底；以及
分离该封装。
8.如权利要求7所述的制作半导体组件封装的方法，其特征在于还包含形成导电凸块耦合该接触结构。
9.如权利要求7所述的制作半导体组件封装的方法，其特征在于该基板材质包含环氧树脂型FR5或FR4、BT、PCB、玻璃、硅、陶瓷、合金或金属。
10.如权利要求7所述的制作半导体组件封装的方法，其特征在于还包含形成第二保护层于该微透镜区域上。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011103813A1 (en) * 2010-02-26 2011-09-01 Xintec Inc. Chip package and fabrication method thereof
CN103579260A (zh) * 2012-07-18 2014-02-12 宏翔光电股份有限公司 基板连接式模块结构
CN108447880A (zh) * 2018-03-16 2018-08-24 隋浩智 一种图像传感器及其制造方法

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI311356B (en) * 2006-01-02 2009-06-21 Advanced Semiconductor Eng Package structure and fabricating method thereof
US7812434B2 (en) * 2007-01-03 2010-10-12 Advanced Chip Engineering Technology Inc Wafer level package with die receiving through-hole and method of the same
JP5264332B2 (ja) * 2008-07-09 2013-08-14 ラピスセミコンダクタ株式会社 接合ウエハ、その製造方法、及び半導体装置の製造方法
US7795573B2 (en) * 2008-11-17 2010-09-14 Teledyne Scientific & Imaging, Llc Detector with mounting hub to isolate temperature induced strain and method of fabricating the same
JP5372579B2 (ja) * 2009-04-10 2013-12-18 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
JP5005113B2 (ja) * 2009-04-15 2012-08-22 オリンパスメディカルシステムズ株式会社 半導体装置および内視鏡
GB2471833B (en) * 2009-07-07 2013-05-15 Cambridge Silicon Radio Ltd Under land routing
TWM382505U (en) * 2010-01-15 2010-06-11 Cheng Uei Prec Ind Co Ltd Video device
KR101963809B1 (ko) 2012-04-25 2019-03-29 삼성전자주식회사 이미지 센서 패키지
US9219091B2 (en) 2013-03-12 2015-12-22 Optiz, Inc. Low profile sensor module and method of making same
US9371982B2 (en) * 2013-08-15 2016-06-21 Maxim Integrated Products, Inc. Glass based multichip package
US9559026B2 (en) 2015-02-26 2017-01-31 Infineon Technologies Americas Corp. Semiconductor package having a multi-layered base
WO2017036344A1 (zh) * 2015-08-28 2017-03-09 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
WO2017221589A1 (ja) 2016-06-20 2017-12-28 ソニー株式会社 半導体チップパッケージ
KR102051373B1 (ko) 2016-09-23 2019-12-04 삼성전자주식회사 팬-아웃 센서 패키지 및 이를 포함하는 카메라 모듈
US10644046B2 (en) * 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
JP2019040893A (ja) 2017-08-22 2019-03-14 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置およびその製造方法、並びに電子機器
JP6987443B2 (ja) * 2017-09-08 2022-01-05 株式会社ディスコ ウェーハの加工方法
KR101942740B1 (ko) * 2017-10-19 2019-01-28 삼성전기 주식회사 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈
US10763293B2 (en) * 2017-11-29 2020-09-01 China Wafer Level Csp Co., Ltd. Image sensing chip package and image sensing chip packaging method
KR102052804B1 (ko) * 2017-12-15 2019-12-05 삼성전기주식회사 팬-아웃 센서 패키지
KR102016495B1 (ko) * 2018-01-31 2019-10-21 삼성전기주식회사 팬-아웃 센서 패키지
US11764117B2 (en) 2018-04-03 2023-09-19 Corning Incorporated Hermetically sealed optically transparent wafer-level packages and methods for making the same
JP2019216187A (ja) * 2018-06-13 2019-12-19 ソニーセミコンダクタソリューションズ株式会社 撮像装置
CN109461746A (zh) * 2018-09-30 2019-03-12 华为技术有限公司 一种摄像头组件、组装方法以及终端
CN111146147B (zh) * 2019-12-30 2023-04-28 中芯集成电路（宁波）有限公司 一种半导体器件集成结构及方法
WO2022239464A1 (ja) * 2021-05-13 2022-11-17 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、固体撮像装置の製造方法及び電子機器
TWI780876B (zh) * 2021-08-25 2022-10-11 旭德科技股份有限公司 封裝載板及封裝結構

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576144B1 (en) * 1992-05-22 1998-08-05 Matsushita Electronics Corporation Solid state image sensor and manufacturing method thereof
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011103813A1 (en) * 2010-02-26 2011-09-01 Xintec Inc. Chip package and fabrication method thereof
CN102782862A (zh) * 2010-02-26 2012-11-14 精材科技股份有限公司 芯片封装体及其制造方法
CN102782862B (zh) * 2010-02-26 2015-08-26 精材科技股份有限公司 芯片封装体及其制造方法
CN103579260A (zh) * 2012-07-18 2014-02-12 宏翔光电股份有限公司 基板连接式模块结构
CN108447880A (zh) * 2018-03-16 2018-08-24 隋浩智 一种图像传感器及其制造方法
CN108447880B (zh) * 2018-03-16 2020-10-20 隋浩智 一种图像传感器及其制造方法

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