CN101246882A - 具有多芯片的半导体组件封装结构及其方法 - Google Patents

具有多芯片的半导体组件封装结构及其方法 Download PDF

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CN101246882A
CN101246882A CNA2008100082720A CN200810008272A CN101246882A CN 101246882 A CN101246882 A CN 101246882A CN A2008100082720 A CNA2008100082720 A CN A2008100082720A CN 200810008272 A CN200810008272 A CN 200810008272A CN 101246882 A CN101246882 A CN 101246882A
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crystal grain
substrate
contact mat
weld pad
rerouting
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杨文焜
林殿方
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Publication of CN101246882A publication Critical patent/CN101246882A/zh
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Abstract

本发明公开了一种具有多芯片的半导体组件封装结构及其方法。包含一基板具有至少一晶粒容纳孔穴、连接通孔结构及基板上表面的第一接触垫与下表面第二接触垫，至少一具有第一焊垫的第一晶粒放置晶粒容纳孔穴中，一第一黏着材料形成晶粒之下，以及一第二黏着材料填入晶粒边缘与基板的晶粒容纳孔穴间的间隙，接着一第一焊线形成连结第一焊垫与第一接触垫，进一步至少一具有第二焊垫的第二晶粒放置于第一晶粒，一第二焊线形成连结第二焊垫与第一接触垫，一介电层形成于第一、第二焊线及第一、第二晶粒与此基板之上。其可提供一超薄封装结构，于基板上有较佳的可靠度，并提供一简单制程以形成一半导体组件封装结构，降低成本并提高优良率。

Description

具有多芯片的半导体组件封装结构及其方法
技术领域
本发明涉及一种半导体组件封装结构及方法，特别涉及一种多芯片半导体组件封装结构以及其方法，此结构可降低封装尺寸并增加优良率与可靠度。
背景技术
近年来高科技电子制造业，发展更具功能性与人性化的电子产品，半导体技术的快速发展，通过采用多脚位、精细线宽以及微小化组件等技术，半导体封装于尺寸缩减上已有长足的进步。晶圆级封装的目的与优点，通过使用较短导线长度，以降低制造成本、降低寄生电容效应与寄生电感，以得到较佳的讯杂比(SNR)。
因为传统封装技术需要于晶圆上切割晶粒以成为个别的晶粒，接着对个别的晶粒作封装，所以此技术的制程须耗费相当时间。也因为当高度要求电子组件尺寸，此芯片封装技术便高度影响集成电路的发展。因上述的理由，封装技术的发展演进便由球状矩阵(ball grid array，BGA)、倒装芯片球状矩阵(flip chip ball grid array，FC-BGA)、芯片尺寸封装(chip scalepackage，CSP)、晶圆级封装(Wafer level package，WLP)等技术发展至今日。”晶圆级封装”顾名思义，整个的其它制程，如整体封装以及所有的内部连结，以及其它相关的制程，其于将晶圆切割制程(切割)成为个别的芯片(晶粒)前，业已完成。一般而言，于完成所有组装或封装制程后，晶圆上的个别的半导体封装，其具有复数个半导体晶粒，此晶圆级封装具有极小的封装尺寸，并具有极佳的电气特性。
在制造方法中晶圆级芯片尺寸封装(wafer level chip scale package，WLCSP)为一种先进封装技术，其中晶粒于晶圆上直接制造、测试，且接着切割成个别的晶粒，以为表面黏着产线组装。因为晶圆级封装技术其标的为整个晶圆，而非单一芯片或晶粒，所以于切割制程前，封装与测试业已完成，进一步，WLP制程的先进，可使制程中的打线接合、晶粒黏着以及底部填胶等制程可被省略。通过使用WLP技术，其成本与制造时程可被缩短，且WLP的结构大小与晶粒面积相当，此技术的实施可切合电子组件极小化的需求。进一步，WLCSP其具有于晶粒面积范围内印刷重布电路，以作为焊接点的优点，其可于晶粒面积上形成数组达到重布焊点，有效利用晶粒上的面积。其焊点位于重布电路所形成倒晶凸块，因此其晶粒的底侧可利用微小的焊点，直接连接于印刷电路板。
虽然，WLCSP可大幅减少讯号路径距离，但当其晶粒整合度与内部元建树增加时，其仍然难以提供所有焊点于晶粒表面上，晶粒上的脚位数因整合度高而增加时，其于一数组中重布脚位变得能以达成。纵使脚位重步可达成，其脚位坚的距离可能便得过小，以致于印刷电路板无法达到线宽要求。这也就是前述的结构与制程技术，于大脚位数的封装，将遭遇优良率与可靠度的困难，进一步此方法于制作上将有高成本与费时的缺点。
WLP技术为一种先进封装技术，其中的晶粒于晶圆上直接制作并测试，接着将晶粒切割成单颗，以为表面黏着线组装。因为晶圆级封装技术其标的为整个晶圆，而非单一芯片或晶粒，因此于切割制程前，封装与测试业已完成，进一步，WLP制程的先进，可使制程中的打线接合、晶粒黏着以及底部填胶等制程可被省略。通过使用WLP技术，其成本与制造时程可被缩短，且WLP的结构大小与晶粒面积相当，此技术的实施可切合电子组件极小化的需求。
虽然，WLP技术具有上述优点，其仍然有些问题，影响WLP技术的接受度。例如，WLP结构的两材料以及母板(PCB)间，其热膨胀系数(CTE)差异(失配Mismatch)，成为机械结构不稳定的关键因素。正因为现有技术使用模制化合物封固硅晶粒，美国专利No.6,271,469中所揭示的封装结构，即受到CTE失配因素的困扰。众所周知，硅材料的CTE为2.3，但其模制化合物材料的CTE范围约20-80。于制程中当到达模制化合物与介电层材料的固化温度更高时，此一配置造成芯片位置移位且其内部连结的焊垫移动，受温度循环很难使其回到原先位置(此归因于环氧树脂特性，当固化温度接近/超过薄离转化态温度Tg)，造成优良率与性能问题，此意味现有封装技术，无法应用高脚位数，且可能增加制造成本。
进一步，某些技术包含将晶粒直接形成于基板之上，此半导体晶粒的焊垫通过重布制程重布，其包含一重布层于复数个焊垫中，成为一面型数组，此增层将增加封装面积，而且更增加封装面积，此将与降低封装体积的需求相抵触。
更进一步，现有技术以形成”平板”型封装，困扰于复杂制程，其需要铸模机具，以注入成型材料并封固，于热固化合物后的挠曲，其未必能控制晶粒面与化合物于同一水平，也许须使用化学机械研磨法(CMP)制程将其磨平，这将增加制作成本。
发明内容
本发明目的在于提供一种具有多芯片的半导体组件封装结构，其可提供一超薄封装结构，于基板上有较佳的可靠度，且与PCB具有相同的热膨胀系数。
本发明另一目的在于提供一种具有多芯片的半导体组件封装结构的方法，其可提供一简单制程以形成一半导体组件封装结构，降低成本并提高优良率，较佳的低脚位数组件解决方案。
对于本发明的具有多芯片的半导体组件封装结构来说，上述目的是这样达成的，其包含：一基板，其中至少具有一晶粒容纳孔穴、连接通孔结构以及于此基板上表面的第一接触垫与于此基板下表面的第二接触垫；至少一具有第一焊垫的第一晶粒，其放置于此晶粒容纳孔穴；一第一黏着材料形成于此第一晶粒之下；一第二黏着材料填入此第一晶粒与此基板的晶粒容孔穴侧壁间空隙；一第一焊线形成并连结此第一焊垫与此第一接触垫；至少一第二晶粒其具有第二焊垫放置于此第一晶粒之上；一第二焊线形成并连结此第二焊垫与此第一接触垫；一晶粒黏着材料形成于此第二晶粒之下；以及一介电层形成于此第一、第二焊线与此第一、第二晶粒以及此基板上方。
对于本发明具有多芯片的半导体组件封装结构的方法来说，上述目的是这样达成的，包含：提供一至少具有一晶粒容纳孔穴的基板，其中利用连接通孔结构连结此基板的上表面的第一接触垫以及此基板的下表面的第二接触垫；晶粒重布工具上进行重布，将该至少一具有第一焊垫的第一晶粒，以一取置精细对准系统依适当的间距重布；焊接此基板至此晶粒重布工具；填上一第一黏着材料于此晶粒的背面；填入一第二黏着材料于此晶粒边缘与此基板的晶粒容纳孔穴间的间隙；由此晶粒重布工具分开此封装结构；形成一第一焊线以连结此第一焊垫与此第一接触垫；放置至少一具有第二焊垫的第二晶粒于此第一晶粒上；形成一第二焊线以连结此第二焊垫与此第一接触垫；涂布一介电层于此第一与第二晶粒的主动面以及此基板的上表面上；黏着此封装结构于一胶膜上，以切割制程切割成为个别晶粒。
对于本发明具有多芯片的半导体组件封装结构的方法来说，上述目的是这样达成的，包含：提供一基板其中具有至少一晶粒容纳孔穴，通过连接通孔结构连结于此基板的上表面的第一接触垫以及此基板的下表面的第二接触垫；焊接此基板至此晶粒重布工具；晶粒重布工具上进行重布，将该至少一具有第一焊垫的第一晶粒，以一取置精细对准系统依适当的间距重布；形成一第一焊线以连结此第一焊垫与此第一接触垫；放置至少一具有第二焊垫的第二晶粒于此第一晶粒上；形成一第二焊线以连结此第二焊垫与此第一接触垫；形成一介电层于此第一与第二晶粒的主动面以及此基板的上表面上，并且将其填入此晶粒边缘与此基板的晶粒容纳孔穴间的间隙；自晶粒重布工具上分离此封装结构；以及黏着此封装结构于一胶膜上，以切割制程切割成为个别晶粒。
在上述具有多芯片的半导体组件封装结构及其方法中，本发明提出一半导体封装结构其具有晶粒容纳孔穴结构，其可提供一超薄的封装结构，其封装厚度小于500微米，且其封装面积略大于晶粒面积。进一步本发明提出一周边形式的扇出结构，以作为小脚位数组件封装解决方案。本发明提出一简单半导体组件封装方法，其可增进可靠度与优良率。本发明更进一步提出一新式多晶粒结构，且其可将芯片封装结构尺寸极小化，以及通过低价材料降低成本并简化制程。所以本发明揭示的此超薄芯片尺寸封装结构与其制程方法，提供一超越现有技术的效益并解决现有技术的问题。此方法可应用于晶圆或基板工业，且也可通过调整并应用于其它相关产业。
附图说明
图1为一根据本发明的实施例，以作为半导体组件封装结构的侧视图。
图2a为一根据本发明的另一实施例，以作为半导体组件封装结构的侧视图。
图2b为一根据本发明的又一实施例，以作为半导体组件封装结构的侧视图。
图3为一根据本发明的再一实施例，以作为半导体组件封装结构的侧视图。
图4为一根据本发明的一实施例，以作为半导体组件封装结构的下视图。
图5为一根据本发明的一实施例，以作为半导体组件封装结构的上视图。
图6a-图6d为一根据本发明的一实施例，以作为形成半导体组件封装方法的侧视图。
图7a-图7h为一根据本发明的另一实施例，以作为形成半导体组件封装方法的侧视图。
具体实施方式
本发明将以较佳的实施例及观点加以详细叙述，而此类叙述是解释本发明的结构及程序，只用以说明而非用以限制本发明的申请专利范围。因此，除说明书中的较佳实施例之外，本发明也可广泛实行于其它实施例。
如图1所示为根据本发明的实施例，以作为半导体组件封装结构100的侧视图，其中封装100包含一基板102、一第一晶粒104、一晶粒容纳孔穴105、一第一黏着材料106、一第二黏着材料107、一第一焊垫108、一第一金属或导电层110、一第一焊线112、一第一接触垫113、连接通孔结构114、第二接触垫115、一第二晶粒122、第二焊垫126、一晶粒黏着胶膜124、一第二焊线128、一介电层118以及复数个导电凸块120。
如图1所示此基板102其具有一晶粒容纳孔穴105，以容纳一第一晶粒104于其中，此晶粒容纳孔穴105位于此基板102自上方表面至下方表面，此晶粒容纳孔穴预先形成于基板102中，此第一黏着材料106涂布(黏贴)于此第二晶粒104的下表面之下，作为此第一晶粒104的密封。此第二黏着材料107填入此第一晶粒104边缘与此晶粒容纳孔穴105的侧壁间的间隙，其中此第一黏着材料106与此第二黏着材料107可为同一种材料。
此基板102进一步包含连接通孔结构114形成于其中，此第一接触垫113与第二接触垫115(于有机基板)分别形成于此连接通孔结构114的上表面与下表面以及此基板102的上表面与下表面，导电材料重新填入此连接通孔结构114中，以作为电性导通，此为此基板102的预成形制程。
此外也可以一金属或导电层110涂布于此晶粒容纳孔穴104的侧壁，此也即此金属层110形成于包围此第一晶粒104的此第二黏着材料107与此基板102之间，其可通过使用某些特殊材料，增进晶粒边缘与晶粒容纳孔穴的侧壁105间于基板102上的固着强度，尤其是橡胶型态的黏着材料。
此第一晶粒104放置于此基板102中的此晶粒容纳孔穴105之中，第一焊垫108形成于此第一晶粒104的上表面，第一焊线112的形成以连接此第一焊垫108与此第一接触垫113。
本发明进一步包含一第二晶粒122形成于一晶粒黏着胶膜124之上，且接着至于此第一晶粒104的主动面之上。换句话说，此第二晶粒122置于此第一晶粒104之上，且露出此第一焊垫126以作为电性连结。此第二晶粒122其具有形成复数个第二焊垫126于此第二晶粒122的上表面，形成一第二焊线128以连结此第二焊垫126与此第一接触垫113。接着，一介电层118形成，以覆盖此第一焊线112、此第二焊线128、此第一晶粒104的上表面、此第二晶粒122以及此基板102。
接着复数个导电凸块120形成，并通过涂布锡膏于表面，连接至此第二接触垫115，接着使用回焊制程以回流(reflow)锡膏，此第一晶粒104与此第二晶粒可通过此导电凸块120以及此第一焊线112与此第二焊线128，通过此通孔结构114作电性连接。
此介电层128可作为保护外力造成封装可能的损坏，此金属层110与此第二黏着材料107可作为缓冲区，利用此第二黏着材料107的具有弹性，以吸收此第一晶粒104与基板102间因温度循环所产生的热机械应力，前述的结构其为周边形式(peripheral type)的平面闸格数组封装(LGA)。
于一实施例中，此基板102的材料包含环氧树脂型的FR5、FR4、BT(酰胺-三氮杂苯树脂，Bismaleimide triazine epoxy)，此基板102的材料也可包含金属、合金、玻璃、硅、陶瓷或PCB(印刷电路板)。其中的合金包含合金42(Alloy42)(42％镍-58％铁)或为柯华合金(Kovar)，(29％镍-17％钴-54％铁)。进一步，此合金较佳的组成为合金42，其为一种铁镍合金，其成分为42％镍与58％铁，由于其热膨胀系数，使得其适合与微小化电路的硅芯片接合。此外其合金以可使用柯华合金(Kovar)，其组成为29％镍、17％钴与54％铁。
此基板102的材料以有机基板如环氧树脂型的FR5、BT、PCB较佳，其中具有预先定义的通孔或预先蚀刻的铜金属电路，此热膨胀系数与此基板102的热膨胀系数相同为较佳，基于此基板102的热膨胀系数与此PCB(母板)的热膨胀系数配合，此于本发明中的设计可提供一较佳的可靠度。此有机基板其具有高玻璃转化态温度(Tg)如环氧树脂型的FR5或BT为较佳，铜金属(CTE约为16)也可使用，而玻璃、陶瓷、硅也可为基板的材料，此第二黏着材料107为硅胶填性材料。
于一实施例中，此第一黏着材料106与第二黏着材料107，其可为紫外光(UV)硬化或热硬化方式的环氧树脂或硅胶型材料。此第一黏着材料也可包含金属材料，进一步此介电层材料118可为液态胶(liquid compound)、树脂、硅胶且也可为苯环丁烯(BCB)、硅氧烷高分子(SINR)或聚亚酰胺(PI)。
于一实施例中，此晶粒黏着胶膜124的材料其包含但不限定于弹性材质，此晶粒黏着胶膜124其具有间隔球(space balls)于其中，其可作为缓冲区域，以吸收此第一晶粒104与此第二晶粒122间，因温度循环或UV固化时所产生的机械应力。
请参照图2a，此为一根据本发明的另一实施例，以作为半导体组件封装结构200的侧视图，一基板202包含一连接通孔结构214形成于此基板202的四外围，此也即此连接通孔结构214分别形成于此基板202的两侧边(或四外围)，一第一接触垫213与第二接触垫215分别形成于此连接通孔结构214上表面与下表面以及部分的此基板202的上表面与下表面，其导电材料再灌入此连接通孔结构214以作为电路连接。
进一步此封装结构200包含一第二晶粒222，其具有复数个第二焊垫226于此晶粒222的上表面，此第二晶粒222形成于一晶粒黏着胶膜224，接着放置此第二晶粒222于此第一晶粒204的主动面之上。换句话说，此第二晶粒222放置于此第一晶粒204，并露出此第一焊垫208以作为电性连结。一第二焊线218连结此第二焊垫226与第一接触垫213，接着复数个导电凸块220形成于此第二接触垫215，根据形成于此第一晶粒204中的此第一焊垫208，以及形成于此第二晶粒222中的此第二焊垫226，以及此第一焊线212与此第二焊线228，此导电凸块220可利用通过此连接通孔结构214作电性连结。
此外一金属层或导电层210涂覆于此晶粒容纳孔穴205的侧壁，也即此金属层210形成于为此黏着材料207所包覆的此第一晶粒204与此基板202之间。
进一步如图1与图2所示，于此封装200中的不同单元，与此封装100中的单元类似，其中详细的叙述在此省略。
图2b为一根据本发明的一实施例，以作为半导体组件封装结构200的侧视图，此第一接触垫213形成于连接通孔结构214上，此连接通孔结构214位于切割道230上，换句话说每个封装于切割后，各具有半个通孔结构214，此可表面黏着制程中增进焊料熔接质量，且可降低封装尺寸(foot print)。同样地此半个通孔结构214的结构可形成于此晶粒容纳孔穴205(图中未显示)的侧壁，其可代替此导电层210，此外上述的通孔结构214也称作连接渠(connecting trench)。
根据图3为一根据本发明的一实施例，以作为半导体组件封装结构200的侧视图，为一根据本发明的另一实施例，一封装结构200可被形成于此第二终端接垫215上无需导电凸块，其它单元类同于图1，省略其详细描述。
于此基板102上表面至介电层118面的厚度约118至218微米为较佳，厚度b由此基板102的上表面约100至150微米为较佳，根据本发明设计，可提供一超薄结构其总厚度小于500微米，且其封装面积约为晶粒面积加上各边0.5毫米至1毫米，以使用传统PCB制程，形成一芯片级封装(CSP)。
参照图4，其为根据本发明的一实施例，以作为半导体组件封装结构100的下视图，其中的封装100背面包含此基板102(锡膏罩幕层于图中未显示)以及此第二黏着层107形成于此，且周围具有复数个第二接触垫115。如图中虚线区域外围，此封装100包含一金属层150以溅镀或电镀方式布于此第一晶粒的背面，以代替此第一黏着材料106，其可增加热传导率，图中虚线内区域为此第二晶粒122面积示意，此金属层150可以锡膏与印刷电路板熔接，此可通过印刷电路板上铜箔将热导出(产生自晶粒之热)。
参照图5，其为根据本发明的一实施例，以作为半导体组件封装结构100的上视图，封装100的上视图中包含此基板102，一第一晶粒104形成于此第一黏着材料106。复数个第一接触垫113形成于此基板102边缘区域的四周，此第一焊线112形成并连接此第一焊垫108与此第一接触垫113，进一步第二晶粒122形成于此第一晶粒104之上，并露出此第一焊垫108，此第二焊线128形成以连结此第二焊垫126与此第一接触垫113，此处须注意，此焊线112以及此第二焊线128于介电层118形成后，即为不可见。
此外封装100可应用于更高脚位数，其中的发明实施例与图5相类似，因此省略详细说明，根据此周围型的发明揭示，可提供一良好的低脚位数封装解决方案。
根据本发明的另一观点，本发明进一步提出一方法以作为一半导体组件封装100其中具有多颗晶粒，例如此第一晶粒104与第二晶粒122，参考图6a-图6d，以作为形成半导体组件封装100方法的侧视图，其实施步骤如下且其步骤也可参考图7a-图7f相关方式进行。
如图6a所示，首先此具有一晶粒容纳孔穴105的基板102，连接通孔结构114与此第一接触垫113设置于一此基板102的上表面，以及第二接触垫115设置于此基板102的下表面，其中次晶粒容内孔穴105与此连接通孔结构114以及此第一接触垫113与第二接触垫115预先成型于此基板102内。如图6b所示在一晶粒重布工具300上进行重布，将该至少一具有第一焊垫108的第一晶粒104以一取置精细对准系统依适当的间距置于此晶粒容纳孔穴。如图6c所示，此基板102黏着至重布工具300，此也即此晶粒104的主动面通过涂布胶水(未显示)黏着于晶粒重布工具300。此第二黏着材料107填入介于此晶粒104与此第一晶粒104背面的第一黏着材料106间的空隙后，此第一与第二黏着材料接着硬化，于应用中，此第一黏着材料106与此第二黏着材料107的组成可为同一材料，接着封装结构利用晶粒重布工具300分开。
于清洁此第一焊垫108的上表面以及此第一接触垫113之后(此胶水图案可能残留于第一焊垫108的上表面以及此第一接触垫113)，如图6c通过此第一焊线112形成并连结此第一焊垫108至此第一接触垫113，紧接着形成于此晶粒黏着胶膜124之上的一第二晶粒204，将晶粒204放置于此晶粒202之上，此第二晶粒204并未盖住此第一焊垫108，所以此第一焊垫108可露出并作为电性连结，此第二晶粒202之上具有此第二焊垫126，接着以第二焊线128连接此第二焊垫126与此第一接触垫113。
接着如图6d所示，于此第一晶粒104的主动层以及此第二晶粒122与此基板102的上表面，披覆(涂布、灌注或散布)并硬化的此介电层118，以作为此第一焊线112以及此第一晶粒104的此第二焊线128此第二晶粒122与此基板120的保护。终端接触垫形成于此第二接触垫115利用锡膏(或锡球)涂布，接着通过回焊方式形成复数个导电凸块120，并且连结的此第二接触垫115，接着此封装结构黏着于一胶膜，以作为切割制程之用。
此外一金属或导电层110或可形成于此基板102中的此晶粒容纳孔穴105的侧壁上，此金属可于基板制程中预先成型，一金属膜(层)可使用溅镀或电镀于此第一晶粒104的背面作为此第一黏着材料106，以得到较佳的热处理需求。
根据本发明的另一观点，本发明也提出另一方法以形成具有晶粒容纳孔穴205并连结通孔结构214的半导体组件封装200，图7a-图7h为一根据本发明的另一实施例，以作为形成半导体组件封装方法的侧视图。
形成此封装200的步骤可包含提供一具有晶粒容纳孔穴205的基板202，连结通孔结构215与此第一接触垫213于此基板202上表面以及一第二接触垫215于此基板202下表面。如图7a此基板202黏于一晶粒重布工具300上，换句话说，此基板202的主动面(作为焊接)通过涂布图案胶水(图中未显示)，黏着于晶粒重布工具300上。如图7b其中于此第一晶粒204其具有第一焊垫208形成于此第一晶粒204的上表面，并且此第一黏着材料206(其或可为黏性胶膜)形成于此第一晶粒204的背面，通过取置精细对准系统依适当的间距，此第一晶粒204重置于晶粒重布工具300上。如图7c，接着此第一焊线212形成，由此第一焊垫208连结至此第一接触垫213。
如图7d，紧接着此第二晶粒222形成于晶粒黏着胶膜224，并接着置于此第一晶粒204之上并露出此第一焊垫208。如图7e，此第二晶粒222具有此第二焊垫226形成于此第二晶粒之上，接着此第一黏着材料206与此晶粒黏着胶膜224被固化。如图7e，并形成此第二焊线228以连结此第二焊垫226以及此第一接触垫213。
如图7f接着此介电层218形成于此第一晶粒204的主动面之上、此第二晶粒222以及此基板202上表面，作为第二黏着材料207，完全覆盖此第一焊线212与此第二焊线228，并且填入晶粒边缘与此晶粒容纳孔穴205侧壁间的空隙。如图7g所示，接着固化此介电层218，并于通过此晶粒重布工具分开此封装结构后，清洁此基板202的背面与此第一黏着材料206。
此终端接触垫另外可通过涂布锡膏形成于此第二接触垫215之上，此也可形成复数个导电凸块并连结至第二接触垫215，紧接着此封装结构200黏着于一胶膜302以施行晶粒切割制程。
如图7h所示，于一实施例中，一传统切割刀232用于晶粒切割制程，此刀具232对准切割道230以分离晶元，通过切割制程，使之成为单一晶粒。
此外一金属层或导电层210形成于此基板202中的此晶粒容纳孔穴的侧壁上，此为前述的预形成型。形成此第一黏着材料206的另一制程步骤，包含种子金属溅镀、形成图案、电镀(铜)、光阻去除、金属湿蚀刻等步骤，以形成此金属层150。
于一实施例中形成导电凸块120与220的方式，可以红外线回焊方式达成。
须注意于图中所示的材料与结构的布置，并非为限制本发明，其中的材料与结构的布置可根据不同状况的需求，作出调整。
根据本发明的观点，本发明提出一半导体封装结构其具有晶粒容纳孔穴结构，其可提供一超薄的封装结构，其封装厚度小于500微米，且其封装面积略大于晶粒面积。进一步本发明提出一周边形式的扇出结构，以作为小脚位数组件封装解决方案。本发明提出一简单半导体组件封装方法，其可增进可靠度与优良率。本发明更进一步提出一新式多晶粒结构，且其可将芯片封装结构尺寸极小化，以及通过低价材料降低成本并简化制程。所以本发明揭示的此超薄芯片尺寸封装结构与其制程方法，提供一超越现有技术的效益并解决现有技术的问题。此方法可应用于晶圆或基板工业，且也可通过调整并应用于其它相关产业。
上述叙述为本发明的较佳实施例。此领域的技术人员应领会其用以说明本发明而非用以限定本发明所主张的专利权利范围。其专利保护范围当视权利要求及其等同领域而定。凡熟悉此领域的技术人员，在不脱离本专利精神或范围内，所作的更动或润饰，均属于本发明所揭示精神下所完成的等效改变或设计，且应包含在权利要求范围内。

Claims (10)

1.一种具有多芯片的半导体组件封装结构，其特征在于：包含：
一基板，其中至少具有一晶粒容纳孔穴、连接通孔结构以及于此基板上表面的第一接触垫与于此基板下表面的第二接触垫；
至少一具有第一焊垫的第一晶粒，其放置于此晶粒容纳孔穴；
一第一黏着材料形成于此第一晶粒之下；
一第二黏着材料填入此第一晶粒与此基板的晶粒容孔穴侧壁间空隙；
一第一焊线形成并连结此第一焊垫与此第一接触垫；
至少一第二晶粒其具有第二焊垫放置于此第一晶粒之上；
一第二焊线形成并连结此第二焊垫与此第一接触垫；
一晶粒黏着材料形成于此第二晶粒之下；以及
一介电层形成于此第一、第二焊线与此第一、第二晶粒以及此基板上方。
2.根据权利要求1所述具有多芯片的半导体组件封装结构，其特征在于：包含复数个导电凸块连接该第二接触垫。
3.根据权利要求1所述具有多芯片的半导体组件封装结构，其特征在于：所述的连接通孔结构形成于该基板的四周侧，且进一步包含一金属或导电层形成于该晶粒容纳孔穴结构的侧壁上。
4.一种制造权利要求1所述具有多芯片的半导体组件封装结构的方法，其特征在于：包含：
提供一至少具有一晶粒容纳孔穴的基板，其中利用连接通孔结构连结此基板的上表面的第一接触垫以及此基板的下表面的第二接触垫；
晶粒重布工具上进行重布，将该至少一具有第一焊垫的第一晶粒，以一取置精细对准系统依适当的间距重布；
焊接此基板至此晶粒重布工具；
填上一第一黏着材料于此晶粒的背面；
填入一第二黏着材料于此晶粒边缘与此基板的晶粒容纳孔穴间的间隙；
由此晶粒重布工具分开此封装结构；
形成一第一焊线以连结此第一焊垫与此第一接触垫；
放置至少一具有第二焊垫的第二晶粒于此第一晶粒上；
形成一第二焊线以连结此第二焊垫与此第一接触垫；
涂布一介电层于此第一与第二晶粒的主动面以及此基板的上表面上；
黏着此封装结构于一胶膜上，以切割制程切割成为个别晶粒。
5.根据权利要求4所述具有多芯片的半导体组件封装结构的方法，其特征在于：包含一熔溶复数个焊料凸块于该终端接垫的步骤。
6.根据权利要求4所述具有多芯片的半导体组件封装结构的方法，其特征在于：进一步包含将黏着胶膜形成于该第二晶粒的步骤。
7.一种制造权利要求1所述具有多芯片的半导体组件封装结构的方法，其特征在于：包含：
提供一基板其中具有至少一晶粒容纳孔穴，通过连接通孔结构连结于此基板的上表面的第一接触垫以及此基板的下表面的第二接触垫；
焊接此基板至此晶粒重布工具；
晶粒重布工具上进行重布，将该至少一具有第一焊垫的第一晶粒，以一取置精细对准系统依适当的间距重布；
形成一第一焊线以连结此第一焊垫与此第一接触垫；
放置至少一具有第二焊垫的第二晶粒于此第一晶粒上；
形成一第二焊线以连结此第二焊垫与此第一接触垫；
形成一介电层于此第一与第二晶粒的主动面以及此基板的上表面上，并且将其填入此晶粒边缘与此基板的晶粒容纳孔穴间的间隙；
自晶粒重布工具上分离此封装结构；以及
黏着此封装结构于一胶膜上，以切割制程切割成为个别晶粒。
8.根据权利要求7所述具有多芯片的半导体组件封装结构的方法，其特征在于：包含一熔溶复数个导电凸块于该第二接触垫上的步骤。
9.根据权利要求7所述具有多芯片的半导体组件封装结构的方法，其特征在于：进一步包含一通过具有图案化胶水将该第一晶粒的背面黏着于该晶粒重布工具的步骤。
10.根据权利要求7所述具有多芯片的半导体组件封装结构的方法，其特征在于：进一步包含将晶粒黏着胶膜形成于该第二晶粒的步骤。
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CN107342264A (zh) * 2017-07-21 2017-11-10 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN107342265A (zh) * 2017-07-21 2017-11-10 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN107342265B (zh) * 2017-07-21 2019-08-30 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法
CN107342264B (zh) * 2017-07-21 2019-09-17 华进半导体封装先导技术研发中心有限公司 扇出型封装结构及其制造方法

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US20080274593A1 (en) 2008-11-06
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