CN101202253A - 具有良好热膨胀系数效能的圆片级封装及其方法 - Google Patents

具有良好热膨胀系数效能的圆片级封装及其方法 Download PDF

Info

Publication number
CN101202253A
CN101202253A CNA2007101994828A CN200710199482A CN101202253A CN 101202253 A CN101202253 A CN 101202253A CN A2007101994828 A CNA2007101994828 A CN A2007101994828A CN 200710199482 A CN200710199482 A CN 200710199482A CN 101202253 A CN101202253 A CN 101202253A
Authority
CN
China
Prior art keywords
substrate
chip
layer
dielectric layer
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101994828A
Other languages
English (en)
Inventor
杨文焜
王东传
周昭男
林志伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yupei Science & Technology Co Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN101202253A publication Critical patent/CN101202253A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明提供一种封装结构，包含基板，其具有预先形成的芯片接收凹槽和/或终端接触金属垫，形成于基板的上部表面。芯片则配置黏附于芯片接收凹槽，而介电层则形成于芯片与基板上。至少一重分布增进层(re－distribution builtup layer，简称RDL)形成于介电层上，并通过接触焊垫耦合至芯片。连接结构，诸如球底层金属(UBM)则形成于重分布增进层上，而终端导电凸块则耦合至球底层金属(UBM)。

Description

具有良好热膨胀系数效能的圆片级封装及其方法
技术领域
本发明是关于一种圆片级封装的构造，特别是一种具有良好热膨胀系数(good CTE)的圆片级封装构造。
背景技术
于半导体装置领域中，其装置的密度不断地增加，而其尺寸渐渐缩小。封装或内接(interconnecting)技术，应用于高密集度的装置的需求也增加，以满足上述情况。一般芯片倒装焊封装(flip-chip attachment)方法中，锡凸块形成于芯片表面上。其锡凸块的构成可使用锡化合材料，通过锡球罩幕(solder mask)用以产生想要的锡凸块图案。芯片封装的功能包括电源分配、信号分配、散热、防护与支撑等等功能。当半导体技术越复杂，传统的封装技术，例如导线架封装(lead frame package)、软式封装(flex package)、刚性封装(rigid package)等封装技术已经不能满足量产体积小、具有高密度组件等等特性的芯片需求。
再者，因为传统封装技术必须分割圆片上的芯片成独立的组件，并随后个别地封装其芯片。因此，上述封装技术消耗了许多工艺时间。集成电路的发展高度地影响芯片封装技术，因此当电子组件的尺寸视为趋势时，封装技术势必也随之起舞。基于上述理由，现今封装技术的趋势是朝向锡球数组(BGA)、多晶技术(FC-BGA)、芯片级封装(CSP)、圆片级封装(WLP)。「圆片级封装」由其文义，可了解其方法是在将圆片切割成芯片前，完整的封装其芯片并完成圆片上所有的内接(interconnections)以及其它的工艺。在组装程序或封装程序后，于具有复数个半导体芯片的圆片上，分割半导体封装成独立的单元。圆片级封装具有极小的尺寸以及极优良的电性等等优点。
圆片级封装(WLP)是一种先进的封装技术，是使半导体芯片于圆片(wafer)上进行加工与测试，并进行单切分割，使其得于表面装配生产在线进行组装。由于圆片级封装技术使整个封装工艺在圆片上完成，而非针对单一芯片或芯片，因此在进行蚀刻线割(scribing)前，封装(packaging)与测试等步骤即已完成；此外，圆片级封装(WLP)的先进技术省略了打线(wirebonding)、黏晶(die mount)与底部封胶(under-fill)等程序。利用圆片级封装(WLP)技术，则可节省制造成本与时间，而圆片级封装(WLP)的最终产物结构则与芯片相同；因此，此技术正符合电子电路设备微小化的需求。
虽然，圆片级封装(WLP)技术有着如上所述的种种优点，但其仍存在有一些问题影响了对于圆片级封装(WLP)的接受度。例如：圆片级封装(WLP)结构的材料间热膨胀系数(CTE)的差异，便是影响该结构的机械不稳定性的一个关键因素。依照英特尔(Intel)的美国专利第6,271,469号所揭露的一种封装系统，其公知技术使用膜封材料(molding compound)来封装硅芯片。已知，硅材料的热膨胀系数(CTE)为2.3，然而膜封材料(moldingcompound)的热膨胀系数(CTE)大约是20到40。这样的配置将会导致在装配程序中，由于膜封材料与介电层材料的热固化温度较高，致使芯片的移位，而内接垫(inter-connecting pad)亦可能移位而导致制造生产与操作执行上的问题。而在温度循环的过程中，很难将其回归原位(当热固化温度接近/超过高玻璃转换温度(Glass transition temperature，简称Tg)时，环氧树脂的特性即造成此现象)。这也意味着该公知技术的结构封装并不能被大量处理加工，并且其将导致过高生产成本。
除此之外，许多技术必须使用到直接形成于基板(substrate)表面的芯片。已知，半导体芯片的焊垫通过重分布层(redistribution layer，简称RDL)进行重分布程序，使其在片面数组式(area array type)中重分布于复数金属垫，而增进层(build-up layers)将增加封装的体积，封装的厚度也因此增加；如此，便违背了减少芯片体积的要求。
另外，公知技术受困于用以形成「板型」封装的复杂程序。其需要塑模工具以用于封装及注入塑模材料。由于材料热固化后形成的变形，故无法控制芯片与材料的表面于同一平面上，因此可能需要利用化学机械研磨(CMP)程序以刨光不平坦的表面，而成本遂增加。
发明内容
本发明的目的在于提供一种具有良好热膨胀系数效能的圆片级封装及其方法。
为实现上述目的，本发明提供的半导体组件封装结构，其包含：
一基板，具有一预先形成的芯片接收凹槽和/或终端接触垫，形成于该基板的上表面；
一芯片，配置黏附于该芯片接收凹槽；
一介电层，形成于该芯片及该基板上，并填充于该芯片与该基板间空隙，以吸收其间的热机械应力，其中该介电层包含一弹性介电层、一感光层、一含硅型介电层、一硅氧烷聚合物层、一聚亚酰胺层或一硅树脂层；
一重分布层，形成于该介电层上且耦合至该芯片；以及
复数个焊垫，耦合至该重分布层。
所述的半导体组件封装结构，其中，还包含耦合至该焊垫的导电凸块。
所述的半导体组件封装结构，其中，该重分布层包含钛/铜/金合金或钛/铜/镍/金合金，并且该基板的材料包含环氧树脂类型的耐高温玻璃纤维板、玻璃纤维板、双马来酰亚胺三氮杂苯树脂、硅、印刷电路板材料、玻璃、陶瓷、合金或金属。
所述的半导体组件封装结构，其中，该基板的材料包含合金42(包含42％镍与58％铁)或柯伐合金(包含29％镍、17％钴与54％铁)。
所述的半导体组件封装结构，其中，还包含形成于该重分布层上的保护层。
本发明提供的用于形成半导体组件封装的方法，其包含：
提供一基板，该基板具有形成于其上表面预先形成芯片接收凹槽和/或终端接触垫；
利用取放精密对准系统将已知为良好的芯片以期望之间距重新分布于承载组件，其中该承载组件包含于该承载组件周围区域的胶合材料，以黏附该基板；
将该胶合材料黏附于芯片的背面；
将该基板接合于该芯片的背面，并予以固化后，自该基板分离该组件；
涂布介电层于该芯片与该基板上，随后执行真空程序；
形成开孔以暴露该芯片和/或该基板上的接触垫；
形成至少一导电增进层于该介电层之上；
形成连接结构于该至少一导电增进层之上；以及
形成保护层于该至少一导电增进层之上。
所述的方法，其中，还包含形成耦合至该连接结构的导电凸块。
所述的方法，其中，该介电层包含一弹性介电层、一感光层、一含硅型介电层、一聚亚酰胺层或一硅树脂层。
所述的方法，其中，该基板的材料包含环氧树脂类型的耐高温玻璃纤维板、玻璃纤维板、双马来酰亚胺三氮杂苯树脂、硅、印刷电路板材料、玻璃、陶瓷、合金或金属，并且该合金包含合金42(包含42％镍与58％铁)或柯伐合金(包含29％镍、17％钴与54％铁)。
所述的方法，其中，该至少一导电增进层是由合金所制成，其中该合金包含钛/铜/金合金或钛/铜/镍/金合金，并且该承载组件是由玻璃所制成。
本发明的优点为：
工艺步骤易于形成面板圆片类型且易于控制面板表面的粗糙度。面板的厚度(包含芯片黏附)易于控制且于加工程序期间芯片偏移的问题将得以排除。可省略注入塑模工具且亦将不会导致引入化学机械研磨(CMP)所引发的刨光变形。
预先备妥具有预先形成凹槽与终端接触金属垫的基板(适用于有机基板)，而凹槽的尺寸约同于(芯片的尺寸于每一侧约加50到100微米，而藉由填充弹性介电材料可用作为应力缓冲释放区域，以吸收由于硅芯片与基板(耐高温玻璃纤维板(FR5)/双马来酰亚胺三氮杂苯树脂(BT)间热膨胀系数不同所造成的热应力)。由于应用简化的增进层于芯片表面上方，故封装生产率将会增加(制造循环时间减少)。终端焊垫形成于芯片主动面的同侧。
芯片放置程序与现行程序相同。无核心黏胶材料(树脂、环氧型化合物、硅胶等)的充填为本发明的必须。热膨胀系数不匹配问题于板型工艺期间予以克服，而芯片与玻璃纤维基板(FR4)间的深度大约仅20到30微米(作为芯片黏附厚度)，当芯片黏附于基板的凹槽后，芯片与基板的表面度可为相同。唯独含硅型介电材料(最好为硅氧烷聚合物(SINR))涂布于主动面与基板(最好为玻璃纤维板(FR4)、耐高温玻璃纤维板(FR5)或双马来酰亚胺三氮杂苯树脂(BT))表面上。由于介电层(硅氧烷聚合物(SINR))为感光层而用以开启接触通孔，故只利用光屏蔽程序即得以开启接触垫。硅氧烷聚合物(SINR)涂布中的真空步骤，用以减少于芯片和基板上凹槽的空隙填充过程所产生的气泡问题。在基板与芯片(芯片)相接合前，芯片黏附材料即印刷于芯片背侧。封装及电路板级二者的可靠度较公知技术为佳，特别于电路板级温度循环测试，乃因基板及印刷电路主机板的热膨胀系数为相同，故无热机械应力作用于焊锡凸块/球上，也因此公知技术中于电路板级测试的温度循环期间的失败模式(焊锡球损毁)于本发明下变得不明显。成本得降低且程序步骤简化。亦易于形成多重芯片封装。
附图说明
图1是根据本发明，说明扩散型圆片级封装(平面闸格数组(LGA)型)结构的横切面示意图。
图2是根据本发明，说明扩散型圆片级封装(锡球数组(BGA)型)结构的横切面示意图。
图3是根据本发明，说明扩散型圆片级封装结构的横切面示意图。
图4是根据本发明，说明基板与承载组件结合的横切面示意图。
图5是根据本发明，说明基板与承载组件结合的顶视图。
图6是根据本发明，说明半导体组件封装设置于印刷电路板(PCB)或主机板结合的横切面示意图。
附图中主要组件符号说明：
基板2
终端接触金属垫3
芯片接收凹槽4
芯片6
胶合材料8
接触垫(接合垫)10
介电层12
重分布层(RDL)14
保护层16
终端焊垫18
导电球20
重分布层24
切割线28
玻璃承载组件40
胶合材料44
具体实施方式
本发明提供了具绝佳热膨胀系数表现及锐减尺寸的扩散型圆片级封装。
本发明提供了具有内含芯片接收凹槽的基板的圆片级封装，以减小组件尺寸。
本发明提供了形成于芯片与基板上的介电层，并填充于芯片与基板间空隙，以吸收其间的热机械应力；其中该介电层包含弹性介电层、感光层、含硅型介电层、硅氧烷聚合物(SINR)层、聚亚酰胺(PI)层或硅树脂层。
本发明公开了一封装结构，包含基板，其具有预先形成的芯片接收凹槽和/或终端接触金属垫(适用FR5/BT的基板)装配于基板的上表面。芯片则以黏着方式配置于芯片接收通孔，而介电层则形成于芯片及基板上。至少一个重分布增进层(re-distribution built up layer)形成于介电层上，并通过接触垫与芯片耦合。连接结构，诸如球底层金属(UBM)，则形成于重分布增进层上，以及终端接触金属垫上。终端导电凸块(Terminal Conductivebump)则耦合至球底层金属(UBM)。
介电层包含弹性介电层、含硅型介电材料、苯酰环丁烯(Benzoyclobutane，简称BCB)或聚亚酰胺(PI)。其中，含硅型介电材料包含硅氧烷聚合物(SINR)、道康宁(Dow Corning)WL5000系列及其结合；或者，介电层亦可选择包含感光层。该介电层形成于芯片与基板上，并且填充于芯片与基板间空隙，以吸收其间的热机械应力；其中该介电层包含弹性介电层、感光层、含硅型介电层、硅氧烷聚合物(SINR)层、聚亚酰胺(PI)层或硅树脂层。
基板的材料包含玻璃纤维板(FR4)、耐高温玻璃纤维板(FR5)、双马来酰亚胺三氮杂苯树脂(Bismaleimide Triazine epoxy，简称BT)、印刷电路板(PCB)材料、聚亚酰胺(PI)、合金或金属。该合金42(Alloy42，包含42％镍与58％铁)，或是柯伐合金(Kovar，包含29％镍、17％钴与54％铁)。或者，该基板亦可选择为玻璃、陶瓷或硅材质。
本发明将以较佳实施例及附图加以详细叙述。然而，本领域技术人员将得以领会，本发明的较佳实施例是为说明而叙述，而非用以限制本发明的权利要求范围。除此处明确叙述的较佳实施例外，本发明可广泛实行于其它实施例，且本发明的范围除申请的权利要求范围所明定外不特别受限。
本发明公开一种扩散型圆片级封装结构，其利用具有形成其上的预定终端接触金属垫3与形成于其中的预先形成的凹槽4的基板2。芯片配置于基板的芯片接收凹槽内且附着于核心黏胶材料，感光材料则涂布于芯片与预先形成的基板上。感光材料最好以弹性材料形成。
图1是根据本发明，说明扩散型圆片级封装结构的横切面示意图。如图1所示，扩散型圆片级封装结构包含具有终端接触金属垫3的基板2(适用有机基板)，以及形成其内的芯片接收凹槽4，其用以装配接收芯片6，而接收凹槽4预先形成于基板2内。在基板2的下表面形成覆盖物22，用以进行激光标记或保护，其材料包含环氧型化合物。
芯片6装配于基板2上芯片接收凹槽4中，并以胶合材料8予以固定(最好为弹性材料)。如其所知，接触垫(接合垫)10形成于芯片6。感光层或介电层12则形成于芯片6上，并填充于芯片6与接收凹槽4的侧壁间空隙。复数个开孔光微影蚀刻程序或曝光及显影程序形成于介电层12内，数个开孔各别对准于接触垫(或输出入焊垫)10及终端接触金属垫3(参阅图2)。重分布层(RDL)14，亦称为导线14，是由移除形成于介电层12上的选定部分金属层(种晶层，seed layer)而形成于介电层12上，其中重分布层(RDL)14通过输出入焊垫10及终端接触金属垫3与芯片6保持电性连接。重分布层(RDL)部份材料会再填充至介电层12上的开孔，而保护层16则会行程并覆盖重分布层(RDL)14。终端焊垫18位于保护层16上，并连接至重分布层(RDL)14及基板的终端接触金属垫3。切割线28定义于封装单元2间以用于分离每一单元，切割线28上可选择性没有介电层。
介电层12形成于芯片6与基板2的顶部，并填充芯片6周围的空隙；由于介电层12为弹性材质，故其可作用为缓冲区域，其吸收温度循环期间芯片6与基板2间的热机械应力。上述结构构成平面闸格数组(LGA)型封装。
一替代性实施例可参阅图2，导电球20形成于终端焊垫18上。此类型称为锡球数组(BGA)型。其它部分类似于图1，故省略详细叙述。终端焊垫18可作用为此实施例中锡球数组(BGA)结构下的球底层金属(UBM)。复数个接触导电垫3形成于基板2的上表面且于重分布层14下方。
基板2的材料最好为有机基板，例如具已定义接收凹槽的环氧型耐高温玻璃纤维板(FR5)、双马来酰亚胺三氮杂苯树脂(BT)、印刷电路板(PCB)或具预蚀刻电路的合金42。具高玻璃化转变温度(Tg)的有机基板最好为环氧型耐高温玻璃纤维板(FR5)或双马来酰亚胺三氮杂苯树脂(BT)型基板。合金42是由42％的镍与58％的铁所组成。柯伐(Kovar)金属亦可使用，其组成包含29％的镍、17％的钴与54％的铁。玻璃、陶瓷或硅亦可用作为基板。
由于环氧型有机基板(耐高温玻璃纤维板(FR5)/双马来酰亚胺三氮杂苯树脂(BT))的热膨胀系数(X/Y方向)约为16，而利用玻璃材料作为芯片重分布的工具其热膨胀系数约为5至8。因此，耐高温玻璃纤维板(FR5)/双马来酰亚胺三氮杂苯树脂(BT)于温度循环(该温度接近玻璃化转变温度(Tg))后无法回复至原本位置，而于需要数个高温程序例如的圆片级封装(WLP)程序期间造成板型中芯片的偏移，例如：介电层的形成、热固化芯片黏附材料等，而以下程序步骤与工具是为确保在程序进行中有机基板的原始位置，而不会有任何扭曲偏移产生。
请参照图3，基板可为圆形例如圆片型，其半径可为200毫米、300毫米或以上。基板亦可为矩形例如板型。图3说明于加工处理后，单切分割前，用于板圆片型的基板2的形成。由图可知，基板2是预先形成芯片接收凹槽4。在图4的上部份，图1的封装单元则被配置一矩阵型式中。切割线28定义于封装单元2间以用于分离每一单元2。
请参阅图4，基板2的周围区域(边缘)并未包含接收凹槽4。圆片级封装(WLP)的过程中，玻璃承载组件40与形成于该玻璃组件周围的胶合材料(最好是紫外线固化型)44用以(黏合)处理有机基板。图4的下部分是说明玻璃承载组件40与基板2，经由接合与紫外线固化程序而产生结合。
图5显示基板2的边缘区域并未包含芯片接收凹槽，其周围区域是于圆片级封装(WLP)的过程中，用以固定玻璃承载组件。基板黏附于玻璃承载组件，而于处理程序中，其将予以固定并支持撑托基板。待圆片级封装(WLP)程序完成后，依虚线指示的区域则由玻璃承载组件上予以切除，这表示由虚线所定义的内部区域将进行封装的单切分割(singulation)的圆片切割程序。
本发明的一实施例中，介电层12最好为弹性介电材料，其以含硅介电型材料组成，包含硅氧烷聚合物(SINR)、道康宁(Dow Corning)WL5000系列及其结合。另一实施例中，介电层是由包含聚亚酰胺(PI)或硅树脂的材料所组成。其最好为感光层以简化工艺。
本发明的一实施例中，弹性介电层为一种具有大于100(ppm/℃)的热膨胀系数、约40％的伸长率(最好30％至50％)及介于塑料及橡胶间的硬度的材料。弹性介电层18的厚度，取决于在温度循环测试期间累积于重分布层/介电层界面内的应力。
请参阅图6，其说明关于热膨胀系数争议的重要部分。硅芯片(热膨胀系数(CTE)约为2.3)封装于组件封装内。耐高温玻璃纤维板(FR5)或双马来酰亚胺三氮杂苯树脂(BT)等有机环氧型材料(热膨胀系数(CTE)约为16)是用作为基板，且其热膨胀系数系与印刷电路板(PCB)或主机板(MotherBoard)相同。芯片与基板间的空隙以填充材料(最好为弹性核心黏胶)充填，以吸收热膨胀系数不匹配(芯片与环氧型耐高温玻璃纤维板(FR5)/双马来酰亚胺三氮杂苯树脂(BT)间)所造成的热机械应力。此外，介电层12包含弹性材料以吸收芯片垫与印刷电路板(PCB)间的应力。重分布层(RDL)的金属为铜/金材料且其热膨胀系数约为16，与印刷电路板(PCB)及有机基板相同，而接触凸块的球底层金属(UBM)18则设置于基板的终端接触金属垫上方。印刷电路板(PCB)的金属焊垫为铜组成金属，铜的热膨胀系数约为16，与印刷电路板(PCB)的热膨胀系数相匹配。综上所述，本发明可提供用于圆片级封装(WLP)程序中，绝佳的热膨胀系数(于X/Y方向充分匹配)解决方案。
显然，增进层(build-up layers)下(印刷电路板(PCB)与基板)的热膨胀系数相配问题，因本发明的方案而获得解决，且其提供了较高的可靠性(基板上无X/Y轴方向热应力产生)；且利用弹性介电层吸收Z轴方向的应力。仅有一材料(环氧型材料)需进行单切分割。另可于芯片边缘与凹槽侧璧间的空隙填充弹性介电材料，以吸收其机械/热应力。
本发明的一实施例中，重分布层24的材料包含钛/铜/金合金或钛/铜/镍/金合金，其厚度是于2微米至15微米间。钛/铜合金是由溅镀技术形成作为种子金属层，且铜/金或铜/镍/金合金是由电镀技术形成；利用电镀程序形成重分布层可使重分布层具有足够的厚度以抵抗温度循环期间的热膨胀系数不匹配。金属垫20可为铝或铜或其结合。若扩散型圆片级封装(FO-WLP)结构利用硅氧烷聚合物(SINR)作为弹性介电层，且利用铜作为重分布层的金属，根据未图示于此的应力分析，累积于重分布层/介电层界面内的应力则会降低。
如图1至图3所示，重分布层(RDL)24从芯片扩散出且朝终端垫18连通。与公知技术不同，芯片6由基板内预先形成的接收凹槽所接收，以此减少封装厚度。公知技术违反减少芯片封装厚度的规则；而本发明的封装将较公知技术为薄。此外，基板是于封装前预先备妥，而芯片接收凹槽4是预先定义。因此，生产率将较以前得到大幅改善。本发明揭露具有减小的厚度及良好的热膨胀系数匹配表现的扩散型圆片级封装。
本发明的程序包含提供对准工具，其具有形成其上的对准图型。接着，图样化黏着剂是予以印刷于工具上(用以黏附芯片的表面)，接续为利用具多晶功能的取放精密对准系统以重分布期望芯片于工具上使其具期望的间距。图样化黏着剂将黏着芯片于工具上。之后，芯片黏附材料则印刷于芯片背面(最好是弹性材料)。嗣后，板结合剂是用以结合基板至芯片背面；而基板上部表面除凹槽外，亦黏贴图样化黏着剂，其后进行真空固化，并自从板型圆片分离该组件。
另外，亦可选择利用具有精密对准工具的芯片键合机，而芯片黏附材料则配置于基板的凹槽，芯片则置放于基板的凹槽。芯片黏附材料经热固化后，得使芯片确实固定于基板上。
一旦芯片重分布于基板上，则施行洁净程序以湿式清洗和/或干式清洗清洁芯片表面。其后步骤为涂布介电材料于板型的表面上，并接着进行真空步骤以确定板型并无气泡。随后，施行光微影蚀刻程序以开启通孔(接触金属垫)、铝接合垫和/或切割线(选择性)。接着，执行等离子清洗(plasmaclean)步骤以清洗通孔及铝接合垫的表面。下一步骤为溅镀钛/铜作为种子金属层，并接着涂布光阻(PR)于介电层及种子金属层上以用于形成重分布金属层图形。之后，进行电镀程序以形成铜/金或铜/镍/金作为重分布层金属，随后剥除光阻(PR)并进行金属湿蚀刻以形成重分布层金属导线。其后，涂布或印刷顶部介电层，并由形成球底层金属(UBM)以开启接触凸块和/或开启切割线(选择性)。
当锡球植入或锡膏印刷后，施行热回融程序以回焊锡球处(适用于锡球数组)，执行测试。利用垂直式探针卡(probe card)施行板圆片级最终测试。于测试后，切割基板以分离封装成独立单元。接着，封装单元各别取放至托盘或卷带及滚动条上。
虽本发明的较佳实施例已叙述如上，然而，本领域技术人员将得以了解，本发明不应受限于所述的较佳实施例。更确切地来说，本领域技术人员可于本发明的权利要求范围所定义的本发明的精神及范围内做若干改变或修改。

Claims (10)

1.一半导体组件封装结构，其特征在于，包含：
一基板，具有一预先形成的芯片接收凹槽和/或终端接触垫，形成于该基板的上表面；
一芯片，配置黏附于该芯片接收凹槽；
一介电层，形成于该芯片及该基板上，并填充于该芯片与该基板间空隙，以吸收其间的热机械应力，其中该介电层包含一弹性介电层、一感光层、一含硅型介电层、一硅氧烷聚合物层、一聚亚酰胺层或一硅树脂层；
一重分布层，形成于该介电层上且耦合至该芯片；以及
复数个焊垫，耦合至该重分布层。
2.如权利要求1所述的半导体组件封装结构，其特征在于，还包含耦合至该焊垫的导电凸块。
3.如权利要求1所述的半导体组件封装结构，其特征在于，该重分布层包含钛/铜/金合金或钛/铜/镍/金合金，并且该基板的材料包含环氧树脂类型的耐高温玻璃纤维板、玻璃纤维板、双马来酰亚胺三氮杂苯树脂、硅、印刷电路板材料、玻璃、陶瓷、合金或金属。
4.如权利要求3所述的半导体组件封装结构，其特征在于，该基板的材料包含合金42(包含42％镍与58％铁)或柯伐合金(包含29％镍、17％钴与54％铁)。
5.如权利要求1所述的半导体组件封装结构，其特征在于，还包含形成于该重分布层上的保护层。
6.一用于形成半导体组件封装的方法，其特征在于，包含：
提供一基板，该基板具有形成于其上表面预先形成芯片接收凹槽和/或终端接触垫；
利用取放精密对准系统将已知为良好的芯片以期望之间距重新分布于承载组件，其中该承载组件包含于该承载组件周围区域的胶合材料，以黏附该基板；
将该胶合材料黏附于芯片的背面；
将该基板接合于该芯片的背面，并予以固化后，自该基板分离该组件；
涂布介电层于该芯片与该基板上，随后执行真空程序；
形成开孔以暴露该芯片和/或该基板上的接触垫；
形成至少一导电增进层于该介电层之上；
形成连接结构于该至少一导电增进层之上；以及
形成保护层于该至少一导电增进层之上。
7.如权利要求6所述的方法，其特征在于，还包含形成耦合至该连接结构的导电凸块。
8.如权利要求6所述的方法，其特征在于，该介电层包含一弹性介电层、一感光层、一含硅型介电层、一聚亚酰胺层或一硅树脂层。
9.如权利要求6所述的方法，其特征在于，该基板的材料包含环氧树脂类型的耐高温玻璃纤维板、玻璃纤维板、双马来酰亚胺三氮杂苯树脂、硅、印刷电路板材料、玻璃、陶瓷、合金或金属，并且该合金包含合金42(包含42％镍与58％铁)或柯伐合金(包含29％镍、17％钴与54％铁)。
10.如权利要求6所述的方法，其特征在于，该至少一导电增进层是由合金所制成，其中该合金包含钛/铜/金合金或钛/铜/镍/金合金，并且该承载组件是由玻璃所制成。
CNA2007101994828A 2006-12-13 2007-12-13 具有良好热膨胀系数效能的圆片级封装及其方法 Pending CN101202253A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/609,970 US20080142946A1 (en) 2006-12-13 2006-12-13 Wafer level package with good cte performance
US11/609,970 2006-12-13

Publications (1)

Publication Number Publication Date
CN101202253A true CN101202253A (zh) 2008-06-18

Family

ID=39517320

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101994828A Pending CN101202253A (zh) 2006-12-13 2007-12-13 具有良好热膨胀系数效能的圆片级封装及其方法

Country Status (7)

Country Link
US (2) US20080142946A1 (zh)
JP (1) JP2008153668A (zh)
KR (1) KR20080055687A (zh)
CN (1) CN101202253A (zh)
DE (1) DE102007060313A1 (zh)
SG (1) SG144082A1 (zh)
TW (1) TWI353659B (zh)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101937895A (zh) * 2010-08-16 2011-01-05 日月光半导体制造股份有限公司 半导体封装件
CN101615584B (zh) * 2008-06-25 2011-06-15 南茂科技股份有限公司 芯片重新配置的封装方法
CN102348328A (zh) * 2011-09-15 2012-02-08 深南电路有限公司 芯片埋入方法和芯片埋入式电路板
CN101567344B (zh) * 2008-04-21 2012-03-21 宏齐科技股份有限公司 可达成正面电导通的半导体芯片封装结构及其制作方法
CN102598259A (zh) * 2009-11-10 2012-07-18 美士美积体产品公司 用于改善晶片级封装的可靠性的再分布层增强
CN103197227A (zh) * 2013-03-25 2013-07-10 西安华芯半导体有限公司 一种用于设计分析目的的晶圆测试方法
CN103219297A (zh) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 承载板、半导体封装件及其制法
CN103295978A (zh) * 2012-03-03 2013-09-11 矽品精密工业股份有限公司 半导体封装件及其制法
CN103632987A (zh) * 2012-08-24 2014-03-12 台湾积体电路制造股份有限公司 三维集成电路（3dic）堆叠的载体翘曲控制
CN103730428A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构
CN103890932A (zh) * 2011-11-22 2014-06-25 富士通株式会社 电子部件及其制造方法
CN104183504A (zh) * 2013-05-20 2014-12-03 矽品精密工业股份有限公司 半导体封装件的制法
CN108711564A (zh) * 2015-01-26 2018-10-26 日月光半导体制造股份有限公司 扇出晶片级封装结构
CN109119344A (zh) * 2017-06-23 2019-01-01 力成科技股份有限公司 半导体封装及半导体封装的制造工艺方法
CN111192832A (zh) * 2020-01-09 2020-05-22 甬矽电子(宁波)股份有限公司 芯片封装方法和芯片封装结构
US10734435B2 (en) 2017-04-18 2020-08-04 Gingy Technology Inc. Image capturing module and manufacturing method thereof
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7657348B2 (en) * 2005-12-30 2010-02-02 Canadian National Railway Company System and method for computing rail car switching solutions using dynamic classification track allocation
US8049323B2 (en) * 2007-02-16 2011-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip holder with wafer level redistribution layer
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
FR2917234B1 (fr) * 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
TWI360207B (en) * 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US20090230554A1 (en) * 2008-03-13 2009-09-17 Broadcom Corporation Wafer-level redistribution packaging with die-containing openings
KR101564278B1 (ko) 2008-06-13 2015-10-30 삼성전자 주식회사 액정표시장치
FR2934082B1 (fr) * 2008-07-21 2011-05-27 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice
KR101003678B1 (ko) * 2008-12-03 2010-12-23 삼성전기주식회사 웨이퍼 레벨 패키지와 그 제조방법 및 칩 재활용방법
US8119454B2 (en) * 2008-12-08 2012-02-21 Stmicroelectronics Asia Pacific Pte Ltd. Manufacturing fan-out wafer level packaging
WO2010106473A1 (en) * 2009-03-16 2010-09-23 Nxp B.V. Packaged semiconductor product and method for manufacture thereof
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
FR2947948B1 (fr) * 2009-07-09 2012-03-09 Commissariat Energie Atomique Plaquette poignee presentant des fenetres de visualisation
TWI466259B (zh) * 2009-07-21 2014-12-21 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
KR101095119B1 (ko) 2009-08-19 2011-12-16 삼성전기주식회사 다이 패키지 및 그 제조방법
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8476750B2 (en) * 2009-12-10 2013-07-02 Qualcomm Incorporated Printed circuit board having embedded dies and method of forming same
US8569894B2 (en) * 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8338934B2 (en) * 2010-03-18 2012-12-25 Marvell World Trade Ltd. Embedded die with protective interposer
TWI411075B (zh) * 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
JP5685012B2 (ja) * 2010-06-29 2015-03-18 新光電気工業株式会社 半導体パッケージの製造方法
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8397379B2 (en) * 2010-08-26 2013-03-19 Samsung Electro-Mechanics Co., Ltd. Method for fabricating ceramic substrate
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8597986B2 (en) * 2011-09-01 2013-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. System in package and method of fabricating same
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
JP2013197310A (ja) 2012-03-19 2013-09-30 Toshiba Corp 発光装置
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
TWI473217B (zh) * 2012-07-19 2015-02-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US8912087B2 (en) * 2012-08-01 2014-12-16 Infineon Technologies Ag Method of fabricating a chip package
US9576930B2 (en) * 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
CN104793026B (zh) * 2014-01-20 2018-09-28 旺矽科技股份有限公司 应用于探针测试装置的支撑结构及其制作方法
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
TWI559468B (zh) * 2015-05-29 2016-11-21 矽品精密工業股份有限公司 電子封裝結構及其承載件
KR102319186B1 (ko) 2015-06-12 2021-10-28 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US20180166356A1 (en) * 2016-12-13 2018-06-14 Globalfoundries Inc. Fan-out circuit packaging with integrated lid
US10529671B2 (en) 2016-12-13 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
TW201909245A (zh) 2017-07-24 2019-03-01 美商康寧公司 精密結構玻璃物件、積體電路封裝、光學元件、微流體元件及其製造方法
US10347509B1 (en) 2018-02-09 2019-07-09 Didrew Technology (Bvi) Limited Molded cavity fanout package without using a carrier and method of manufacturing the same
WO2019160566A1 (en) 2018-02-15 2019-08-22 Didrew Technology (Bvi) Limited Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener
US10734326B2 (en) 2018-02-15 2020-08-04 Didrew Technology (Bvi) Limited Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage
US20190259675A1 (en) * 2018-02-19 2019-08-22 Didrew Technology (Bvi) Limited Glass frame fan out packaging and method of manufacturing thereof
US10804254B2 (en) * 2018-06-29 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with cavity substrate
US10971446B2 (en) * 2018-11-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11302563B2 (en) 2019-06-20 2022-04-12 Corning Incorporated Carrier for back end of line processing
TWI756000B (zh) * 2020-12-28 2022-02-21 欣興電子股份有限公司 晶片封裝結構及其製作方法
CN113078149B (zh) * 2021-03-12 2023-11-10 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
CN113078148B (zh) * 2021-03-12 2024-03-26 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
CN113097201B (zh) * 2021-04-01 2023-10-27 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
CN113453475A (zh) * 2021-06-28 2021-09-28 贵州航天电子科技有限公司 一种用于引信产品的封装工装及封装工艺

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
US7349223B2 (en) * 2000-05-23 2008-03-25 Nanonexus, Inc. Enhanced compliant probe card systems having improved planarity
US6917525B2 (en) * 2001-11-27 2005-07-12 Nanonexus, Inc. Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6559464B1 (en) * 1999-11-15 2003-05-06 Axsun Technologies, Inc. Optical system active alignment process including alignment structure attach, position search, and deformation
EP1556895A4 (en) * 2002-10-08 2009-12-30 Chippac Inc SEMICONDUCTOR STACKED MULTIPLE CAPSULATION MODULE WITH INVERTED SECOND CAPACITY
US7368810B2 (en) * 2003-08-29 2008-05-06 Micron Technology, Inc. Invertible microfeature device packages
US7334946B2 (en) * 2005-12-21 2008-02-26 Intel Corporation Passively aligned optical-electrical interface with microlenses

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101567344B (zh) * 2008-04-21 2012-03-21 宏齐科技股份有限公司 可达成正面电导通的半导体芯片封装结构及其制作方法
CN101615584B (zh) * 2008-06-25 2011-06-15 南茂科技股份有限公司 芯片重新配置的封装方法
CN102598259A (zh) * 2009-11-10 2012-07-18 美士美积体产品公司 用于改善晶片级封装的可靠性的再分布层增强
CN102598259B (zh) * 2009-11-10 2016-05-18 马克西姆综合产品公司 用于改善晶片级封装的可靠性的再分布层增强
CN101937895B (zh) * 2010-08-16 2012-08-22 日月光半导体制造股份有限公司 半导体封装件
CN101937895A (zh) * 2010-08-16 2011-01-05 日月光半导体制造股份有限公司 半导体封装件
CN102348328A (zh) * 2011-09-15 2012-02-08 深南电路有限公司 芯片埋入方法和芯片埋入式电路板
CN102348328B (zh) * 2011-09-15 2015-05-13 深南电路股份有限公司 芯片埋入方法和芯片埋入式电路板
CN103890932A (zh) * 2011-11-22 2014-06-25 富士通株式会社 电子部件及其制造方法
CN103890932B (zh) * 2011-11-22 2017-03-29 富士通株式会社 电子部件及其制造方法
CN103219297A (zh) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 承载板、半导体封装件及其制法
CN103295978A (zh) * 2012-03-03 2013-09-11 矽品精密工业股份有限公司 半导体封装件及其制法
CN103632987B (zh) * 2012-08-24 2019-06-21 台湾积体电路制造股份有限公司 三维集成电路（3dic）堆叠的载体翘曲控制
US10825693B2 (en) 2012-08-24 2020-11-03 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
CN103632987A (zh) * 2012-08-24 2014-03-12 台湾积体电路制造股份有限公司 三维集成电路（3dic）堆叠的载体翘曲控制
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
US10290513B2 (en) 2012-08-24 2019-05-14 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
CN103197227A (zh) * 2013-03-25 2013-07-10 西安华芯半导体有限公司 一种用于设计分析目的的晶圆测试方法
CN104183504B (zh) * 2013-05-20 2017-04-12 矽品精密工业股份有限公司 半导体封装件的制法
CN104183504A (zh) * 2013-05-20 2014-12-03 矽品精密工业股份有限公司 半导体封装件的制法
CN103730428A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构
CN108711564A (zh) * 2015-01-26 2018-10-26 日月光半导体制造股份有限公司 扇出晶片级封装结构
CN108711564B (zh) * 2015-01-26 2021-10-15 日月光半导体制造股份有限公司 扇出晶片级封装结构
US10734435B2 (en) 2017-04-18 2020-08-04 Gingy Technology Inc. Image capturing module and manufacturing method thereof
CN109119344A (zh) * 2017-06-23 2019-01-01 力成科技股份有限公司 半导体封装及半导体封装的制造工艺方法
CN111192832A (zh) * 2020-01-09 2020-05-22 甬矽电子(宁波)股份有限公司 芯片封装方法和芯片封装结构
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Also Published As

Publication number Publication date
US7655501B2 (en) 2010-02-02
US20080142946A1 (en) 2008-06-19
DE102007060313A1 (de) 2008-08-28
TW200832644A (en) 2008-08-01
SG144082A1 (en) 2008-07-29
JP2008153668A (ja) 2008-07-03
KR20080055687A (ko) 2008-06-19
TWI353659B (en) 2011-12-01
US20080248614A1 (en) 2008-10-09

Similar Documents

Publication Publication Date Title
CN101202253A (zh) 具有良好热膨胀系数效能的圆片级封装及其方法
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US8178964B2 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US8115297B2 (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US8178963B2 (en) Wafer level package with die receiving through-hole and method of the same
US7812434B2 (en) Wafer level package with die receiving through-hole and method of the same
TWI533412B (zh) 半導體元件封裝結構及其形成方法
US20080083980A1 (en) Cmos image sensor chip scale package with die receiving through-hole and method of the same
US20080157358A1 (en) Wafer level package with die receiving through-hole and method of the same
US20080217761A1 (en) Structure of semiconductor device package and method of the same
US20080237828A1 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
CN101188220A (zh) 具晶粒接收凹孔的晶片级封装
US20080211075A1 (en) Image sensor chip scale package having inter-adhesion with gap and method of the same
KR20080077934A (ko) 축소된 구조를 갖는 멀티칩 패키지 및 그 형성 방법
KR20080075450A (ko) 다이 수용 캐비티를 갖는 웨이퍼 레벨 이미지 센서 패키지및 그 방법
TWI409923B (zh) 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法
CN101728368A (zh) 具有多晶粒的半导体组件封装结构及其方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication