CN103295978A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN103295978A
CN103295978A CN2012101096765A CN201210109676A CN103295978A CN 103295978 A CN103295978 A CN 103295978A CN 2012101096765 A CN2012101096765 A CN 2012101096765A CN 201210109676 A CN201210109676 A CN 201210109676A CN 103295978 A CN103295978 A CN 103295978A
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layer
semiconductor package
making
package part
chip
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张江城
李孟宗
黄荣邦
邱世冠
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件的制法包括：形成离型层于一表面具凹部的承载板上；置放芯片于该凹部内的离型层上；形成封装胶体于该芯片与离型层上；形成接着层于该封装胶体上；移除该离型层与承载板；以及形成线路结构于该封装胶体与芯片上。借由离型层对芯片及封装胶体仅具些微粘性的特性，以避免因热膨胀系数不同而使整体结构在后续工艺的温度循环中发生翘曲。

Description

半导体封装件及其制法
技术领域
本发明关于半导体封装件及其制法，特别是关于一种提升可靠度的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微型化(miniaturization)的封装需求，发展出晶圆级封装(Wafer Level Packaging，WLP)的技术。
第6452265号美国专利与第7202107号美国专利提供一种晶圆级封装的制法。请参阅图1A至图1E，其为现有半导体封装件1的制法的剖面示意图。
如图1A所示，形成一热化离型胶层(thermal release tape)11于一承载板10上，该热化离型胶层11具有遇热失去粘性的特性。
如图1B所示，置放多个芯片12于该热化离型胶层11上，这些芯片12具有相对的作用面12a与非作用面12b，各该作用面12a上均具有多个电极垫120，且各该作用面12a结合于该热化离型胶层11上。
如图1C所示，以模压(molding)方式形成一封装胶体13于该芯片12与该热化离型胶层11上。
如图1D所示，加热移除该热化离型胶层11与该承载板10，以外露该芯片12的作用面12a。
如图1E所示，形成一线路结构14于该封装胶体13与该芯片12的作用面12a上，令该线路结构14电性连接该芯片12的电极垫120。
然而，现有半导体封装件1的制法中，该热化离型胶层11具有粘性，又该热化离型胶层11与承载板10热膨胀系数(Coefficient ofthermal expansion，CTE)差异过大，所以在封装胶体13形成后，往往使整体结构在温度循环中发生翘曲(warpage)，导致产品的可靠度不佳。
此外，使用热化离型胶层11涂布于该承载板10上的工艺，不利于将该热化离型胶层11均匀涂布于大版面尺寸的承载板10上，所以多选择涂布于小版面尺寸的承载板10上以达均匀涂布的需求。然而，若将热化离型胶层11涂布于小版面尺寸的承载板10上，不仅输送设备(图略)不便输送小版面尺寸的承载板10，且难以提高生产效率。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺点，本发明的主要目的在于提供一种半导体封装件及其制法，以避免因热膨胀系数不同而使整体结构在后续工艺的温度循环中发生翘曲。
本发明的半导体封装件包括：封装胶体，其具有相对的第一表面与第二表面，且该第一表面上形成有凸部；芯片，其嵌埋于该封装胶体中，该芯片具有相对的作用面与非作用面，该作用面上具有多个电极垫，且该作用面与电极垫外露于该凸部；线路结构，形成于该封装胶体的第一表面与该芯片的作用面上，令该线路结构电性连接该芯片的电极垫；以及接着层，形成于该封装胶体的第二表面上。
本发明还提供一种半导体封装件的制法，包括：提供一表面具有凹部的承载板，且该承载板的具有该凹部的表面上形成有离型层；置放芯片于该凹部内的离型层上，该芯片具有相对的作用面与非作用面，该作用面上具有多个电极垫，且该作用面结合于该离型层上；形成封装胶体于该芯片与该离型层上；形成接着层于该封装胶体上；移除该离型层与该承载板，以外露该芯片的作用面；以及形成线路结构于该封装胶体与该芯片的作用面上，令该线路结构电性连接该芯片的电极垫。
前述的制法中，形成该承载板的材质可为玻璃或金属，且形成该离型层的材质可为疏水性材质、无机物或高分子聚合物。
前述的制法中，可以电浆辅助化学气相沉积的方式形成该离型层，且可以压合方式形成该接着层。
前述的制法还可包括切单工艺，以分离出多个该半导体封装件。
前述的制法于移除该离型层与该承载板的步骤前，还可包括形成一分隔层于该接着层上，其中，该分隔层位于一支撑板上，以令该分隔层夹置于该支撑板与该接着层之间。例如：在该封装胶体上形成该接着层的步骤前，可先令该分隔层夹置于该支撑板与该接着层之间。其中，该分隔层对该支撑板与该接着层不具粘性。
因此，该分隔层可经图案化形成缝隙，再埋设该分隔层于该接着层中，使部分该接着层位于该缝隙中，以令该接着层结合该支撑板，而形成该线路结构之后，可沿对应该缝隙的切割路径进行切割，以分离该分隔层与该支撑板，且分离出多个该半导体封装件。或者，该分隔层的面积可小于该接着层与该支撑板的面积，使部分该接着层包覆该分隔层的边缘，以令该接着层结合至该支撑板的边缘，而形成该线路结构之后，可对应该芯片进行切单工艺，并沿该分隔层边缘进行切割，以分离该支撑板与分隔层，且分离出多个该半导体封装件。
前述的半导体封装件及其制法中，形成该接着层的材质可为聚酰亚胺、干膜或半干材。
前述的半导体封装件及其制法中，该线路结构可具有设于该封装胶体与该作用面上的至少一介电层、形成于该介电层上的线路层、及形成于该介电层中的导电盲孔，且该导电盲孔电性连接该线路层与该电极垫。
依上述结构及其制法，最外层的介电层上可形成有绝缘层，该绝缘层具有开孔，以令该线路层的部分表面外露于该开孔，可供结合导电组件。
另外，于其它实施例中，该线路结构可具有设于该封装胶体上的至少一介电层、及形成于该介电层与该作用面上的线路层，且该线路层电性连接该芯片的电极垫。
由上可知，本发明半导体封装件及其制法，借由该离型层对芯片及封装胶体仅具些微粘性，以避免因热膨胀系数(CTE)不同而使整体结构在温度循环中发生翘曲。此外，以电浆辅助化学气相沉积的方式，该离型层容易形成于大版面的承载板上，所以可便于输送，且可提高生产效率。
附图说明
图1A至图1E为现有半导体封装件的制法的剖面示意图；以及
图2A至图2H为本发明的半导体封装件的制法的剖面示意图；其中，图2E’为图2E的另一实施例，图2G’、图2G”及图2H’为图2G及图2H的其它实施例。
主要组件符号说明
1，2，2’     半导体封装件
10，20        承载板
11            热化离型胶层
12，22        芯片
12a，22a      作用面
12b，22b      非作用面
120，220      电极垫
13，23        封装胶体
14，24        线路结构
200           凹部
21            离型层
23a           第一表面
23b           第二表面
230           凸部
240           介电层
241           线路层
242           导电盲孔
25            绝缘层
250           开孔
26            导电组件
27            接着层
28，28’      分隔层
280           缝隙
29            支撑板
L，L’，L”       切割线。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相关的改变或调整，在无实质变更技术内容下，也当视为本发明可实施的范畴。
请参阅图2A至图2H，其为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，提供表面上具有多个凹部200的一承载板20上。在本实施例中，形成该承载板20的材质为玻璃或金属，且各该凹部200为数组排形成于该承载板20上。
如图2B所示，形成一离型层21于该承载板20表面与这些凹部200表面上。
在本实施例中，利用电浆辅助化学气相沉积(Plasma-EnhancedChemical Vapor Deposition，PECVD)的方式形成该离型层21，且形成该离型层21的材质为疏水性材质、无机物或高分子聚合物，如聚对二甲苯(Poly-para-xylylene，parylene)。
此外，利用电浆辅助化学气相沉积方式形成该离型层21，较容易形成于大版面尺寸的承载板20上，因而不仅便于输送大版面的承载板20，且可提高生产效率。
如图2C所示，置放多个芯片22于各该凹部200的离型层21上，各该芯片22具有相对的作用面22a与非作用面22b，该作用面22a上具有多个电极垫220，且该作用面22a结合于该离型层21上。
本发明借由形成凹部200，以利于芯片22对位置放，因而可避免芯片22的位置偏移，且该离型层21对该芯片22仅具些微粘性，所以相比于现有技术的热化离型胶层，该离型层21的热膨胀系数(CTE)也不会造成芯片22位置偏移过大的问题。因此，本发明的制法可使芯片22的位置固定，因而可提升产品后续工艺的可靠度。
如图2D所示，以压合或涂布的方式形成一封装胶体23于该芯片22与该离型层21上，以包覆该芯片22。
在本实施例中，形成该封装胶体23的材质可为聚酰亚胺(Polyimide，PI)，并无特别限制，但该离型层21对该封装胶体23具有黏性。
如图2D及图2E所示，借由一支撑板29，以压合方式形成一接着层27于该封装胶体23上，且压合一分隔层28于该接着层27中。
在本实施例中，该接着层27的厚度可为10至100um，且形成该接着层27的材质为聚酰亚胺(Polyimide，PI)、干膜(dry film)或半干材，而形成该支撑板29的材质为玻璃。
此外，该分隔层28对该接着层27(如PI)与该支撑板29(如玻璃)均不具粘性，而接着层27(如PI)与该支撑板29(如玻璃)具粘性，所以于工艺中，需先将该分隔层28进行图案化工艺以形成缝隙280，再进行压合，使该接着层27压入该缝隙280中以结合该支撑板29。
此外，在本实施例中，同时压合该接着层27、图案化的分隔层28与支撑板29，如图2D所示。而于其它实施例中，也可先将该接着层27形成于该封装胶体23上，再借由该支撑板29将图案化的分隔层28压入该接着层27中。
另外，在另一实施例中，可借由尺寸设计，使该接着层27结合该支撑板29。如图2E’所示，该分隔层28’的面积小于该接着层27的面积及该支撑板29的面积，当进行压合作业时，部分该接着层27将受压包覆该分隔层28’的边缘，以令该接着层27结合至该支撑板29的边缘。
如图2F所示，移除该离型层21与该承载板20，以外露该芯片22的作用面22a，且使该封装胶体23具有凸部230。
在本实施例中，先剥除该承载板20，再以电浆(plasma)方式移除该离型层21。因此，本发明的制法中，可不需依靠加热方式即可移除该离型层21，所以可避免整体结构在温度循环中发生翘曲的问题。
此外，于此移除阶段的工艺，因需将整体结构移至另一机台上，且翻面进行移除作业，所以于前一步骤须设置该支撑板29，以令该支撑板29于此阶段作承载之用。
如图2G所示，形成一线路结构24于该封装胶体23与该芯片22的作用面22a上，令该线路结构24电性连接该芯片22的电极垫220。
在本实施例中，该线路结构24具有设于该封装胶体23与该作用面22a上的至少一介电层240、形成于该介电层240上的线路层241、及形成于该介电层240中的导电盲孔242，且该导电盲孔242电性连接该线路层241与该电极垫220。接着，形成一绝缘层25于该最外层的介电层240上，该绝缘层25具有多个开孔250，以令该线路层241的部分表面对应外露于各该开孔250，以供结合导电组件26。
所述的介电层240可依需求为多层，而增加线路层241的功能。所述的绝缘层25的厚度可为30至500um，且该绝缘层25的材质可为二氧化硅(SiO2)或氮化硅(silicon nitrate)以作为钝化层(passivationlayer)。该绝缘层25的材质也可为聚酰亚胺(Polyimide，PI)或如聚对二唑苯(Polybenzoxazole，PBO)的补强材。
此外，该导电组件26可为焊球、凸块或焊针等，并无特别限制。
另外，在其它实施例中，如图2G’所示，该线路结构24也可具有设于该封装胶体23与该作用面22a上的至少一介电层240及形成于该介电层240上的线路层241，且该线路层241电性连接该芯片22的电极垫220。
本发明借由压合或涂布的方式形成该封装胶体23，取代现有模压方式，以包覆该芯片22，再以图案化方式形成大版面的线路结构24，可有效降低制作成本。
如图2H或图2H’所示，利用激光或刀具等切割工具，沿对应该缝隙280的切割线L(如图2F所示)进行切单工艺，以切割出多个半导体封装件2，2’。
在本实施例中，借由图案化该分隔层28所形成的缝隙280，以于切割时，使该接着层27不再粘住该支撑板29，所以可一并分离移除该支撑板29与分隔层28。因此，本发明利用支撑板29、分隔层28与接着层27所构成的三明治结构，以于切割完成后，便于取出各该半导体封装件2。
在另一实施例中，若以图2E’进行后续工艺，于切割时，沿对应该芯片22周围的切割线L’(如图2G”所示)进行切单工艺，且还需沿该分隔层28’边缘的切割线L”(如图2G”所示)进行切单工艺，以完全分离移除该支撑板29与分隔层28。
本发明提供一种半导体封装件2，2’，包括：具有相对的第一表面23a与第二表面23b的封装胶体23、嵌入该封装胶体23中的一芯片22、形成于该封装胶体23上的一线路结构24、以及形成于该封装胶体23的第二表面23b上的一接着层27。
所述的封装胶体23的第一表面23a上具有一凸部230。
所述的芯片22嵌入该凸部230中且具有相对的作用面22a与非作用面22b，该作用面22a上具有多个电极垫220，且该作用面22a与这些电极垫220外露于该封装胶体23的凸部230表面。
所述的接着层27的材质为聚酰亚胺、干膜或半干材。
所述的线路结构24还形成于该第一表面23a与芯片22的作用面22a上，令该线路结构24电性连接该电极垫220。其中，该线路结构24具有设于该封装胶体23与该作用面22a上的至少一介电层240、形成于该介电层240上的线路层241、及形成于该介电层240中的导电盲孔242，且该导电盲孔242电性连接该线路层241与该电极垫220。
或者，该线路结构24具有设于该封装胶体23与该作用面22a上的至少一介电层240及形成于该介电层240上的线路层241，且该线路层241电性连接该芯片22的电极垫220。
此外，该最外层的介电层240上形成有一绝缘层25，该绝缘层25具有多个开孔250，以令该线路层241的部分表面外露于各该开孔250，以供结合导电组件26。另外，在其它实施例中，该线路结构24也可为多层线路层的结构。
综上所述，本发明的半导体封装件及其制法，借由离型层对芯片与封装胶体仅具些微粘性，以避免整体结构发生翘曲，所以有效提升产品的可靠度。
此外，该离型层较容易形成于大版面的承载板上，因而便于输送，且可提高生产效率。
此外，借由压合或涂布的方式形成该封装胶体，再以图案化方式形成大版面的线路结构，以达到降低制作成本的目的。
另外，借由该分隔层的物理特性(粘性)与图案化设计，以于切割完成后，便于拿取该半导体封装件。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种半导体封装件，其特征在于，该半导体封装件包括：
封装胶体，具有相对的第一表面与第二表面，且该第一表面上形成有凸部；
芯片，嵌埋于该封装胶体中，该芯片具有相对的作用面与非作用面，该作用面上具有多个电极垫，且该作用面与电极垫外露于该凸部；
线路结构，形成于该封装胶体的第一表面与该芯片的作用面上，令该线路结构电性连接该芯片的电极垫；以及
接着层，形成于该封装胶体的第二表面上。
2.根据权利要求1所述的半导体封装件，其特征在于，该线路结构具有设于该封装胶体与该作用面上的至少一介电层、形成于该介电层上的线路层、及形成于该介电层中的导电盲孔，且该导电盲孔电性连接该线路层与该电极垫。
3.根据权利要求2所述的半导体封装件，其特征在于，该最外层的介电层上形成有绝缘层，该绝缘层具有开孔，以令该线路层的部分表面外露于该开孔，以供结合导电组件。
4.根据权利要求1所述的半导体封装件，其特征在于，该线路结构具有设于该封装胶体上的至少一介电层、及形成于该介电层与该作用面上的线路层，且该线路层电性连接该芯片的电极垫。
5.根据权利要求1所述的半导体封装件，其特征在于，形成该接着层的材质为聚酰亚胺、干膜或半干材。
6.一种半导体封装件的制法，其特征在于，该半导体封装件的制法包括：
提供一表面具有凹部的承载板，且该承载板的具有该凹部的表面上形成有离型层；
置放芯片于该凹部内的离型层上，该芯片具有相对的作用面与非作用面，该作用面上具有多个电极垫，且该作用面结合于该离型层上；
形成封装胶体于该芯片与该离型层上；
形成接着层于该封装胶体上；
移除该离型层与该承载板，以外露该芯片的作用面；以及
形成线路结构于该封装胶体与该芯片的作用面上，令该线路结构电性连接该芯片的电极垫。
7.根据权利要求6所述的半导体封装件的制法，其特征在于，形成该承载板的材质为玻璃或金属。
8.根据权利要求6所述的半导体封装件的制法，其特征在于，形成该离型层的材质为疏水性材质、无机物或高分子聚合物。
9.根据权利要求6所述的半导体封装件的制法，其特征在于，是以电浆辅助化学气相沉积的方式形成该离型层。
10.根据权利要求6所述的半导体封装件的制法，其特征在于，是以压合方式形成该接着层。
11.根据权利要求6所述的半导体封装件的制法，其特征在于，形成该接着层的材质为聚酰亚胺、干膜或半干材。
12.根据权利要求6所述的半导体封装件的制法，其特征在于，该线路结构具有设于该封装胶体与该作用面上的至少一介电层、形成于该介电层上的线路层、及形成于该介电层中的导电盲孔，且该导电盲孔电性连接该线路层与该电极垫。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，该最外层的介电层上形成有绝缘层，该绝缘层具有开孔，以令该线路层的部分表面外露于该开孔，以供结合导电组件。
14.根据权利要求6所述的半导体封装件的制法，其特征在于，该线路结构具有设于该封装胶体上的至少一介电层、及形成于该介电层与该作用面上的线路层，且该线路层电性连接该芯片的电极垫。
15.根据权利要求6所述的半导体封装件的制法，其特征在于，在移除该离型层与该承载板的步骤前，还包括下列步骤：
形成一分隔层于该接着层上，其中，该分隔层位于一支撑板上，以令该分隔层夹置于该支撑板与该接着层之间。
16.根据权利要求15所述的半导体封装件的制法，其特征在于，在该封装胶体上形成该接着层的步骤前，先令该分隔层夹置于该支撑板与该接着层之间。
17.根据权利要求15所述的半导体封装件的制法，其特征在于，该分隔层对该支撑板与该接着层不具粘性。
18.根据权利要求15所述的半导体封装件的制法，其特征在于，该分隔层经图案化形成缝隙，再埋设该分隔层于该接着层中，使部分该接着层位于该缝隙中，以令该接着层结合该支撑板。
19.根据权利要求18所述的半导体封装件的制法，其特征在于，该制法还包括形成该线路结构之后，沿对应该缝隙的切割路径进行切割，以分离该分隔层与该支撑板，且分离出多个该半导体封装件。
20.根据权利要求15所述的半导体封装件的制法，其特征在于，该分隔层的面积小于该接着层与该支撑板的面积，使部分该接着层包覆该分隔层的边缘，以令该接着层结合至该支撑板的边缘。
21.根据权利要求20所述的半导体封装件的制法，其特征在于，该制法还包括形成该线路结构之后，对应该芯片进行切单工艺，且沿该分隔层边缘进行切割，以分离该支撑板与分隔层，且分离出多个该半导体封装件。
22.根据权利要求6所述的半导体封装件的制法，其特征在于，该制法还包括进行切单工艺，以分离出多个该半导体封装件。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637853A (zh) * 2013-11-14 2015-05-20 上海华虹宏力半导体制造有限公司 硅片的临时键合工艺方法
CN104637855A (zh) * 2013-11-06 2015-05-20 矽品精密工业股份有限公司 半导体封装件的制法
CN104979260A (zh) * 2014-04-03 2015-10-14 矽品精密工业股份有限公司 半导体封装件的制法及其所用的支撑件
CN105575918A (zh) * 2014-09-26 2016-05-11 矽品精密工业股份有限公司 半导体封装件及其制法
CN111430249A (zh) * 2020-03-05 2020-07-17 广东工业大学 一种抑制芯片漂移与翘曲的封装方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI500090B (zh) * 2012-11-13 2015-09-11 矽品精密工業股份有限公司 半導體封裝件之製法
TWI566348B (zh) * 2014-09-03 2017-01-11 矽品精密工業股份有限公司 封裝結構及其製法
TWI573231B (zh) * 2015-07-17 2017-03-01 矽品精密工業股份有限公司 封裝基板及其製法
US9806030B2 (en) * 2015-10-28 2017-10-31 Indiana Integrated Circuits, LLC Prototyping of electronic circuits with edge interconnects
US9947570B2 (en) * 2015-12-30 2018-04-17 International Business Machines Corporation Handler bonding and debonding for semiconductor dies
US10224219B2 (en) 2015-12-30 2019-03-05 International Business Machines Corporation Handler bonding and debonding for semiconductor dies
CN106374055B (zh) * 2016-10-19 2019-04-30 深圳市华星光电技术有限公司 Oled显示面板的制作方法
JP6834469B2 (ja) * 2016-12-27 2021-02-24 日亜化学工業株式会社 発光装置及びその製造方法
US10811298B2 (en) * 2018-12-31 2020-10-20 Micron Technology, Inc. Patterned carrier wafers and methods of making and using the same
KR20210044654A (ko) 2019-10-15 2021-04-23 에스케이하이닉스 주식회사 웨이퍼 지지 구조체
TWI718801B (zh) * 2019-12-06 2021-02-11 矽品精密工業股份有限公司 電子封裝件之製法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281047B1 (en) * 2000-11-10 2001-08-28 Siliconware Precision Industries, Co., Ltd. Method of singulating a batch of integrated circuit package units constructed on a single matrix base
TW543129B (en) * 2000-08-30 2003-07-21 Hitachi Ltd A semiconductor device and a method of manufacturing the same
CN101192544A (zh) * 2006-11-23 2008-06-04 全懋精密科技股份有限公司 半导体元件埋入承载板的叠接结构及其制法
CN101202253A (zh) * 2006-12-13 2008-06-18 育霈科技股份有限公司 具有良好热膨胀系数效能的圆片级封装及其方法
CN101290893A (zh) * 2007-04-16 2008-10-22 日月光半导体制造股份有限公司 传感器芯片的封胶方法
CN101436553A (zh) * 2007-11-16 2009-05-20 南茂科技股份有限公司 芯片重新配置的封装结构中使用金属凸块的制造方法
CN101546718A (zh) * 2008-02-01 2009-09-30 英飞凌科技股份有限公司 半导体装置封装和制造半导体装置封装的方法
CN101794853A (zh) * 2008-12-11 2010-08-04 精材科技股份有限公司 芯片封装体及其形成方法
CN102157392A (zh) * 2011-01-31 2011-08-17 江阴长电先进封装有限公司 低成本芯片扇出结构的封装方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
DE1025587T1 (de) * 1997-07-21 2001-02-08 Aguila Technologies Inc Halbleiter-flipchippackung und herstellungsverfahren dafür
US6452265B1 (en) 2000-01-28 2002-09-17 International Business Machines Corporation Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion
JP3815239B2 (ja) * 2001-03-13 2006-08-30 日本電気株式会社 半導体素子の実装構造及びプリント配線基板
DE10334576B4 (de) 2003-07-28 2007-04-05 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse
US7176563B2 (en) * 2003-09-18 2007-02-13 International Business Machine Corporation Electronically grounded heat spreader
US7221055B2 (en) * 2005-05-23 2007-05-22 Texas Instruments Incorporated System and method for die attach using a backside heat spreader
KR101049390B1 (ko) * 2005-12-16 2011-07-14 이비덴 가부시키가이샤 다층 프린트 배선판 및 그 제조 방법
TWI364801B (en) * 2007-12-20 2012-05-21 Chipmos Technologies Inc Dice rearrangement package structure using layout process to form a compliant configuration
US7964450B2 (en) * 2008-05-23 2011-06-21 Stats Chippac, Ltd. Wirebondless wafer level package with plated bumps and interconnects
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8722537B2 (en) * 2009-03-19 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-sacrificial layer and method
JP5584011B2 (ja) * 2010-05-10 2014-09-03 新光電気工業株式会社 半導体パッケージの製造方法
JP5685012B2 (ja) * 2010-06-29 2015-03-18 新光電気工業株式会社 半導体パッケージの製造方法
TWI492349B (zh) * 2010-09-09 2015-07-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
TWI508245B (zh) * 2010-10-06 2015-11-11 矽品精密工業股份有限公司 嵌埋晶片之封裝件及其製法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW543129B (en) * 2000-08-30 2003-07-21 Hitachi Ltd A semiconductor device and a method of manufacturing the same
US6281047B1 (en) * 2000-11-10 2001-08-28 Siliconware Precision Industries, Co., Ltd. Method of singulating a batch of integrated circuit package units constructed on a single matrix base
CN101192544A (zh) * 2006-11-23 2008-06-04 全懋精密科技股份有限公司 半导体元件埋入承载板的叠接结构及其制法
CN101202253A (zh) * 2006-12-13 2008-06-18 育霈科技股份有限公司 具有良好热膨胀系数效能的圆片级封装及其方法
CN101290893A (zh) * 2007-04-16 2008-10-22 日月光半导体制造股份有限公司 传感器芯片的封胶方法
CN101436553A (zh) * 2007-11-16 2009-05-20 南茂科技股份有限公司 芯片重新配置的封装结构中使用金属凸块的制造方法
CN101546718A (zh) * 2008-02-01 2009-09-30 英飞凌科技股份有限公司 半导体装置封装和制造半导体装置封装的方法
CN101794853A (zh) * 2008-12-11 2010-08-04 精材科技股份有限公司 芯片封装体及其形成方法
CN102157392A (zh) * 2011-01-31 2011-08-17 江阴长电先进封装有限公司 低成本芯片扇出结构的封装方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637855A (zh) * 2013-11-06 2015-05-20 矽品精密工业股份有限公司 半导体封装件的制法
CN104637855B (zh) * 2013-11-06 2018-08-17 矽品精密工业股份有限公司 半导体封装件的制法
CN104637853A (zh) * 2013-11-14 2015-05-20 上海华虹宏力半导体制造有限公司 硅片的临时键合工艺方法
CN104979260A (zh) * 2014-04-03 2015-10-14 矽品精密工业股份有限公司 半导体封装件的制法及其所用的支撑件
CN104979260B (zh) * 2014-04-03 2019-02-12 矽品精密工业股份有限公司 半导体封装件的制法及其所用的支撑件
CN105575918A (zh) * 2014-09-26 2016-05-11 矽品精密工业股份有限公司 半导体封装件及其制法
CN105575918B (zh) * 2014-09-26 2019-01-04 矽品精密工业股份有限公司 半导体封装件及其制法
CN111430249A (zh) * 2020-03-05 2020-07-17 广东工业大学 一种抑制芯片漂移与翘曲的封装方法
CN111430249B (zh) * 2020-03-05 2022-02-22 广东工业大学 一种抑制芯片漂移与翘曲的封装方法

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