CN104347528A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN104347528A
CN104347528A CN201310348855.9A CN201310348855A CN104347528A CN 104347528 A CN104347528 A CN 104347528A CN 201310348855 A CN201310348855 A CN 201310348855A CN 104347528 A CN104347528 A CN 104347528A
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semiconductor package
semiconductor
making
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package parts
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CN104347528B (zh
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马光华
邱世冠
陈仕卿
柯俊吉
吕长伦
卢俊宏
陈贤文
林畯棠
赖顗喆
邱启新
曾文聪
袁宗德
程吕义
叶懋华
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，先置放半导体组件于一承载件的凹部中，再形成粘着材于该凹部中与该半导体组件周围，之后形成介电层于该粘着材与半导体组件上，且形成线路层于该介电层上，使该线路层电性连接该半导体组件，最后移除该承载件的凹部下方的部分，以保留该承载件的凹部侧壁的部分，以供作为支撑部。本发明的制法藉由无需制作现有硅中介板的方式，以降低该半导体封装件的制作成本。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种具晶圆级线路的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，例如芯片尺寸构装(ChipScale Package,CSP)、芯片直接贴附封装(Direct Chip Attached,DCA)或多芯片模块封装(Multi－Chip Module,MCM)等覆晶型态的封装模块、或将芯片立体堆栈化整合为三维集成电路(3D IC)芯片堆栈技术等。
第1图为现有半导体封装件1的剖面示意图，该半导体封装件1于一封装基板18与半导体芯片11之间设置一硅中介板（ThroughSilicon interposer,TSI）10，该硅中介板10具有导电硅穿孔（Through-silicon via,TSV）100及设于该导电硅穿孔100上的线路重布结构（Redistribution layer,RDL）15，令该线路重布结构15藉由多个导电组件17电性结合间距较大的封装基板18的焊垫180，并形成粘着材12包覆该些导电组件17，而间距较小的半导体芯片11的电极垫110藉由多个焊锡凸块19电性结合该导电硅穿孔100。之后，再形成粘着材12包覆该些焊锡凸块19。
若该半导体芯片11直接结合至该封装基板18上，因半导体芯片11与封装基板18两者的热膨胀系数的差异甚大，所以半导体芯片11外围的焊锡凸块19不易与封装基板18上对应的焊垫180形成良好的接合，致使焊锡凸块19自封装基板18上剥离。另一方面，因半导体芯片11与封装基板18之间的热膨胀系数不匹配(mismatch)，其所产生的热应力(thermal stress)与翘曲(warpage)的现象也日渐严重，致使半导体芯片11与封装基板18之间的电性连接可靠度(reliability)下降，且将造成信赖性测试的失败。
因此，藉由半导体基材制作的硅中介板10的设计，其与该半导体芯片11的材质接近，所以可有效避免上述所产生的问题。
然而，前述现有半导体封装件1的制法中，于制作该硅中介板10时，需形成该导电硅穿孔100，而该导电硅穿孔100的制程需于该硅中介板10上挖孔及金属填孔，致使该导电硅穿孔100的整体制程占整个该硅中介板10的制作成本达约40～50%（以12吋晶圆为例，不含人工成本），以致于最终产品的成本及价格难以降低。
此外，该硅中介板10的制作技术难度高，致使该半导体封装件1的生产量相对降低，且制作良率降低。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的为提供一种半导体封装件及其制法，以降低该半导体封装件的制作成本。
本发明的半导体封装件，包括：半导体组件，其具有相对的作用侧与非作用侧、及相邻接该作用侧与该非作用侧的侧面；粘着材，其设于该半导体组件的侧面周围；介电层，其设于该粘着材与半导体组件的作用侧上方；以及线路层，其设于该介电层上并电性连接该半导体组件。
前述的半导体封装件中，还包括包围该粘着材的支撑部，例如，该支撑部为含硅框体，且该半导体组件的厚度大于或未大于该支撑部的高度。
本发明还提供一种半导体封装件的制法，包括：置放一半导体组件于一承载件的凹部中，该半导体组件具有相对的作用侧与非作用侧、及相邻接该作用侧与该非作用侧的侧面；形成粘着材于该凹部中与该半导体组件的侧面周围；形成介电层于该粘着材与半导体组件的作用侧上方；形成线路层于该介电层上，且该线路层电性连接该半导体组件；以及移除该承载件的凹部下方的部分，以保留该承载件的凹部侧壁的部分，以供作为支撑部。
前述的制法中，该承载件为含硅的板体。
前述的制法中，该承载件具有多个个该凹部，以于移除该承载件的凹部下方的部分后，进行切单制程，例如，该切单制程同时移除该支撑部。
前述的制法中，该凹部的深度至多为该承载件的厚度的一半。
前述的制法中，该半导体组件凸伸或未凸伸出该凹部。
前述的制法中，该半导体组件的非作用侧藉由结合层结合至该凹部中，例如，该结合层的厚度为5至25微米，且于移除该承载件的凹部下方的部分时，一并移除该结合层。
前述的制法中，该介电层填入该凹部中，且该介电层包覆该半导体组件的侧面周围。
前述的半导体封装件及制法中，该半导体组件为多芯片模块或单一芯片结构。
前述的半导体封装件及制法中，该半导体组件的厚度为10至300微米。
前述的半导体封装件及制法中，形成该介电层的材质不同于该粘着材，且形成该介电层的材质为无机材质或有机材质。
前述的半导体封装件及制法中，该线路层具有多个导电盲孔，以藉其电性连接该半导体组件。
前述的半导体封装件及制法中，还包括形成线路重布结构于该介电层与该线路层上，且该线路重布结构电性连接该线路层，且于移除该承载件的凹部下方的部分后，结合封装基板至该线路重布结构上，且该线路重布结构电性连接该封装基板。例如，该线路重布结构包含相叠的介电部与线路部，且形成该介电部的材质为无机材质或有机材质。
前述的半导体封装件及制法中，还包括于移除该承载件的凹部下方的部分后，结合封装基板至该线路层上，且该线路层电性连接该封装基板。
前述的半导体封装件及制法中，还包括于形成该介电层前，形成止蚀层于该半导体组件的作用侧上，使该介电层形成于该止蚀层上。例如，于形成该止蚀层前，先形成介电材于该粘着材与该半导体组件的作用侧上，并包覆半导体组件的侧面，再形成开口于该介电材上以外露该半导体组件的作用侧，使该止蚀层形成于该半导体组件的作用侧上。又，形成该止蚀层的材质为氮化硅，且形成该介电材的材质为无机材质或有机材质。
另外，前述的半导体封装件及制法中，该无机材质为氧化硅或氮化硅，且该有机材质为聚酰亚胺、聚对二唑苯或苯环丁烯。
由上可知，本发明的半导体封装件及其制法，藉由无需制作现有硅中介板的方式，不仅能大幅降低该半导体封装件的制作成本，且能简化制程，使该半导体封装件的生产量提高及提高制作良率。
附图说明
图1为现有半导体封装件的剖面示意图；
图2A至图2H为本发明的半导体封装件的制法的第一实施例的剖面示意图；其中，图2B’及图2B”为图2B的其它实施例，图2G’及图2G”为图2G的其它实施例，图2H’及图2H”为图2H的其它实施例；以及
图3A至图3E为本发明的半导体封装件的制法的第二实施例的剖面示意图；其中，图3C’为图3C的其它实施例，图3E’及图3E”为图3E的其它实施例。
符号说明
1、2a、2b、2c、2d、2e、2f、3、3’、3”半导体封装件
10                 硅中介板
100                导电硅穿孔
11                 半导体芯片
110、210、310a     电极垫
12、22             粘着材
15、25             线路重布结构
17、27             导电组件
18、28             封装基板
180                焊垫
19                 焊锡凸块
20                 承载件
20’               支撑部
20a                表面
200                凹部
21、21’、31a、31b 半导体组件
21a                作用侧
21b                非作用侧
21c                侧面
211                结合层
212                结合材
212a、212b         芯片
23、33             介电层
230、230’         盲孔
24                 线路层
240                导电盲孔
250                介电部
251                线路部
26                 绝缘保护层
260                开孔
30                 介电材
300                开口
31                 止蚀层
310                第二穿孔
330                第一穿孔
S                  切割路径
H、L               高度
T、t、t’、m       厚度
d                  深度
h                  高度差。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2H为本发明的半导体封装件2a-2f的制法的第一实施例的剖面示意图。
如图2A所示，提供一具有多个凹部200的承载件20。
于本实施例中，该承载件20为含硅的板体，且该凹部200的深度d至多为该承载件20的厚度T的一半。
如图2B所示，置放多个半导体组件21于该承载件20的凹部200中，且形成粘着材22于该凹部200中与该半导体组件21的侧面21c周围。
于本实施例中，形成该粘着材22的材质为环氧树脂，该半导体组件21具有相对的作用侧21a与非作用侧21b、及相邻接该作用侧21a与该非作用侧21b的侧面21c，该作用侧21a具有多个电极垫210，且该非作用侧21b藉由一结合层211将该半导体组件21结合至该凹部200中，并使该半导体组件21未凸伸出该凹部200（即该半导体组件21的作用侧21a的位置低于该承载件20的表面20a），其中，该半导体组件21的厚度t为10至300微米（um），较佳为20至150微米（um），而该结合层211的厚度m为5至25微米（um）。
此外，该结合层211如芯片粘着层（die attach film,DAF），可先形成于该半导体组件21的非作用侧21b，再将该半导体组件21置放于该凹部200中；或者，该结合层211也可先形成于该凹部200中（如图2B”所示的点胶方式），再将该半导体组件21结合至该凹部200中的结合层211上。
又，于其它实施例中，如图2B’所示，该半导体组件21也可凸伸出该凹部200，即该半导体组件21的作用侧21a的位置高于该承载件20的表面20a而产生高度差h。
另外，该半导体组件21为单一芯片结构，且于一凹部200中置放两个半导体组件21，但不限于置放两个半导体组件21。但于其它实施例中，如图2B”所示，该半导体组件21’也可为多芯片模块，例如，先将两芯片212a,212b以结合材212（环氧树脂）相结合成一模块，再将该模块置放于该凹部200中。
如图2C所示，接续图2B的制程，形成一介电层23于该承载件20、粘着材22与半导体组件21的作用侧21a上，且形成多个盲孔230于该介电层23中，以令该些电极垫210外露于该些盲孔230。
于本实施例中，该介电层23填入该凹部200中。
此外，形成该介电层23的材质为无机材质，如氧化硅（SiO2）、氮化硅（SixNy）等、或有机材质，如聚酰亚胺（Polyimide,PI）、聚对二唑苯（Polybenzoxazole,PBO）、苯环丁烯(Benzocyclclobutene,BCB)等，所以形成该介电层23的材质不同于该粘着材22。
又，可藉由化学（如蚀刻）或物理（如激光开孔）方式形成该些盲孔230。
如图2D所示，形成一线路层24于该介电层23上，且形成导电盲孔240于该盲孔230中，使该线路层24藉由该些导电盲孔240电性连接该半导体组件21的作用侧21a的电极垫210。
于本实施例中，该线路层24为晶圆级线路，而非封装基板级线路。目前封装基板最小的线宽与线距为12μm，而半导体制程能制作出3μm以下的线宽与线距。
本发明的制法中，由于该承载件20为含硅的材质，使其与该半导体组件21之间的热膨胀系数相似，所以可避免该承载件20于部分制作过程中因升温降温而发生翘曲(warpage)的现象，因而能避免该导电盲孔240与该电极垫210间的对位不准确，或因翘曲度过大而造成该半导体组件21破裂的问题发生。
如图2E所示，进行线路重布层（Redistribution layer,RDL）制程，即形成一线路重布结构25于该介电层23与该线路层24上，且该线路重布结构25电性连接该线路层24。
于本实施例中，该线路重布结构25包含相叠的介电部250、线路部251及绝缘保护层26，且该绝缘保护层26形成有多个开孔260，令该线路部251外露于各该开孔260，以供结合如焊球的导电组件27。
此外，形成该介电部250的材质为无机材质，如氧化硅（SiO2）、氮化硅（SixNy）等、或有机材质，如聚酰亚胺（Polyimide,PI）、聚对二唑苯（Polybenzoxazole,PBO）、苯环丁烯(Benzocyclclobutene,BCB)等。
如图2F所示，移除该承载件20的凹部200下方的部分及该结合层211，以外露该半导体组件21的非作用侧21b与粘着材22，且保留该承载件20的凹部200侧壁的部分，以供作为支撑部20’。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，且保留该支撑部20’，以形成本发明的其中一种半导体封装件2a的实施例。
于本实施例中，该支撑部20’用于形成框体，且该半导体组件21的厚度t未大于该支撑部20’的高度L。
此外，也可如图2G’所示，于进行切单制程时，一并移除该支撑部20’，以形成本发明的其中一半导体封装件2b的实施例。
又，若接续图2B’的制程，可得到具有支撑部20’的半导体封装件，且该半导体组件21的厚度t’大于该支撑部20’的高度H，如图2G”所示的半导体封装件2c。
本发明的制法中，藉由该支撑部20’的设计，能增加该半导体封装件2a,2c的整体结构的刚性。
如图2H所示，接续图2G的制程，藉由该些导电组件27结合一封装基板28至该线路重布结构25上，且该线路重布结构25的线路部251电性连接该封装基板28，以形成本发明的其中一种半导体封装件2d的实施方法。
此外，如图2H’所示，其接续图2D所示的制程，即形成该线路层24后，先形成该绝缘保护层26于该线路层24上，且该绝缘保护层26形成有外露该线路层24的多个开孔260，以形成该些导电组件27于该线路层24的外露处上，再进行切单制程，之后藉由该些导电组件27结合该封装基板28至该线路层24上，且该线路层24电性连接该封装基板28，以形成本发明的其中一种半导体封装件2e的实施方法。
又，若接续图2B”的制程，可得到如图2H”所示的具有支撑部20’的半导体封装件2f或不具有支撑部的半导体封装件（图略）。
图3A至图3E为本发明的半导体封装件的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于形成该介电层33前的前置作业，其它步骤的制程大致相同，所以不再赘述相同处。
如图3A所示，接续图2B的制程（也可接续图2B’或图2B”的制程），形成一介电材30于该承载件20、粘着材22与该半导体组件21的作用侧21a上，并包覆半导体组件21的侧面21c周围，再形成一开口300于该介电材30上以外露该半导体组件21的作用侧21a。
于本实施例中，该半导体组件21为单一芯片结构，且于一凹部200中置放一个半导体组件21(并不限单一半导体组件，而本实施例以单一半导体组件为例)。
此外，该介电材30为无机材质，如氧化硅（SiO2）、氮化硅（SixNy）等、或有机材质，如聚酰亚胺（Polyimide,PI）、聚对二唑苯（Polybenzoxazole,PBO）、苯环丁烯(Benzocyclclobutene,BCB)等。
又，形成该开口300的方式可视该介电材30的种类而定，若该介电材30具有感光特性（如有机材质），则可利用曝光、显影的方式直接形成该开口300于该介电材30上；若该介电材30不具有感光特性（如无机材质），则可利用图案化光阻形成该介电材30上，再蚀刻该介电材30以形成该开口300。
如图3B所示，形成一止蚀层31于该介电材30与该半导体组件21的作用侧21a上。
于本实施例中，形成该止蚀层31的材质为氮化硅（SixNy）。
如图3C所示，形成该介电层33于该止蚀层31上，且以蚀刻方式形成多个第一穿孔330于该介电层33上。
于本实施例中，由于以蚀刻方式形成该第一穿孔330，所以形成该介电层23的材质需不同于该止蚀层31的材质，例如，形成该介电层23的材质为氧化硅（SiO2）。
如图3D所示，形成多个第二穿孔310于该止蚀层31上，以令各该第一穿孔330对应连通各该第二穿孔310而形成盲孔230’，使该半导体组件21的电极垫210外露于该些盲孔230’。
于本实施例中，可藉由蚀刻方式形成该第二穿孔310，但形成该第二穿孔310的蚀刻液不同于形成该第一穿孔330的蚀刻液。
本发明的制法藉由止蚀层31的设计，可避免形成该第一穿孔330（或第一实施例的盲孔230）时，因该第一穿孔330孔深较深，选择蚀刻速度较快的蚀刻液，蚀刻时间控制难度高，恐造成过蚀现象，使蚀刻液破坏该半导体组件21（如电极垫210），所以设置一止蚀层31，之后再选择蚀刻速度慢的蚀刻液以形成孔深较浅的第二穿孔310，而保护住该半导体组件21。
又，于该止蚀层31的另一种应用中，当设置多个厚度不同的半导体组件31a,31b于该凹部200中时，如图3C’所示，使用该方式可保护厚度较厚的半导体组件31a的电极垫310a不会遭受破坏，此因位于厚度薄的半导体组件31b上方的介电层33，需要较久的蚀刻时间方能形成该第一穿孔330。若无该止蚀层31，蚀刻液会破坏厚度较厚的半导体组件31a的电极垫310a。
如图3E、图3E’及图3E”所示，后续形成该线路层24（依需求形成该线路重布结构25，如图3E”所示）、进行切单制程（依需求形成支撑部20’，如图3E所示、或结合该封装基板28，如图3E”所示），以形成本发明的其中一种半导体封装件3,3’,3”的实施方式。
本发明的制法中，因无需制作现有硅中介板，所以不仅能大幅降低该半导体封装件2a-2f,3,3’,3”的制作成本，且能简化制程，使该半导体封装件2a-2f,3,3’,3”的生产量提高及提高制作良率。
此外，本发明的半导体封装件2a-2f,3,3’,3”因无现有硅中介板，所以相较于现有具硅中介板的封装件，本发明的半导体封装件能使最终产品的整体厚度较薄。
又，本发明的半导体封装件2a-2f,3,3’,3”的半导体组件21,21’无需经由现有硅中介板做讯号转接传输，所以该半导体组件21,21’的传输速度更快。
本发明提供一种半导体封装件2a-2f,3,3’,3”，包括：至少一半导体组件21,21’、设于该半导体组件21,21’的侧面21c周围的粘着材22、设于该粘着材22与半导体组件21,21’的作用侧21a上方的一介电层23、以及设于该介电层23上的一线路层24。
所述的半导体组件21,21’为多芯片模块或单一芯片结构，且该半导体组件21,21’具有相对的作用侧21a与非作用侧21b，其厚度t,t’为20至150微米。
所述的介电层23的材质不同于该粘着材22，且形成该介电层23的材质为无机材质或有机材质。
所述的线路层24具有多个导电盲孔240，以藉其电性连接该半导体组件21,21’。
于一实施例中，该介电层23包覆该半导体组件21,21’的侧面21c周围。
于一实施例中，所述的半导体封装件2a-2d,2f,3”还包括一线路重布结构25，设于该介电层23与该线路层24上并电性连接该线路层24，且该线路重布结构25包含相叠的介电部250与线路部251，而形成该介电部250的材质为无机材质或有机材质。于一实施例中，所述的半导体封装件2d,2f,3”又包括封装基板28，设于该线路重布结构25上并电性连接该线路重布结构25。
于一实施例中，所述的半导体封装件2e还包括一封装基板28，设于该线路层24上并电性连接该线路层24。
于一实施例中，所述的半导体封装件2a,2c-2f,3还包括一支撑部20’，包围该粘着材22，且该支撑部20’为含硅框体。其中一实施例，该半导体组件的厚度t未大于该支撑部20’的高度L，而另一实施例，该半导体组件21的厚度t’大于该支撑部20’的高度H。
于一实施例中，所述的半导体封装件3,3’,3”还包括一止蚀层31，例如氮化硅，其设于该半导体组件21的作用侧21a与该介电层33之间。较佳地，所述的半导体封装件3,3’,3”又包括一介电材30，如无机材质或有机材质，其设于该粘着材22与半导体组件21的作用侧21a上并具有外露该半导体组件21的作用侧21a的一开口300，使该止蚀层31能设于该半导体组件21的作用侧21a与该介电层33之间。
所述的无机材质为氧化硅（SiO2）或氮化硅（SixNy），且所述的有机材质为聚酰亚胺（Polyimide,PI）、聚对二唑苯（Polybenzoxazole,PBO）或苯环丁烯(Benzocyclclobutene,BCB)。
综上所述，本发明的半导体封装件及其制法，藉由无需制作现有硅中介板的方式，不仅能大幅降低该半导体封装件的制作成本，且能简化制程，使该半导体封装件的生产量提高及提高制作良率。
此外，本发明的半导体封装件因无现有硅中介板的结构，所以能使最终产品的整体厚度较薄，且能使该半导体组件的传输速度更快。
又，藉由该承载件为含硅材质的设计，以避免该承载件发生翘曲的现象。
另外，藉由该支撑部的设计，能增加该半导体封装件的整体结构的刚性。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (50)

1.一种半导体封装件，其包括：
半导体组件，其具有相对的作用侧与非作用侧、及相邻接该作用侧与该非作用侧的侧面；
粘着材，其设于该半导体组件的侧面周围；
介电层，其设于该粘着材与半导体组件的作用侧上方；以及
线路层，其设于该介电层上并电性连接该半导体组件。
2.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件为多芯片模块或单一芯片结构。
3.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件的厚度为10至300微米。
4.根据权利要求1所述的半导体封装件，其特征在于，该介电层的材质不同于该粘着材。
5.根据权利要求1所述的半导体封装件，其特征在于，形成该介电层的材质为无机材质或有机材质。
6.根据权利要求1所述的半导体封装件，其特征在于，该介电层包覆该半导体组件的侧面周围。
7.根据权利要求1所述的半导体封装件，其特征在于，该线路层具有多个导电盲孔，以藉其电性连接该半导体组件。
8.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括线路重布结构，设于该介电层与该线路层上并电性连接该线路层。
9.根据权利要求8所述的半导体封装件，其特征在于，该线路重布结构包含相叠的介电部与线路部。
10.根据权利要求9所述的半导体封装件，其特征在于，形成该介电部的材质为无机材质或有机材质。
11.根据权利要求8所述的半导体封装件，其特征在于，该半导体封装件还包括封装基板，其设于该线路重布结构上并电性连接该线路重布结构。
12.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括封装基板，其设于该线路层上并电性连接该线路层。
13.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括支撑部，其包围该粘着材。
14.根据权利要求13所述的半导体封装件，其特征在于，该支撑部为含硅框体。
15.根据权利要求13所述的半导体封装件，其特征在于，该半导体组件的厚度未大于该支撑部的高度。
16.根据权利要求13所述的半导体封装件，其特征在于，该半导体组件的厚度大于该支撑部的高度。
17.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括止蚀层，其设于该半导体组件的作用侧与该介电层之间。
18.根据权利要求17所述的半导体封装件，其特征在于，形成该止蚀层的材质为氮化硅。
19.根据权利要求17所述的半导体封装件，其特征在于，该半导体封装件还包括介电材，其设于该粘着材与半导体组件的作用侧上，并包覆半导体组件的侧面周围，且具有外露该半导体组件的开口，使该止蚀层设于该半导体组件的作用侧与该介电层之间。
20.根据权利要求19所述的半导体封装件，其特征在于，该介电材为无机材质或有机材质。
21.根据权利要求5、10或20所述的半导体封装件，其特征在于，该无机材质为氧化硅或氮化硅。
22.根据权利要求5、10或20所述的半导体封装件，其特征在于，该有机材质为聚酰亚胺、聚对二唑苯或苯环丁烯。
23.一种半导体封装件的制法，其包括：
置放一半导体组件于一承载件的凹部中，该半导体组件具有相对的作用侧与非作用侧、及相邻接该作用侧与该非作用侧的侧面；
形成粘着材于该凹部中与该半导体组件的侧面周围；
形成介电层于该粘着材与半导体组件的作用侧上方；
形成线路层于该介电层上，且该线路层电性连接该半导体组件；以及
移除该承载件的凹部下方的部分，以保留该承载件的凹部侧壁的部分，以供作为支撑部。
24.根据权利要求23所述的半导体封装件的制法，其特征在于，该承载件为含硅的板体。
25.根据权利要求23所述的半导体封装件的制法，其特征在于，该承载件具有多个该凹部，以于移除该承载件的凹部下方的部分后，进行切单制程。
26.根据权利要求25所述的半导体封装件的制法，其特征在于，该切单制程同时移除该支撑部。
27.根据权利要求23所述的半导体封装件的制法，其特征在于，该凹部的深度至多为该承载件的厚度的一半。
28.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体组件为多芯片模块或单一芯片结构。
29.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体组件的厚度为10至300微米。
30.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体组件未凸伸出该凹部。
31.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体组件凸伸出该凹部。
32.根据权利要求23所述的半导体封装件的制法，其特征在于，该半导体组件的非作用侧藉由结合层结合至该凹部中。
33.根据权利要求32所述的半导体封装件的制法，其特征在于，该结合层的厚度为5至25微米。
34.根据权利要求32所述的半导体封装件的制法，其特征在于，于移除该承载件的凹部下方的部分时，一并移除该结合层。
35.根据权利要求23所述的半导体封装件的制法，其特征在于，形成该介电层的材质为无机材质或有机材质。
36.根据权利要求23所述的半导体封装件的制法，其特征在于，形成该介电层的材质不同于该粘着材。
37.根据权利要求23所述的半导体封装件的制法，其特征在于，该介电层包覆该半导体组件的侧面周围。
38.根据权利要求23所述的半导体封装件的制法，其特征在于，该介电层填入该凹部中。
39.根据权利要求23所述的半导体封装件的制法，其特征在于，该线路层藉由多个导电盲孔电性连接该半导体组件。
40.根据权利要求23所述的半导体封装件的制法，其特征在于，该制法还包括形成线路重布结构于该介电层与该线路层上，且该线路重布结构电性连接该线路层。
41.根据权利要求40所述的半导体封装件的制法，其特征在于，该线路重布结构包含相叠的介电部与线路部。
42.根据权利要求41所述的半导体封装件的制法，其特征在于，形成该介电部的材质为无机材质或有机材质。
43.根据权利要求40所述的半导体封装件的制法，其特征在于，该制法还包括于移除该承载件的凹部下方的部分后，结合封装基板至该线路重布结构上，且该线路重布结构电性连接该封装基板。
44.根据权利要求23所述的半导体封装件的制法，其特征在于，该制法还包括于移除该承载件的凹部下方的部分后，结合封装基板至该线路层上，且该线路层电性连接该封装基板。
45.根据权利要求23所述的半导体封装件的制法，其特征在于，该制法还包括于形成该介电层前，形成止蚀层于该半导体组件的作用侧上，使该介电层形成于该止蚀层上。
46.根据权利要求45所述的半导体封装件的制法，其特征在于，形成该止蚀层的材质为氮化硅。
47.根据权利要求45所述的半导体封装件的制法，其特征在于，该制法还包括于形成该止蚀层前，形成介电材于该粘着材与该半导体组件的作用侧上，并包覆半导体组件的侧面，再形成开口于该介电材上以外露该半导体组件的作用侧，使该止蚀层形成于该半导体组件的作用侧上。
48.根据权利要求47所述的半导体封装件的制法，其特征在于，该介电材为无机材质或有机材质。
49.根据权利要求35、42或48所述的半导体封装件的制法，其特征在于，该无机材质为氧化硅或氮化硅。
50.根据权利要求35、42或48所述的半导体封装件的制法，其特征在于，该有机材质为聚酰亚胺、聚对二唑苯或苯环丁烯。
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