TWI718801B - 電子封裝件之製法 - Google Patents

電子封裝件之製法 Download PDF

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Publication number
TWI718801B
TWI718801B TW108144709A TW108144709A TWI718801B TW I718801 B TWI718801 B TW I718801B TW 108144709 A TW108144709 A TW 108144709A TW 108144709 A TW108144709 A TW 108144709A TW I718801 B TWI718801 B TW I718801B
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Taiwan
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package
carrier
manufacturing
layer
electronic
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TW108144709A
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TW202123348A (zh
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廖信一
張正楷
馬伯豪
柯俊吉
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矽品精密工業股份有限公司
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Priority to TW108144709A priority Critical patent/TWI718801B/zh
Priority to CN201911322598.5A priority patent/CN112928032A/zh
Priority to US16/821,095 priority patent/US11195812B2/en
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Publication of TWI718801B publication Critical patent/TWI718801B/zh
Publication of TW202123348A publication Critical patent/TW202123348A/zh

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種電子封裝件之製法，係先製作複數封裝結構，其包含一承載件及至少一設於該承載件上之電子元件，再將該複數封裝結構設於一支撐板上，之後形成封裝層於該支撐板上以包覆該複數封裝結構，故即使電子封裝件之規格繁多，該封裝層所用之模具仍僅需針對該支撐板之單一規格開發，以有效降低製程成本。

Description

電子封裝件之製法
本發明係有關一種半導體封裝製程，尤指一種電子封裝件之製法。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。
第1圖係為習知半導體封裝件1之剖面示意圖。如第1圖所示，該半導體封裝件1係包括：一封裝基板10、一覆晶設於該封裝基板10上之半導體晶片11、以及用以包覆該半導體晶片11之封裝膠體13。所述之封裝基板10之置晶側係具有複數電性接觸墊100，而植球側係結合複數銲球14以接置電路板。所述之半導體晶片11以其電極墊110藉由複數銲錫凸塊12結合於該電性接觸墊100上。
習知半導體封裝件1於封裝過程中，係先將複數半導體晶片11設於整版面型封裝基板10上，再形成封裝膠體13，之後進行切單製程以獲取複數半導體封裝件1。
惟，習知半導體封裝件1之規格種類繁多，故於形成封裝膠體13時，該封裝膠體13所用之模具需配合各種半導體封裝件1之規格對應該封裝基板10開發出不同態樣之模形，因而大幅增加製程成本。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件之製法，係包括：提供複數封裝結構，其中，該封裝結構係包含一承載件及至少一電子元件，該承載件係具有相對之第一表面與第二表面，且該電子元件係設於該承載件之第一表面上並電性連接該承載件；將該複數封裝結構以其承載件之第二表面設於支撐板上，其中，各該封裝結構係相互間隔配置於該支撐板上；形成封裝層於該支撐板上，以令該封裝層包覆該複數封裝結構；以及移除該支撐板。
前述之製法中，該承載件之第二表面係藉由結合層結合於該支撐板上。
前述之製法中，該支撐板係為膠帶或金屬板。
前述之製法中，該支撐板係為方形板體或圓形板體。
前述之製法中，該支撐板之邊緣配置有強化件。
前述之製法中，該電子元件係外露於該封裝層。
前述之製法中，復包括形成複數導電元件於該承載件之第二表面上。
前述之製法中，復包括於移除該支撐板後，進行切單製程。例如，該封裝層於切單製程後係包覆該承載件之側面。或者，該封裝層於切單製程後未包覆該承載件之側面。
由上可知，本發明之電子封裝件之製法中，主要藉由先製作複數封裝結構，再將該些封裝結構配置於支撐板上，之後形成封裝層及進行切單製程，因而於形成封裝層時，該封裝層所用之模具僅需針對該支撐板之單一規格開發，而無需配合電子封裝件之規格開發。因此，即使電子封裝件之規格繁多，該封裝層所用之模具仍僅需針對該支撐板之單一規格開發，故相較於習知技術，本發明之製法能有效降低製程成本。
1‧‧‧半導體封裝件
10‧‧‧封裝基板
100‧‧‧電性接觸墊
11‧‧‧半導體晶片
110‧‧‧電極墊
12‧‧‧銲錫凸塊
13‧‧‧封裝膠體
14‧‧‧銲球
2,2’,2”‧‧‧電子封裝件
2a‧‧‧封裝結構
20‧‧‧承載件
20a‧‧‧第一表面
20b‧‧‧第二表面
20c‧‧‧側面
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
22‧‧‧導電凸塊
23‧‧‧底膠
24‧‧‧結合層
25‧‧‧封裝層
26‧‧‧導電元件
8‧‧‧強化件
9‧‧‧支撐板
D‧‧‧寬度
S‧‧‧切割路徑
t‧‧‧間距
第1圖係為習知半導體封裝件的剖視示意圖。
第2A至2F圖係為本發明之電子封裝件之製法之剖視示意圖。
第2D’圖係為第2D圖之另一實施例之剖視圖。
第2F’及2F”圖係為第2F圖之不同實施例之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀， 並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供複數封裝結構2a，其中，各該封裝結構2a係包含一承載件20及至少一電子元件21，該承載件20係具有相對之第一表面20a與第二表面20b，且該電子元件21係設於該承載件20之第一表面20a上並電性連接該承載件20。
於本實施例中，該承載件20係為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，該線路結構係於介電材上形成線路層(圖略)，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且介電材係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等。應可理解地，該承載件20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(lead-frame)或矽中介板(silicon interposer)等載件，並不限於上述。
再者，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件21係為半導體晶片，其具有作用面21a與相對該作用面 21a之非作用面21b，且該作用面21a上具有複數電極墊(圖略)，使其藉由複數導電凸塊22以覆晶方式電性連接該承載件20之線路層，並以底膠23包覆該些導電凸塊22；或者，該電子元件21可以其非作用面21b設於該承載件20之第一表面20a上且該些電極墊藉由複數銲線(圖略)以打線方式電性連接該線路層；亦或，該電子元件21可直接接觸(如：晶片電極墊和基板接觸墊接合)該線路層以電性連接該線路層。然而，有關該電子元件21電性連接該承載件20之方式不限於上述。
如第2B圖所示，將複數封裝結構2a以其承載件20之第二表面20b設於支撐板9上，其中，該複數封裝結構2a係相互間隔(如第2B圖所示之間距t)配置於該支撐板9上。
於本實施例中，該承載件20之第二表面20b係藉由結合層24結合於該支撐板9上。例如，該結合層24係為黏性體，如膠帶或離形膜。
再者，該支撐板9係為膠帶或金屬板，其可為整版面型(panel form)或框條型(strip form)之方形板體或圓形板體。
又，該支撐板9之邊緣可依需求配置有強化件(stiffener)8。例如，該強化件8可為金屬框體、牆體或柱體。
如第2C圖所示，形成封裝層25於該支撐板9上，以令該封裝層25包覆該些封裝結構2a。
於本實施例中，該封裝層25係為封模底膠(molding underfill，簡稱MUF)，其材質如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝層(molding compound)。例如，該封裝層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該支撐板9上。
再者，該電子元件21係外露於該封裝層25。例如，可藉由整平製程，使該封裝層25之上表面齊平該電子元件之非作用面21b，以令該電子元件之非作用面21b外露於該封裝層25。例如，該整平製程係藉由研磨方式，移除該封裝層25之部分材質(如第2C圖所示之虛線處)。
如第2D圖所示，移除該支撐板9，以外露出該封裝層25下表面及結合層24下表面(或該強化件8底面)。
於另一實施例中，如第2D’圖所示，可依需求移除該結合層24，以外露出該承載件20之第二表面20b。
如第2E圖所示，接續第2D圖之製程，形成複數導電元件26於該承載件20之第二表面20b上，且該些導電元件26電性連接該承載件20之線路層。
於本實施例中，該導電元件26係穿過該結合層24以電性連接該承載件20之線路層，且該導電元件26係為如銲球之球狀、如銅柱或銲錫凸塊等金屬柱狀、或銲線機製作之釘狀(stud)導電件，但不限於此。
如第2F圖所示，沿如第2E圖所示之切割路徑S進行切單製程，以獲取複數電子封裝件2，其中，該電子封裝件2可藉由該些導電元件26接置一如電路板之電子裝置(圖略)。
於本實施例中，該封裝層25於切單製程後係包覆該承載件20之側面20c。
再者，若接續第2D’圖之製程，將得到如第2F’圖所示之電子封裝件2’，其導電元件26係結合於該承載件20之第二表面20b上，且該些導電元件26電性連接該承載件20之線路層。
又，該封裝層25可依需求未包覆該承載件20，如第2F”圖所示之電子封裝件2”。例如，調整該切割路徑S之寬度D(如第2E圖所示)，使 該封裝層25側表面齊平該承載件20之側面20c，以令該承載件20之側面20c外露出該封裝層25。
因此，本發明之電子封裝件之製法係藉由先製作該複數封裝結構2a，再將其配置於該支撐板9上，接著形成該封裝層25，最後進行切單製程，故於形成封裝層25時，該封裝層25所用之模具僅需針對該支撐板9之單一規格開發單一態樣之模具，因而能大幅降低製程成本。
綜上所述，本發明之電子封裝件2,2’,2”藉由複數封裝結構2a之設計，即使該電子封裝件2,2’,2”之規格不同，該封裝層25所用之模具仍僅需針對該支撐板9之單一規格開發，而無需配合該電子封裝件2,2’,2”之規格開發多種模具，故相較於習知技術，本發明之製法能有效降低製程成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2a‧‧‧封裝結構
20‧‧‧承載件
20b‧‧‧第二表面
21‧‧‧電子元件
24‧‧‧結合層
8‧‧‧強化件
9‧‧‧支撐板
t‧‧‧間距

Claims (10)

  1. 一種電子封裝件之製法，係包括：提供複數封裝結構，其中，各該封裝結構係包含一具有線路層之承載件及至少一電子元件，該承載件係具有相對之第一表面與第二表面，且該電子元件係設於該承載件之第一表面上並電性連接該線路層；將該複數封裝結構以其承載件之第二表面相互間隔配置於一支撐板上；形成封裝層於該支撐板上，以令該封裝層包覆該複數封裝結構；以及移除該支撐板。
  2. 如申請專利範圍第1項所述之電子封裝件之製法，其中，該承載件之第二表面係藉由結合層結合於該支撐板上。
  3. 如申請專利範圍第1項所述之電子封裝件之製法，其中，該支撐板係為膠帶或金屬板。
  4. 如申請專利範圍第1項所述之電子封裝件之製法，其中，該支撐板係為方形板體或圓形板體。
  5. 如申請專利範圍第1項所述之電子封裝件之製法，其中，該支撐板之邊緣配置有強化件。
  6. 如申請專利範圍第1項所述之電子封裝件之製法，其中，該電子元件係外露於該封裝層。
  7. 如申請專利範圍第1項所述之電子封裝件之製法，復包括形成複數導電元件於該承載件之第二表面上。
  8. 如申請專利範圍第1項所述之電子封裝件之製法，復包括於移除該支撐板後，進行切單製程。
  9. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該封裝層於切單製程後係包覆該承載件之側面。
  10. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該封裝層於切單製程後未包覆該承載件之側面。
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