TWI476841B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI476841B
TWI476841B TW101107145A TW101107145A TWI476841B TW I476841 B TWI476841 B TW I476841B TW 101107145 A TW101107145 A TW 101107145A TW 101107145 A TW101107145 A TW 101107145A TW I476841 B TWI476841 B TW I476841B
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layer
semiconductor package
encapsulant
wafer
adhesive layer
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TW101107145A
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TW201338059A (zh
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張江城
李孟宗
黃榮邦
邱世冠
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矽品精密工業股份有限公司
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Priority to TW101107145A priority Critical patent/TWI476841B/zh
Priority to CN2012101096765A priority patent/CN103295978A/zh
Priority to US13/534,664 priority patent/US20130228915A1/en
Publication of TW201338059A publication Critical patent/TW201338059A/zh
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Publication of TWI476841B publication Critical patent/TWI476841B/zh
Priority to US15/497,964 priority patent/US10049955B2/en

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Description

半導體封裝件及其製法
本發明係關於半導體封裝件及其製法，特別是關於一種提升可靠度之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
第6452265號美國專利與第7202107號美國專利係提供一種晶圓級封裝之製法。請參閱第1A至1E圖，係為習知半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載板10上，該熱化離型膠層11具有遇熱失去黏性之特性。
如第1B圖所示，置放複數晶片12於該熱化離型膠層11上，該些晶片12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a結合於該熱化離型膠層11上。
如第1C圖所示，以模壓(molding)方式形成一封裝膠體13於該晶片12與該熱化離型膠層11上。
如第1D圖所示，加熱移除該熱化離型膠層11與該承載板10，以外露該晶片12之作用面12a。
如第1E圖所示，形成一線路結構14於該封裝膠體13與該晶片12之作用面12a上，令該線路結構14電性連接該晶片12之電極墊120。
惟，習知半導體封裝件1之製法中，該熱化離型膠層11具有黏性，又該熱化離型膠層11與承載板10熱膨脹係數(Coefficient of thermal expansion,CTE)差異過大，故在封裝膠體13形成後，往往使整體結構在溫度循環中發生翹曲(warpage)，導致產品之可靠度不佳。
再者，使用熱化離型膠層11塗佈於該承載板10上之製程，不利於將該熱化離型膠層11均勻塗佈於大版面尺寸之承載板10上，故多選擇塗佈於小版面尺寸之承載板10上以達均勻塗佈之需求。然而，若將熱化離型膠層11塗佈於小版面尺寸之承載板10上，不僅輸送設備(圖略)不便輸送小版面尺寸之承載板10，且難以提高生產效率。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種半導體封裝件，係包括：封裝膠體，係具有相對之第一表面與第二表面，且該第一表面上形成有凸部；晶片，係嵌埋於該封裝膠體中，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面與電極墊係外露於該凸部；線路結構，係形成於該封裝膠體之第一表面與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊；以及接著層，係形成於該封裝膠體之第二表面上。
本發明復提供一種半導體封裝件之製法，係包括：提供一表面具有凹部之承載板，且該承載板之具有該凹部之表面上形成有離型層；置放晶片於該凹部內之離型層上，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面結合於該離型層上；形成封裝膠體於該晶片與該離型層上；形成接著層於該封裝膠體上；移除該離型層與該承載板，以外露該晶片之作用面；以及形成線路結構於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
前述之製法中，形成該承載板之材質可為玻璃或金屬，且形成該離型層之材質可為疏水性材質、無機物或高分子聚合物。
前述之製法中，可以電漿輔助化學氣相沉積之方式形成該離型層，且可以壓合方式形成該接著層。
前述之製法復可包括切單製程，以分離出複數個該半導體封裝件。
前述之製法於移除該離型層與該承載板之步驟前，復可包括形成一分隔層於該接著層上，其中，該分隔層係位於一支撐板上，以令該分隔層夾置於該支撐板與該接著層之間。例如：於形成該接著層於該封裝膠體上之步驟前，可先令該分隔層夾置於該支撐板與該接著層之間。其中，該分隔層對該支撐板與該接著層不具黏性。
因此，該分隔層可經圖案化形成縫隙，再埋設該分隔層於該接著層中，使部分該接著層位於該縫隙中，以令該接著層結合該支撐板，而形成該線路結構之後，可沿對應該縫隙之切割路徑進行切割，以分離該分隔層與該支撐板，且分離出複數個該半導體封裝件。或者，該分隔層之面積可小於該接著層與該支撐板之面積，使部分該接著層包覆該分隔層之邊緣，以令該接著層結合至該支撐板之邊緣，而形成該線路結構之後，可對應該晶片進行切單製程，並沿該分隔層邊緣進行切割，以分離該支撐板與分隔層，且分離出複數個該半導體封裝件。
前述之半導體封裝件及其製法中，形成該接著層之材質可為聚亞醯胺、乾膜或半乾材。
前述之半導體封裝件及其製法中，該線路結構可具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該電極墊。
依上述結構及其製法，最外層之介電層上可形成有絕緣層，該絕緣層具有開孔，以令該線路層之部分表面外露於該開孔，可供結合導電元件。
另外，於其他態樣中，該線路結構可具有設於該封裝膠體上之至少一介電層、及形成於該介電層與該作用面上之線路層，且該線路層電性連接該晶片之電極墊。
由上可知，本發明半導體封裝件及其製法，係藉由該離型層對晶片及封裝膠體僅具些微黏性，以避免因熱膨脹係數(CTE)不同而使整體結構在溫度循環中發生翹曲。再者，以電漿輔助化學氣相沉積之方式，該離型層容易形成於大版面之承載板上，故可便於輸送，且可提高生產效率。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2H圖，係為本發明之半導體封裝件2之製法之剖面示意圖。
如第2A圖所示，提供表面上具有複數凹部200之一承載板20上。於本實施例中，形成該承載板20之材質係為玻璃或金屬，且各該凹部200係陣列排形成於該承載板20上。
如第2B圖所示，形成一離型層21於該承載板20表面與該些凹部200表面上。
於本實施例中，係利用電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PECVD)之方式形成該離型層21，且形成該離型層21之材質係為疏水性材質、無機物或高分子聚合物，如聚對二甲苯(Poly-para-xylylene,parylene)。
又，利用電漿輔助化學氣相沉積方式形成該離型層21，較容易形成於大版面尺寸之承載板20上，因而不僅便於輸送大版面之承載板20，且可提高生產效率。
如第2C圖所示，置放複數晶片22於各該凹部200之離型層21上，各該晶片22具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，且該作用面22a結合於該離型層21上。
本發明藉由形成凹部200，以利於晶片22對位置放，因而可避免晶片22之位置偏移，且該離型層21對該晶片22僅具些微黏性，故相較於習知技術之熱化離型膠層，該離型層21之熱膨脹係數(CTE)亦不會造成晶片22位置偏移過大之問題。因此，本發明之製法可使晶片22之位置固定，因而可提升產品後續製程之可靠度。
如第2D圖所示，以壓合或塗佈之方式形成一封裝膠體23於該晶片22與該離型層21上，以包覆該晶片22。
於本實施例中，形成該封裝膠體23之材質可為聚亞醯胺(Polyimide,PI)，並無特別限制，但該離型層21對該封裝膠體23具有黏性。
如第2D及2E圖所示，藉由一支撐板29，以壓合方式形成一接著層27於該封裝膠體23上，且壓合一分隔層28於該接著層27中。
於本實施例中，該接著層27之厚度可為10至100um，且形成該接著層27之材質係為聚亞醯胺(Polyimide,PI)、乾膜(dry film)或半乾材，而形成該支撐板29之材質係為玻璃。
再者，該分隔層28對該接著層27(如PI)與該支撐板29(如玻璃)均不具黏性，而接著層27(如PI)與該支撐板29(如玻璃)具黏性，故於製程中，需先將該分隔層28進行圖案化製程以形成縫隙280，再進行壓合，使該接著層27壓入該縫隙280中以結合該支撐板29。
又，於本實施例中，係同時壓合該接著層27、圖案化之分隔層28與支撐板29，如第2D圖所示。而於其他實施例中，亦可先將該接著層27形成於該封裝膠體23上，再藉由該支撐板29將圖案化之分隔層28壓入該接著層27中。
另外，於另一實施例中，係可藉由尺寸設計，使該接著層27結合該支撐板29。如第2E’圖所示，該分隔層28’之面積小於該接著層27之面積及該支撐板29之面積，當進行壓合作業時，部分該接著層27將受壓包覆該分隔層28’之邊緣，以令該接著層27結合至該支撐板29之邊緣。
如第2F圖所示，移除該離型層21與該承載板20，以外露該晶片22之作用面22a，且使該封裝膠體23具有凸部230。
於本實施例中，係先剝除該承載板20，再以電漿(plasma)方式移除該離型層21。因此，本發明之製法中，可不需依靠加熱方式即可移除該離型層21，故可避免整體結構在溫度循環中發生翹曲之問題。
再者，於此移除階段的製程，因需將整體結構移至另一機台上，且翻面進行移除作業，故於前一步驟須設置該支撐板29，以令該支撐板29於此階段作承載之用。
如第2G圖所示，形成一線路結構24於該封裝膠體23與該晶片22之作用面22a上，令該線路結構24電性連接該晶片22之電極墊220。
於本實施例中，該線路結構24具有設於該封裝膠體23與該作用面22a上之至少一介電層240、形成於該介電層240上之線路層241、及形成於該介電層240中之導電盲孔242，且該導電盲孔242電性連接該線路層241與該電極墊220。接著，形成一絕緣層25於該最外層之介電層240上，該絕緣層25具有複數開孔250，以令該線路層241之部分表面對應外露於各該開孔250，俾供結合導電元件26。
所述之介電層240可依需求為多層，而增加線路層241之功能。所述之絕緣層25之厚度可為30至500um，且該絕緣層25之材質可為二氧化矽(SiO2 )或氮化矽(silicon nitrate)以作為鈍化層(passivation layer)。該絕緣層25之材質亦可為聚亞醯胺(Polyimide,PI)或如聚對二唑苯(Polybenzoxazole,PBO)之補強材。
再者，該導電元件26可為銲球、凸塊或銲針等，並無特別限制。
另外，於其他實施例中，如第2G’圖所示，該線路結構24亦可具有設於該封裝膠體23與該作用面22a上之至少一介電層240及形成於該介電層240上之線路層241，且該線路層241電性連接該晶片22之電極墊220。
本發明藉由壓合或塗佈之方式形成該封裝膠體23，取代習知模壓方式，以包覆該晶片22，再以圖案化方式形成大版面之線路結構24，可有效降低製作成本。
如第2H或2H’圖所示，利用雷射或刀具等切割工具，沿對應該縫隙280之切割線L(如第2F圖所示)進行切單製程，以切割出複數個半導體封裝件2,2’。
於本實施例中，係藉由圖案化該分隔層28所形成之縫隙280，以於切割時，使該接著層27不再黏住該支撐板29，故可一併分離移除該支撐板29與分隔層28。因此，本發明係利用支撐板29、分隔層28與接著層27所構成之三明治結構，以於切割完成後，便於取出各該半導體封裝件2。
於另一實施例中，若以第2E’圖進行後續製程，於切割時，係沿對應該晶片22周圍之切割線L’(如第2G”圖所示)進行切單製程，且還需沿該分隔層28’邊緣之切割線L”(如第2G”圖所示)進行切單製程，以完全分離移除該支撐板29與分隔層28。
本發明提供一種半導體封裝件2,2’，係包括：具有具有相對之第一表面23a與第二表面23b之封裝膠體23、嵌入該封裝膠體23中之一晶片22、形成於該封裝膠體23上之一線路結構24、以及形成於該封裝膠體23之第二表面23b上之一接著層27。
所述之封裝膠體23之第一表面23a上係具有一凸部230。
所述之晶片22係嵌入該凸部230中且具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，且該作用面22a與該些電極墊220係外露於該封裝膠體23之凸部230表面。
所述之接著層27之材質係為聚亞醯胺、乾膜或半乾材。
所述之線路結構24復形成於該第一表面23a與晶片22之作用面22a上，令該線路結構24電性連接該電極墊220。其中，該線路結構24具有設於該封裝膠體23與該作用面22a上之至少一介電層240、形成於該介電層240上之線路層241、及形成於該介電層240中之導電盲孔242，且該導電盲孔242電性連接該線路層241與該電極墊220。
或者，該線路結構24具有設於該封裝膠體23與該作用面22a上之至少一介電層240及形成於該介電層240上之線路層241，且該線路層241電性連接該晶片22之電極墊220。
又，該最外層之介電層240上形成有一絕緣層25，該絕緣層25具有複數開孔250，以令該線路層241之部分表面外露於各該開孔250，俾供結合導電元件26。另外，於其他實施例中，該線路結構24亦可為多層線路層之結構。
綜上所述，本發明之半導體封裝件及其製法，係藉由離型層對晶片與封裝膠體僅具些微黏性，以避免整體結構發生翹曲，故有效提升產品之可靠度。
再者，該離型層較容易形成於大版面之承載板上，因而便於輸送，且可提高生產效率。
又，藉由壓合或塗佈之方式形成該封裝膠體，再以圖案化方式形成大版面之線路結構，以達到降低製作成本之目的。
另外，藉由該分隔層之物理特性(黏性)與圖案化設計，以於切割完成後，便於拿取該半導體封裝件。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’．．．半導體封裝件
10,20．．．承載板
11．．．熱化離型膠層
12,22．．．晶片
12a,22a．．．作用面
12b,22b．．．非作用面
120,220．．．電極墊
13,23．．．封裝膠體
14,24．．．線路結構
200．．．凹部
21．．．離型層
23a．．．第一表面
23b．．．第二表面
230．．．凸部
240．．．介電層
241．．．線路層
242．．．導電盲孔
25．．．絕緣層
250．．．開孔
26．．．導電元件
27．．．接著層
28,28’．．．分隔層
280．．．縫隙
29．．．支撐板
L,L’,L”．．．切割線
第1A至1E圖係為習知半導體封裝件之製法之剖面示意圖；以及
第2A至2H圖係為本發明之半導體封裝件之製法之剖面示意圖；其中，第2E’圖係為第2E圖之另一實施例，第2G’、2G”及2H’圖係為第2G及2H圖之其它實施例。
20．．．承載板
21．．．離型層
22．．．晶片
23．．．封裝膠體
27．．．接著層
28．．．分隔層
280．．．縫隙
29．．．支撐板

Claims (22)

  1. 一種半導體封裝件，係包括：封裝膠體，係具有相對之第一表面與第二表面，且該封裝膠體於該第一表面上向外形成有相對該第一表面凸出之凸部；晶片，係自該凸部嵌埋於該封裝膠體中，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面與電極墊係外露於該凸部；線路結構，係形成於該封裝膠體之第一表面、凸部與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊；以及接著層，係形成於該封裝膠體之第二表面上。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路結構具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該電極墊。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，最外層之該介電層上形成有絕緣層，該絕緣層具有開孔，以令該線路層之部分表面外露於該開孔，俾供結合導電元件。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路結構具有設於該封裝膠體上之至少一介電層、及形成於該介電層與該作用面上之線路層，且該線路 層電性連接該晶片之電極墊。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，形成該接著層之材質係為聚亞醯胺、乾膜或半乾材。
  6. 一種半導體封裝件之製法，係包括：提供一表面具有凹部之承載板，且該承載板之具有該凹部之表面上形成有離型層；置放晶片於該凹部內之離型層上，該晶片具有相對之作用面與非作用面，該作用面上具有複數電極墊，且該作用面結合於該離型層上；形成封裝膠體於該晶片與該離型層上；形成接著層於該封裝膠體上；移除該離型層與該承載板，以外露該晶片之作用面；以及形成線路結構於該封裝膠體與該晶片之作用面上，令該線路結構電性連接該晶片之電極墊。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，形成該承載板之材質係為玻璃或金屬。
  8. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，形成該離型層之材質係為疏水性材質、無機物或高分子聚合物。
  9. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，係以電漿輔助化學氣相沉積之方式形成該離型層。
  10. 如申請專利範圍第6項所述之半導體封裝件之製法， 其中，係以壓合方式形成該接著層。
  11. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，形成該接著層之材質係為聚亞醯胺、乾膜或半乾材。
  12. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該線路結構具有設於該封裝膠體與該作用面上之至少一介電層、形成於該介電層上之線路層、及形成於該介電層中之導電盲孔，且該導電盲孔電性連接該線路層與該電極墊。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，最外層之該介電層上形成有絕緣層，該絕緣層具有開孔，以令該線路層之部分表面外露於該開孔，俾供結合導電元件。
  14. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該線路結構具有設於該封裝膠體上之至少一介電層、及形成於該介電層與該作用面上之線路層，且該線路層電性連接該晶片之電極墊。
  15. 如申請專利範圍第6項所述之半導體封裝件之製法，於移除該離型層與該承載板之步驟前，復包括下列步驟：形成一分隔層於該接著層上，其中，該分隔層係位於一支撐板上，以令該分隔層夾置於該支撐板與該接著層之間。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法， 其中，於形成該接著層於該封裝膠體上之步驟前，先令該分隔層夾置於該支撐板與該接著層之間。
  17. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該分隔層對該支撐板與該接著層不具黏性。
  18. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該分隔層經圖案化形成縫隙，再埋設該分隔層於該接著層中，使部分該接著層位於該縫隙中，以令該接著層結合該支撐板。
  19. 如申請專利範圍第18項所述之半導體封裝件之製法，復包括形成該線路結構之後，沿對應該縫隙之切割路徑進行切割，以分離該分隔層與該支撐板，且分離出複數個該半導體封裝件。
  20. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該分隔層之面積小於該接著層與該支撐板之面積，使部分該接著層包覆該分隔層之邊緣，以令該接著層結合至該支撐板之邊緣。
  21. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括形成該線路結構之後，係對應該晶片進行切單製程，且沿該分隔層邊緣進行切割，以分離該支撐板與分隔層，且分離出複數個該半導體封裝件。
  22. 如申請專利範圍第6項所述之半導體封裝件之製法，復包括進行切單製程，以分離出複數個該半導體封裝件。
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