CN102157392B - 低成本芯片扇出结构的封装方法 - Google Patents

低成本芯片扇出结构的封装方法 Download PDF

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CN102157392B
CN102157392B CN2011100337651A CN201110033765A CN102157392B CN 102157392 B CN102157392 B CN 102157392B CN 2011100337651 A CN2011100337651 A CN 2011100337651A CN 201110033765 A CN201110033765 A CN 201110033765A CN 102157392 B CN102157392 B CN 102157392B
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张黎
赖志明
陈栋
陈锦辉
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及一种低成本芯片扇出结构的封装方法，所述方法包括以下工艺步骤：一、取载体基板；二、在载体基板上贴上临时粘结膜；三、将芯片倒装至载体基板上；四、将带有芯片的载体基板用塑封体进行包封，形成重构基板；五、将重构基板与载体基板剥离；六、在重构基板上罩上掩膜板，通过光刻或者激光的方式在掩膜板上形成掩膜图形开口；七、在形成掩膜图形开口的重构基板上形成再布线金属；八、移除掩膜板；九、在重构基板上印刷或者贴再布线金属保护膜；十、在再布线金属保护膜上打出开口图形；十一、在开口图形处植球并回流，形成金属凸点。本发明的低成本芯片扇出结构封装方法，可极大程度的降低工艺难度和工艺成本，可实现低成本芯片扇出结构的规模化生产。

Description

低成本芯片扇出结构的封装方法
技术领域
本发明涉及一种低成本芯片扇出结构的封装方法。属于集成电路或分立器件封装技术领域。
背景技术
近年来，随着电子封装技术的高速发展，一些的新的封装形式不断出现，特别是晶圆级封装的出现，为低成本封装提供了极佳的解决思路。但对产品生产成本和性能的追求是无限的，传统的晶圆级封装技术采用的是扇入结构（Fan-in），这就要求芯片面积与封装面积需要保持1:1的比例，虽然缩小了封装面积，但是反过来却是增大了芯片面积，进而增加了芯片制造成本。因而，随着晶圆级封装技术的日益成熟，人们开始致力于利用小芯片完成适合配装的封装结构，简单意义上讲，就是将小芯片上的引脚通过扇出结构放大。圆片级扇入结构和扇出结构的示意图如图12和图13所示。
这种扇出结构的结果是，芯片尺寸大大缩小，而最终用于装配的封装体仍然保持现有扇入结构封装体尺寸，从而节省了整个产品的成本。与此同时，利用扇出结构的工艺特点，将一些无源器件、有源芯片、特种芯片等以多芯片封装的形式，形成一个大的球栅阵列（BGA）、栅格阵列封装（LGA）等封装结构。
虽然扇出结构有着上述优势，且目前的封装形式是以圆片为单位进行，其最大的问题是封装成本较高，造成封装成本偏高的原因有如下几个方面：
1）使用高端的芯片到圆片倒装技术，这种技术目前无论是设备还是工艺本身，还不够成熟；
2）使用圆片包封的方式形成重构圆片，同样，这种技术的设备还处于开发期间，不但昂贵，而且工艺也不够成熟；
3）使用光刻、电镀等工艺，成本相对较高。
发明内容
本发明的目的在于克服现有晶圆级扇出结构封装方法高成本工艺的不足，实现一种无光刻工艺的低成本芯片扇出结构的封装方法。
本发明的目的是这样实现的：一种低成本芯片扇出结构的封装方法，所述方法包括以下工艺步骤：
步骤一、取载体基板；
步骤二、在载体基板上预先形成对位图形，在预先形成对位图形的载体基板上贴上临时粘结膜；
步骤三、将芯片倒装至贴有临时粘结膜的载体基板上；
步骤四、将带有芯片的载体基板用塑封体进行包封，形成重构基板；
步骤五、将包封后形成的重构基板与载体基板剥离；
步骤六、在重构基板上罩上掩膜板，通过光刻或者激光的方式在掩膜板上形成掩膜图形开口；
步骤七、利用离子镀的方式在形成掩膜图形开口的重构基板上形成再布线金属；
步骤八、移除掩膜板；
步骤九、在形成再布线金属的重构基板上印刷或者贴再布线金属保护膜；
步骤十、在再布线金属保护膜上应用激光打出开口图形；
步骤十一、在步骤十形成的开口图形处植球并回流，形成金属凸点。
本发明的理念是采用利用基板作为临时载体，完成低成本的重构基板的制备，然后在重构基板上进行离子镀和激光开口工艺。该过程避开了圆片包封、光刻、电镀、腐蚀等诸多高成本工艺过程，实现芯片扇出结构的低成本封装。
本发明的有益效果是：
本发明的低成本芯片扇出结构封装方法，可极大程度的降低工艺难度和工艺成本，可实现低成本芯片扇出结构的规模化生产。
附图说明
图1~图11为本发明低成本芯片扇出结构的封装方法各工序实施例图。
图12为以往芯片扇入结构平面图。
图13为以往芯片扇出结构平面图。
图中附图标记：
载体基板2-1、临时粘结膜2-2、芯片2-3-1、芯片2-3-2、塑封体2-4、掩膜板2-5-1、掩膜图形开口2-5-2、再布线金属2-6、再布线金属保护膜2-7、开口图形2-7-1、金属凸点2-8；
芯片硅基体W-1、金属电极W-2、再布线金属W-3、金属凸点W-4、芯片一F-1、芯片二F-2、芯片三F-3、塑封基体F-4、再布线金属F-5、金属电极F-6、金属凸点F-7。
具体实施方式
参见图1~图11，图1~图11为本发明的无光刻低成本芯片扇出结构的封装方法各工序实施例图。由图1~图11可以看出，本发明低成本芯片扇出结构的封装方法，所述方法包括以下工艺步骤：
步骤一、取载体基板2-1，如图1；
步骤二、在载体基板2-1上预先形成对位图形，载体基板尺寸与现有的倒装机台加载能力相匹配，通常为250X80、 210x70mm；在预先形成对位图形的载体基板上贴上临时粘结膜2-2，该临时粘结膜应具备双面粘结性能，能够经受一定的工艺温度，如图2；
步骤三、将单个或多个芯片2-3-1/ 2-3-2倒装至贴有临时粘结膜的载体基板上，通过临时粘结膜固定，如图3；
步骤四、将带有芯片的载体基板用塑封体2-4进行包封，形成重构基板，包封厚度以大于芯片厚度为准，多个芯片则需要以高过最高芯片高度为准，如图4；
步骤五、将包封后形成的重构基板与载体基板剥离，如图5；
步骤六、在重构基板上罩上掩膜板2-5-1、2-5-2，如图6；
步骤七、利用离子镀的方式在形成掩膜图形开口的重构基板上形成再布线金属2-6，如图7；
步骤八、移除掩膜板，如图8；
步骤九、在形成再布线金属的重构基板上印刷或者贴再布线金属保护膜2-7，如图9；
步骤十、在再布线金属保护膜2-7上应用激光打出开口图形2-7-1，如图10；
步骤十一、在步骤十形成的开口图形处植球并回流，形成金属凸点2-8，如图11。
所述芯片为单个芯片或多个芯片，芯片类型包括无源器件和有源器件等。

Claims (1)

1.一种芯片扇出结构的封装方法，其特征在于：所述方法包括以下工艺步骤：
步骤一、取载体基板，载体基板尺寸为长250×宽70mm；
步骤二、在载体基板上预先形成对位图形，在预先形成对位图形的载体基板上贴上临时粘结膜；
步骤三、将芯片倒装至贴有临时粘结膜的载体基板上；
步骤四、将带有芯片的载体基板用塑封体进行包封，形成重构基板；
步骤五、将包封后形成的重构基板与载体基板剥离；
步骤六、在重构基板上罩上掩膜板，通过光刻或者激光的方式在掩膜板上形成掩膜图形开口；
步骤七、利用离子镀的方式在形成掩膜图形开口的重构基板上形成再布线金属；
步骤八、移除掩膜板；
步骤九、在形成再布线金属的重构基板上印刷或者贴再布线金属保护膜；
步骤十、在再布线金属保护膜上应用激光打出开口图形；
步骤十一、在步骤十形成的开口图形处植球并回流，形成金属凸点。
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TWI476841B (zh) * 2012-03-03 2015-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI509767B (zh) 2013-12-13 2015-11-21 Universal Scient Ind Shanghai 電子封裝模組及其製造方法
CN104716102B (zh) * 2013-12-13 2017-07-21 环旭电子股份有限公司 电子封装模块及其制造方法
CN105161433A (zh) * 2015-09-28 2015-12-16 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装方法
WO2018165818A1 (zh) * 2017-03-13 2018-09-20 深圳修远电子科技有限公司 电路扇出方法
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