CN101221915B - 功率mosfet的晶片级芯片规模封装 - Google Patents

功率mosfet的晶片级芯片规模封装 Download PDF

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CN101221915B
CN101221915B CN2007103080328A CN200710308032A CN101221915B CN 101221915 B CN101221915 B CN 101221915B CN 2007103080328 A CN2007103080328 A CN 2007103080328A CN 200710308032 A CN200710308032 A CN 200710308032A CN 101221915 B CN101221915 B CN 101221915B
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power mosfet
wafer level
scale
encapsulation
level chip
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CN101221915A (zh
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冯涛
孙明
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Chongqing Wanguo Semiconductor Technology Co ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明公开了一种功率MOSFET的晶片级芯片规模封装方法，该方法包括：化学镀晶片背面以及晶片正面上的多个接触区，和在将晶片切割成多个功率MOSFET芯片之前在经镀覆的多个接触区上形成焊球的步骤。在可替代的实施例中，该方法包括：在晶片背面设置永久保护层，化学镀晶片正面的多个接触区，和在将晶片切割成多个功率MOSFET芯片之前在经镀覆的多个接触区上形成焊球的步骤。

Description

功率MOSFET的晶片级芯片规模封装
技术领域
本发明涉及功率电子器件的封装，更具体地涉及一种功率MOSFET的晶片级芯片规模封装及相关封装工艺。
背景技术
晶片级芯片规模封装产生具有相似于或稍大于半导体芯片的尺寸的半导体封装。通常，半导体封装形成在具有多个半导体芯片的晶片上，然后独立的封装从该晶片上切割而成。
在功率MOSFET的情况下，源极和栅极触点区域通常位于芯片的正面，而漏极位于金属化的芯片背面。在功率MOSFET的晶片级芯片规模封装中，漏极必须延伸到芯片正面，或者可以用包括两个芯片的共漏结构，使用于电连接到印刷电路板的焊球能够形成在芯片的同一个正面的金属区上。但是，在各种情况下，金属化的背面还是必须的和/或有利的。
在功率MOSFET的晶片级芯片规模封装的制造中存在特定的挑战。更具体地，在下凸点金属镀层(UBM，Under Bump Metallization)工艺中常规使用化学镀，因为不需要掩模，因此既简单成本又低。由于背面金属通常与晶片正面的金属不同，如果背面没有适当保护，则在化学镀处理期间可能发生化学镀剂的污染。
常规上，在化学镀工艺中阻挡化学镀剂和化学镀温度的薄膜带或光刻胶的临时保护层被涂敷于背面金属上。化学镀工艺完成之后，临时保护层必须去除。涂敷和后继的去除临时保护层的步骤增加了封装工艺的总体复杂性，提高了成本却降低了产量。
作为对保护晶片背面的替代，在化学镀步骤之后可以进行背面研磨和背面金属化的步骤。但是，该工艺流程也不是总是能进行和/或方便的。
因此就存在对于功率MOSFET的晶片级芯片规模封装工艺的克服先有技术的限制的需要。最好该工艺对下凸点金属镀层采用化学镀并且提供易于以低成本和高效率的方式制造的功率MOSFET的晶片级芯片规模封装。
发明内容
本发明的目的在于提供一种功率MOSFET的晶片级芯片规模封装，其对下凸点金属镀层采用化学镀，并且制造成本低，制造效率高。
为达上述目的，本发明提供一种功率MOSFET的晶片级芯片规模封装，该方法包括如下步骤：向晶片的背面材料层化学镀Ni，以及向晶片正面上的多个接触区化学镀Ni；在经镀覆的多个接触区上形成焊球；切割晶片以形成多个功率MOSFET芯片。
本发明还提供一种制造功率MOSFET的晶片级芯片规模封装的方法，该方法包括如下步骤：在晶片背面设置永久保护层；向晶片正面的多个接触区化学镀Ni；在经镀覆的多个接触区上形成焊球。
本发明还提供一种制造功率MOSFET的晶片级芯片规模封装的方法，该方法包括如下步骤：在晶片背面设置永久坯衬底；通过溅射和电解镀下凸金属化晶片正面的多个接触区；在经镀覆的多个接触区上形成焊球。
本发明提供的一种功率MOSFET的晶片级芯片规模封装，其对下凸点金属镀层采用化学镀，并且制造成本低，制造效率高。
为了使下文对本发明的详尽叙述以及本发明对该技术领域的贡献能得到更好的理解，对本发明的较重要的特征必须进行即使不全面也应该概括的说明。当然，本发明还有其它的特征，这些特征也将在下文进行叙述并且形成本文附后的权利要求的主题内容。
在该方面，在详尽解释本发明的至少一个实施例之前，应该理解的是，本发明在其应用中不限于下文的叙述中阐明的和附图中图解的功能性组件的细节以及这些组件的设置。本发明能够实现其它的实施例并且能够以各种方式实施和执行。还有，应该理解的是，本文采用的措词和术语以及摘要是为了叙述的目的而不应该被认为是限制。
这样，本技术领域的熟练人员将理解，本发明根据的原理可以容易地利用为设计实行本发明的若干目的的其它方法和系统的基础。因此，重要的是，权利要求被认为包括不背离本发明的精神和范围的这样的等效构造。
附图说明
图1是说明制造根据本发明的功率MOSFET的晶片级芯片规模封装的示例性方法的流程图；
图2是图1所示方法中的一个步骤的示意图；
图3是图1所示方法中的另一个步骤的示意图；
图4是图1所示方法中的另一个步骤的示意图；
图5是说明制造根据本发明的功率MOSFET的晶片级芯片规模封装的另一种示例性方法的流程图；
图6是图5所示方法中的一个步骤的示意图；
图7是图5所示方法中的另一个步骤的示意图；
图8是图5所示方法中的另一个步骤的示意图；
图9是图5所示方法中的另一个步骤的示意图；
图10是说明制造根据本发明的功率MOSFET的晶片级芯片规模封装的还有一种示例性方法的流程图；
图11是图10所示方法中的一个步骤的示意图；
图12是图10所示方法中的另一个步骤的示意图；
图13是图10所示方法中的另一个步骤的示意图；
图14是图10所示方法中的另一个步骤的示意图；以及
图15是根据本发明的共漏功率MOSFET封装的示意图。
具体实施方式
下文将参考结合附图1-附图15附图对本发明进行详尽叙述，所提供的叙述作为本发明的说明性的实施例，使本技术领域的熟练人员能够实践本发明。应该注意，下文提及的附图和实例的意义并不是限制本发明的范围。在本发明的一定的组件能够部分或全部用已知的组件实施的地方，仅对这样的已知组件中对理解本发明必须的部分进行叙述而省略对其他部分的详述，以免不突出本发明的特征。另外，本发明也通过说明的方式涵盖与本文涉及的各个组件等效的当前已知的和将来能够理解的等效内容。
本发明发现了在芯片正面具有栅区，源区和漏区，背面电极通过重掺杂沉穴或其它电连接类型电连接到正面区域的诸如侧MOSFET或垂直MOSFET的漏极电连接的两个或多个MOSFET的共漏功率MOSFET芯片结构或单功率MOSFET芯片结构的芯片级芯片规模封装的适用范围。在所有这些方面背面金属仍是需要的，但是背面金属上不需要制作电接触点。
下文将参考图1到图4讨论总体标以100的示例性功率MOSFET的晶片级芯片规模封装方法。在步骤110，接收其上已经形成多个功率MOSFET芯片的晶片200。晶片200包括提供与芯片触点的连接的多个接触区210。晶片200的背面215包括材料层220，该材料可以包括能够被化学镀又不污染镀槽的Al或Zn。最好该材料层220由Ti/Al或Ti/Al合金形成。
接着在步骤120进行Ni化学镀，接着是Au浸润以镀覆多个接触区210和金属化的背面215。如图3所示，Ni层230被镀覆到接触区210上，Ni层240被镀覆到金属化的背面215上。金层235被淀积到Ni层230上，金层245被镀覆到Ni层240上。
在步骤130，在经镀覆的接触区210上形成焊球250，在步骤140切割晶片。结果的功率MOSFET的晶片级芯片规模封装提供了保护和向晶片背面良好的焊接能力。结果的背面也有利于进行激光标记刻制。
关于本发明的另一个方面，下文将参考图5到图9讨论总体标以500的功率MOSFET的晶片级芯片规模封装方法。在步骤510，接收其上已经形成多个功率MOSFET芯片的晶片600。晶片600包括提供与芯片触点的连接的多个接触区610。接触区610最好是Al或Al合金。晶片600的背面615通常包括Ti/Ni/Ag层620。
在步骤520，永久的钝化层625被淀积到Ti/Ni/Ag层620上。该永久钝化层625可以通过旋转涂敷，PVD，CVD等方法淀积。在本发明的另一个方面，可以用高温薄膜带替代永久钝化层625。永久钝化层和高温薄膜带可以包括玻璃，氮化硅，PTFE和聚酰胺。
接着在步骤530进行化学镀Ni，接着是金浸润以镀覆多个接触区610。如图7所示，Ni层630被镀覆到接触区610上。金层635被淀积到Ni层630上。在化学镀Ni期间永久钝化层625保护金属化的背面615并防止诸如Ag的背面金属污染化学镀剂。
在步骤540在经镀覆的接触区610上形成焊球650，在步骤550切割晶片。晶片级芯片规模封装方法500提供对晶片背面的保护并更易于进行激光标记刻制。
关于本发明的另一个方面，下文将参考图10到图14讨论总体标以1000的功率MOSFET的晶片级芯片规模封装方法。在步骤1010，接收其上已经形成多个功率MOSFET芯片的晶片1100。晶片1100包括提供与芯片触点的连接的多个接触区1110。接触区1110最好是Al或Al合金。晶片1100的背面1115通常包括Ti/Ni/Ag层1120。
在步骤1120，永久的坯衬底1140用热导电粘结剂或环氧树脂层1130附贴到Ti/Ni/Ag层1120上。该永久坯衬底1140向晶片背面提供保护以及增强机械强度。
接着在步骤1030进行化学镀Ni，接着是金浸润以镀覆多个接触区1110。如图13所示，Ni层1130被镀覆到接触区1110上。金层1135被淀积到Ni层1130上。在化学镀Ni期间永久坯衬底1140保护金属化的背面1115并防止Ti/Ni/Ag污染镀槽。
在替代的实施例中，诸如永久坯衬底1140的永久坯衬底可以用于提供UBM工艺中的保护层以及支撑层。
在步骤1040在经镀覆的接触区1110上形成焊球1150，在步骤1050切割晶片。
虽然所叙述的功率MOSFET的晶片级芯片规模封装方法1000包括化学镀步骤1030，但可以用其它的UBM工艺镀覆接触区1110。例如通过包括溅射接着是电解镀的工艺形成的Ni-V/Cu可以替代化学镀Ni步骤1030。
本发明的功率MOSFET的晶片级芯片规模封装方法提供易于以低成本高效率的方式制造的功率MOSFET的晶片级芯片规模封装。图15显示在共漏功率MOSFET 1500的切割之后根据本发明要求保护的工艺的结果的晶片级芯片规模封装的正视图。共漏功率MOSFET 1500包括同一个芯片上并排形成的两个MOSFET 1501和1502，漏极通过衬底1510和金属层1520电连接。MOSFET 1501有两个源区S1和一个栅区G1，都与焊球相连。MOSFET1502有两个源区S2和一个栅区G2，也都与焊球相连。在该示例性的布局中，焊球的直径约为370μm，各个区之间的间隔约为650μm，而整个芯片的尺寸约为1500×2500μm。
显而易见，上述实施例可以有多种方式的变化而不背离本发明的范围。另外，具体实施例的各个方面可以包含与同一实施例的其它方面无关的受专利保护的主题内容。还有，不同实施例的各个方面可以组合到一起。因此，本发明的范围应该由附后的权利要求及其法定等效内容确定。

Claims (19)

1.一种制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，该方法包括如下步骤：
向晶片的背面材料层化学镀Ni，以及向晶片正面上的多个接触区化学镀Ni；和
在经镀覆的多个接触区上形成焊球。
2.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，该方法进一步包括切割晶片以形成多个功率MOSFET芯片的步骤。
3.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的接触区包括Al。
4.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的接触区包括Al合金。
5.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的背面材料层包括Ti/Al。
6.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的背面材料层包括Ti/Al合金。
7.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的背面材料层包括从由Ti/Zn，Ti/Pd组成的组合中选择的金属或用作化学镀Ni的籽晶层的任何其它金属。
8.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的功率MOSFET包含共漏功率MOSFET芯片。
9.如权利要求1所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的多个接触区包括源，栅和漏接触区。
10.一种制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，该方法包括如下步骤：
在晶片背面设置永久保护层；
向晶片正面的多个接触区化学镀Ni；和
在经镀覆的多个接触区上形成焊球。
11.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的保护层包括钝化层。
12.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的保护层包括能够耐受化学镀剂以及与化学镀和焊料回流相关的温度的薄膜带。
13.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的保护层包括坯衬底。
14.如权利要求13所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的坯衬底通过粘结剂层粘结到所述的背面。
15.如权利要求13所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的坯衬底通过环氧树脂层粘结到所述的背面。
16.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，该方法进一步包括切割晶片以形成多个功率MOSFET芯片规模封装的步骤。
17.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的接触区包括Al。
18.如权利要求10所述的制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，所述的接触区包括Al合金。
19.一种制造功率MOSFET的晶片级芯片规模封装的方法，其特征在于，该方法包括如下步骤：
在晶片背面设置永久坯衬底；
通过溅射和电解镀下凸金属化晶片正面的多个接触区；和
在经镀覆的多个接触区上形成焊球。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421214B2 (en) * 2007-10-10 2013-04-16 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
CN102097404B (zh) * 2009-12-10 2013-09-11 万国半导体有限公司 低衬底电阻的晶圆级芯片尺寸封装及其制造方法
JP2013004572A (ja) * 2011-06-13 2013-01-07 Mitsubishi Electric Corp 半導体装置の製造方法
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US8980743B2 (en) * 2012-06-12 2015-03-17 Flipchip International Llc Method for applying a final metal layer for wafer level packaging and associated device
CN103219243B (zh) * 2012-09-28 2016-12-21 复旦大学 图案化金属线路的制备方法
CN106997900A (zh) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 半导体结构、其形成方法及测试方法
US9640497B1 (en) * 2016-06-30 2017-05-02 Semiconductor Components Industries, Llc Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods
CN111540681A (zh) * 2020-05-29 2020-08-14 上海华虹宏力半导体制造有限公司 应用于igbt芯片的金属化方法
CN111710613A (zh) * 2020-06-18 2020-09-25 宁波芯健半导体有限公司 一种晶圆级芯片封装方法
CN113436981B (zh) * 2021-06-29 2022-10-04 山东宝乘电子有限公司 一种在功率mosfet芯片的栅接触区制作焊球的方法
EP4310891A1 (en) * 2022-07-20 2024-01-24 Infineon Technologies Austria AG Semiconductor device, battery management system and method of producing a semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617696B1 (en) * 2002-03-14 2003-09-09 Fairchild Semiconductor Corporation Supporting control gate connection on a package using additional bumps
CN1536631A (zh) * 2003-04-09 2004-10-13 全懋精密科技股份有限公司 半导体封装基板的电性连接垫电镀金属层结构及其制法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3230098A (en) * 1962-10-09 1966-01-18 Engelhard Ind Inc Immersion plating with noble metals
US5775569A (en) * 1996-10-31 1998-07-07 Ibm Corporation Method for building interconnect structures by injection molded solder and structures built
US6436816B1 (en) * 1998-07-31 2002-08-20 Industrial Technology Research Institute Method of electroless plating copper on nitride barrier
KR100462980B1 (ko) * 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정
KR100721139B1 (ko) * 2000-02-10 2007-05-25 인터내쇼널 렉티파이어 코포레이션 단일면 상에 돌출 접촉부를 갖는 수직 전도성의 플립칩디바이스
US6683344B2 (en) * 2001-09-07 2004-01-27 Ixys Corporation Rugged and fast power MOSFET and IGBT
US6911230B2 (en) * 2001-12-14 2005-06-28 Shipley Company, L.L.C. Plating method
JP3750680B2 (ja) * 2003-10-10 2006-03-01 株式会社デンソー パッケージ型半導体装置
JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
US20050230262A1 (en) * 2004-04-20 2005-10-20 Semitool, Inc. Electrochemical methods for the formation of protective features on metallized features
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617696B1 (en) * 2002-03-14 2003-09-09 Fairchild Semiconductor Corporation Supporting control gate connection on a package using additional bumps
CN1536631A (zh) * 2003-04-09 2004-10-13 全懋精密科技股份有限公司 半导体封装基板的电性连接垫电镀金属层结构及其制法

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