CN103715166B - 用于部件封装件的装置和方法 - Google Patents

用于部件封装件的装置和方法 Download PDF

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Publication number
CN103715166B
CN103715166B CN201310018281.9A CN201310018281A CN103715166B CN 103715166 B CN103715166 B CN 103715166B CN 201310018281 A CN201310018281 A CN 201310018281A CN 103715166 B CN103715166 B CN 103715166B
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semiconductor devices
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component
semiconductor device
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CN103715166A (zh
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陈志华
陈承先
萧景文
曾明鸿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种部件封装件和形成方法。第一部件封装件可包括第一半导体器件，具有附接至第一半导体器件的两侧的一对中介件。每个中介件可包括形成在其中的迹线以提供电连接至形成在各中介件的表面上的导电部件。多个通孔可提供将中介件相互电连接。第一中介件可提供至印刷电路板或者后续半导体器件的电连接。第二中介件可提供至第二半导体器件和第二部件封装件的电连接。第一和第二部件封装件可组合以形成封装件层叠(“PoP”)结构。本发明还提供了用于部件封装件的装置和方法。

Description

用于部件封装件的装置和方法
技术领域
本发明涉及半导体技术领域，更具体地，涉及用于部件封装件的装置和方法。
背景技术
集成电路(“IC”)的尺寸、形成、密度和封装的改进已经引导半导体产业经历快速成长。集成密度的改进已经使得IC部件尺寸减小，这使得更多部件集成到给定区域内。
提高电路密度的一种改进是两个IC管芯在相互的顶部上堆叠(一个管芯叠在另一个管芯上)以形成称作的三维(“3D”)IC。在典型3D IC形成工艺中，两个管芯接合在一起并且电连接形成每个管芯和衬底上的接触焊盘之间。例如，两个管芯在相互的顶部上堆叠并且位于下面的管芯连接至衬底。衬底中的通孔(“TV”)将管芯与衬底的反面上的导电焊盘连接。然后，可用电连接将导电焊盘连接至印刷电路板(“PCB”)等等。
提高电路密度的另一种3D封装件称为“封装件层叠”(“PoP”)结构，其中连接至各自的衬底的多个管芯可“堆叠”在相互的顶部上并且连接在一起。为了形成PoP结构，第一管芯电连接至第一衬底以形成第一电路。第一电路包括第一连接点用于连接至第二电路。第二电路包括第二管芯以及在其每侧上具有连接点的衬底。第一电路堆叠并且电连接在第二电路的顶部上以形成PoP结构。然后，可使用电连接将PoP结构电连接至PCB等。
存储电路与各种其他电路部件堆叠在3D IC中以形成存储模块。这些存储模块可通常包括逻辑电路、一个或者多个处理器或者一个或者多个应用处理器单元(“APU”)，可能开发成用户定义的专用集成电路(“ASIC”)。设置在3D IC中的存储器模块通常包括连接至衬底的APU，并且TV将APU连接至衬底的反面上的焊盘。TV增加了3D IC的总高度以及3D IC的设计和制造复杂度。TV还降低了存储电路的产量。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种装置，包括：
第一半导体器件；
第二半导体器件；
第一再分布层(RDL)，电连接至所述第一半导体器件的第一侧；
第二RDL，设置在所述第一半导体器件的第二侧，所述第二RDL与所述第二半导体器件电连接；
第一材料，设置在所述第一RDL和所述第二RDL之间；以及
多个通孔，延伸穿过所述第一材料，所述多个通孔将所述第一RDL与所述第二RDL电连接。
在可选实施例中，所述多个通孔延伸穿过与所述第一半导体器件相邻的一个或者多个区域中的所述第一材料。
在可选实施例中，所述通孔由选自由铜、铝、金、钨和它们的组合所组成的组中的材料来制造。
在可选实施例中，所述第一半导体器件是应用处理器单元。
在可选实施例中，所述第二半导体器件是存储器IC管芯。
根据本发明的另一个方面，还提供了一种装置，包括：
第一封装部件，所述第一封装部件包括：
第一半导体器件，具有第一侧和第二侧；
第一再分布层(RDL)，电连接至所述第一半导体器件的所述第一侧；
第二RDL，设置在所述第一半导体器件的所述第二侧，所述第二RDL电连接至第二半导体器件，所述第二RDL具有形成在其上的多个第一导电部件；
第一材料，设置在所述第一RDL和所述第二RDL之间；
多个通孔，延伸穿过所述第一材料，所述多个通孔将所述第一RDL与所述第二RDL电连接；
第二封装部件，所述第二封装部件包括：
第三半导体器件；以及
中介件，电连接至所述第三半导体器件，所述中介件具有形成在其上的多个第二导电部件，其中所述第二导电部件电连接至所述第二RDL的所述第一导电部件。
在可选实施例中，所述第一半导体器件是应用处理器单元。
在可选实施例中，所述第二半导体器件是存储器IC管芯。
在可选实施例中，所述第三半导体器件是存储器IC管芯。
根据本发明的又一方面，还提供了一种方法，包括：
在第一载体上形成第一金属层；
在所述第一金属层上形成多个导电柱；
将第一半导体器件的第一侧附接至所述第一金属层；
密封所述第一半导体器件和所述多个导电柱；
在所述第一半导体器件的第二侧形成第一再分布层(RDL)，其中所述第一RDL与所述导电柱和所述第一半导体器件电连接；
将第二载体附接至所述第一RDL；
去除所述第一载体和所述第一金属层；以及
在所述第一半导体器件的所述第一侧形成第二RDL以形成第一封装部件，所述第二RDL与所述多个导电柱电连接。
在可选实施例中，所述方法进一步包括：将第二半导体器件与所述第二RDL连接。
在可选实施例中，所述多个导电柱设置在与所述第一半导体器件的垂直部分相邻的区域中。
在可选实施例中，所述多个导电柱由铜、铝、钨、金或它们的组合的材料制造。
在可选实施例中，所述第一半导体器件是应用处理器单元。
在可选实施例中，所述第二半导体器件是存储器IC管芯。
在可选实施例中，所述第一半导体器件和所述导电柱被密封在选自由树脂、环氧树脂、聚合物和它们的组合所组成的组的材料中。
在可选实施例中，所述方法进一步包括：将所述第一封装部件附接至切割胶带；从所述第一封装部件去除所述第二载体；分割所述第一封装部件；以及，将第二封装部件连接至所述第一封装部件以形成封装层叠(PoP)结构。
在可选实施例中，所述连接进一步包括：在所述第二RDL上的第二组导电部件和所述第二封装部件上的第一组导电部件之间形成电连接。
在可选实施例中，所述方法进一步包括：通过所述第一RDL上的多个导电连接件将所述PoP结构连接至印刷电路板。
在可选实施例中，所述第二封装部件包括一个或者多个存储器IC管芯。
附图说明
为更完整的理解本实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出了用于说明实施例的结构的截面图；以及
图2-图16示出了形成实施例的各中间阶段。
具体实施方式
下面，详细讨论本实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅示出了制造和使用所公开的发明主旨的具体方式，并且不用于限制不同实施例的范围。
首先参照图1，示出了用于说明实施例应用的一种实例PoP结构100。PoP结构100可包括第一部件封装件110和第二部件封装件160。第一部件封装件110和第二部件封装件160可电连接在一起以形成PoP结构100，将在此详细阐述。
第一部件封装件110可包括第一管芯120。第一管芯120可具有第一侧和第二侧。第一侧本文还称为“前侧”，而第二侧还称为“背侧”。如下面更详细描述的，第一管芯120前侧可以电连接至第一再分布层(“RDL”)113。第二RDL 116可以形成在第一管芯120背侧上。如下面更详细描述的，第二管芯140可以电连接至第二RDL 116。第一RDL113和第二RDL 116可以使用第一组TV 111(例如，通孔组件)电连接在一起，第一组TV 111可以设置在围绕第一管芯120的第一密封材料112中。
第一RDL 113可以包括具有形成在其内的第一金属迹线114的一个或者多个介电层。第一迹线114可由铜、铝、金或者其他类似的材料形成以提供穿过第一RDL 113的导电通路。第一RDL 113可使用一种或者多种金属蚀刻工艺(Subtractive Etch Process)、单镶嵌技术和/或双镶嵌技术形成。第一RDL 113可具有形成在其上的第一组导电部件115，第一组导电部件115还可连接至第一迹线114。第一组导电部件115可以由铜、铝、金或者其他类似的材料形成。第一组导电部件115可以具有形成在其上的第一组导电连接件130，第一组导电连接件130可提供用于PoP结构100至PCB、高密度互连件、衬底、硅衬底、有机衬底、陶瓷衬底、层压衬底、另一种半导体封装件等的电连接。在各种实施例中，第一组导电连接130可包括无铅焊料、共晶铅、导电柱、它们的组合，和/或类似物。
第一RDL 113以及对应的第一迹线114和第一组导电部件115可提供对第一管芯120的信号再分布以及附加支持。第一RDL 113还可在第一管芯120和PCB或者PoP结构100可以安装到其上的其他电子器件之间提供热应力去除。在一种实施例中，模塑底部填充物(“MUF”)(未示出)可施加在第一组导电部件115之间以保护部件之间的区域免受环境或者外部污染。在一种实施例中，第一钝化层(未示出)可以形成在第一管芯120和第一RDL 113之间。第一钝化层可以为聚酰亚胺层、PBO、BCB、非光敏聚合物，并且在可选实施例中可由氮化物、碳化物或者其他电介质形成。
如图1所示，第一RDL 113可没有TV，这可降低第一封装件110的总高度以及降低第一封装件110的设计和制造复杂性。作为附加的优势，第一RDL 113中缺少TV相对于在类似位置的中介板中包括TV的设计可提高PoP结构100的制造产量。
第二RDL 116可包括一个或者多个介电层，所述介电层具有形成在其内的第二金属迹线117。第二迹线117可由铜、铝、金或者其他类似的材料形成以提供穿过第二RDL 116的导电通路。第二RDL 116可使用一种或者多种金属蚀刻工艺、单镶嵌技术和/或双镶嵌技术形成。第二RDL 116可具有形成在其上的第二组导电部件118和第三组导电部件119，每组导电部件还可连接至第二迹线117。第二管芯140可具有形成在其上的第四组导电部件141。第二、第三和/或第四组导电部件118、119、141分别由铜、铝、金或者其他类似的材料形成。第二管芯140可通过第二组导电连接件150连接至第二RDL 116，第二组导电连接件150可连接至形成在第二RDL116上的第二组导电部件118和第二管芯140的第四组导电部件141。在一种实施例中，钝化层(未示出)可形成在第一管芯120和第二RDL 116之间。
第二管芯140可通过由第四组导电部件141、第二组导电连接件150、第二组导电部件118，第二迹线117、第一组TV 111、形成在第一管芯120前侧上的第一线路114和导电部件(未示出)形成的导电通道电连接至第一管芯120。第二迹线117、第一组TV 111、第一迹线114、第一组导电部件115以及第一组导电连接件130还可提供第二管芯140和PCB或者中介件(PoP结构100可安装至其处)之间的电连接。
在一种实施例中，第一管芯120可以为APU。在一种实施例中，第二管芯140可以为存储器IC，例如，动态RAM(例如，宽数据字(“宽I/O”))DRAM或者DDR RAM。在另一种实施例中，第二管芯140可以为静态RAM(例如，SRAM)，或者非易失性器件(例如，EPROM或者FLAM存储器)。
如所述的，TV 111不需要路由穿过第一管芯。在第一管芯120可以为APU和第二管芯可以为存储器IC的一些实施例中，去除路由穿过第一管芯120的TV可比包括路由穿过这种管芯的TV的封装件支持更高的I/O带宽存储器IC。可以意识到通过去除路由穿过第一管芯120的TV的另一种优势是在不需费时间和金钱重新设计第一部件封装件110的情况下，提高使第一部件封装件110适应支持不同的管芯类型(对于第一管芯120和第二管芯140)的灵活性，其中不同的管芯类型根据不同制造工艺(即45nm、65nm等)构建而成或者由不同半导体材料(即，GaAs)制造而成。与使用穿过第一管芯120的TV的技术相比，这种增加的灵活性可降低制造和测试成本(即，TV信号完整性特征)以及减少对技术重设计来说市场的时间。而且，去除路由穿过第一管芯120的TV可提高第一部件封装件110的制造产量。
在各种实施例中，第一组TV 111可由铜、铝、金或类似物形成。在各种实施例中，第二管芯140可使用凸块下金属化结构、微凸块下金属化结构、金属柱、金属柱凸块等连接至第二RDL 116。在各种实施例中，第二组导电连接件150可包括无铅焊料、共晶铅等等。在各种实施例中，第一密封材料112可包括诸如树脂、环氧树脂、聚合物等并且可保护第一部件封装件110中的部件免受环境影响或者污染。在一种实施例中，第一部件封装件110可包括设置在第一组导电部件115和第一组导电连接件130之间的密封剂或者底部填充物(未示出)。
如上所述，PoP结构100可包括第二部件封装件160。第二部件封装件160可包括电连接至中介件162的一个或者多个第三管芯161。如本文进一步详述的，第二部件封装件160可电连接至第一部件封装件110。中介件162可以为陶瓷、塑料、层压板、膜、电介质或者其他类似的层并且可包括第三金属迹线或者RDL 165。中介件162还可以为PCB、衬底、硅衬底、有机衬底、陶瓷衬底，层压衬底、另一种半导体封装件等。第三迹线165可由铜、铝、金或者其他材料形成以提供穿过中介件162的导电通路。中介件162还可包括可由铜、铝、镍或其他类似材料形成的TV 166。
在第一侧上，中介件162可具有形成在其上的第五组导电部件163，第五组导电部件163还可电连接至第三迹线165。在相反的第二侧，中介件162可具有形成在其上的第六组导电部件167，第六组导电部件167还可电连接至第三迹线165。第五和第六组导电部件可由铜、铝、金或者其他类似材料形成。一个或者多个第三管芯161可通过第三组导电连接件164连接至第五组导电部件163。第三组导电连接件164可包括诸如可由铝、铜、金或者其他丝焊材料形成的细丝焊。在一种实施例中，第三组导电连接件164可例如使用热压焊(“TCB”)连接至第五组导电部件163。
图1示出了使用丝焊技术形成在第三管芯161之间(即，通过第三组导电连接件164)的电连接，仅用于说明目的。其他实施例可使用其他方法，例如，倒装、球栅阵列、TV、凸块下金属、导电柱等。
第二部件封装件160可进一步包括形成在部件上方的第二密封材料168以保护部件免受环境影响和/或外部污染。在各种实施例中，第二密封材料168可包括诸如树脂、环氧树脂、聚合物或类似物。第二部件封装件160可通过连接在第三组导电部件119和第六组导电部件167之间的第四组导电连接件170连接至第一部件封装件110。第四组导电连接件170可包括诸如免铅焊料、共晶铅、导电柱、它们的组合，和/或类似物。在一种实施例中，可分别对第三组导电部件119和第六组导电部件167中的一个或者两个都施加焊剂(未示出)。焊剂可在诸如以下操作期间施加：将第二RDL 116或者中介件162的表面分别浸在焊剂中或者涂覆在焊剂中。焊剂可有助于清洁中介件的导电部件的表面，从而帮助在第三和第六组导电部件119和167中的每个导电部件之间分别形成电接触。在另一种实施例中，MUF 180可以设置在第一部件封装件110和第二部件封装件160之间以保护第二RDL 116和中介件162之间的区域免受环境或者外部污染。
在一种实施例中，第三管芯161可以为动态RAM，例如，宽数据字DRAM、DDR RAM或者低功耗DDR(“LPDDR”)RAM。在另一种实施例中，第三管芯161可以为静态RAM(例如，SRAM)，或者非易失性器件(例如，EPROM或者FLASH存储器)。
图2-图16是形成一种实施例的各中间阶段的截面图。图2示出了根据本发明一种实施例的在第一载体210上设置第一金属层220以开始第一封装件110的形成的截面图。第一载体210可由各种材料形成，包括但不限于玻璃、硅、陶瓷、它们的组合和/或类似物。如图2所示，第一金属层220可使用第一粘附层230暂时安装在或者连接至第一载体220。如图2中所示，第一金属层220和第一粘附层230的厚度被放大，仅为了示例说明的目的。
在各种实施例中，第一金属层220可由诸如铜箔、铜合金、铝、钨、银、它们的组合等的导电材料形成。在各种实施例中，第一金属层220可由诸如环氧树脂或类似物形成。
在一种实施例中，第一金属层220可通过电化学或者电镀工艺形成。对于这种工艺，第一光刻胶掩模(未示出)可形成在第一粘附层230或者第一载体210上(在没有第一粘附层230的实施例中)。第一掩模可被蚀刻以为第一金属层220提供区域，然后第一金属层220使用诸如电镀技术形成在其上。
图3示出了在第一金属层220上形成第一组TV 111的截面图。第一金属层220可充当用于第一组TV 111的种子层，第一组TV 111可从此形成。在一种实施例中，TV 111可通过电化学沉积或者电镀工艺形成。对于这种工艺，第二光刻胶掩模(未示出)可形成在第一金属层220上。第二掩模可被蚀刻以为在第一金属层220上设置TV 111提供开口。然后，TV 111可使用诸如电镀技术形成在第一金属层220上并且掩模可随后去除。随着TV 111的形成，第一管芯120背侧可安装在第一金属层220上或者连接至第一金属层220。在第一管芯120正侧上可形成第一钝化层310和第七组导电部件312，第七组导电部件312可提供至第一管芯120的电连接。
在各种实施例中，第一组TV 111可由铜、铝、钨、金、它们的组合和/或类似物形成。在各种实施例中，第一钝化层310可以为聚酰亚胺层、PBO、BCB、非光敏聚合物，并且在可选的实施例中，可由氮化物、碳化物或者其他电介质形成。如图3中所示的TV 111还可称为导电柱。一旦围绕导电柱的密封材料(如下图4所述)形成，柱可称为TV 111。
如图4所示，第一密封材料112可形成在第一封装件中的部件上，包括但不限于第一管芯120和第一组TV 111。第一密封材料112可使用注入，模铸或者其他类似的工艺形成在部件上。在一种实施例中，第一密封材料112可覆盖第一管芯120前侧表面至预确定高度。在各种实施例中，第一密封材料112可包括诸如树脂、环氧树脂、聚合物或类似物并且可保护第一部件封装件110中的部件免受环境影响或者污染。现在参照图5，可通过研磨、精磨或者其他工艺从第一管芯120的前侧表面去除第一密封材料112以暴露第一管芯120和第七组导电部件312的顶面。
图6示出了第一RDL 113形成在第一管芯120前侧。第一RDL 113可使用一种或者多种金属蚀刻工艺、单镶嵌技术和/或双镶嵌技术形成。如所述的，第一RDL 113可包括第一金属迹线114并且可具有形成在其上的第一组导电部件115。根据本发明的一种实施例，第一RDL 113可形成大约60μm的高度，然而所述高度可随各种设计因素确定而改变，所述设计要素包括但不限于穿过第一RDL 113的第一迹线114的布线要求。
如图7所示，第一组导电部件115可具有形成在其上的第一组导电连接件130。在各种实施例中，第一组导电连接件130可包括免铅焊料、共晶铅、导电柱、它们的组合，和/或类似物。在一种实施例中，MUF 710可设置在第一组导电部件115和/或第一组导电连接件130之间以保护第一RDL 113免受环境影响或者外部污染。MUF 710可由诸如聚合物、环氧树脂或者其他类似材料形成。
现在参照图8，可通过第一组导电连接件130对第一管芯120进行第一功能测试。可进行功能测试以验证经由第一迹线114穿过第一RDL 113至第一管芯120的连接性。还可进行功能测试以验证第一管芯120的某些功能。
如图9所示，第二载体910可附加或者结合在与第一载体210相对的一侧。第二载体910可由各种材料形成，包括但不限于，玻璃、硅、陶瓷、它们的组合，和/或类似物。现在参照图10，可从第一管芯120的背侧区域去除或者去结合第一载体210。可进行研磨或者精磨工艺以从背侧区域去除第一金属层220和第一粘附层230(如图2所示)。
图11示出了第二RDL 116形成在第一管芯120背侧。第二RDL 116可使用一种或者多种金属蚀刻工艺、单镶嵌技术和/或双镶嵌技术形成。如前所述，第二RDL 116可具有形成在其上的第二组导电部件118和第三组导电部件119，第二组导电部件118和第三组导电部件119的每组还可连接至第二线路117。
如图12所示，第二管芯140可电连接至第二RDL 116。第二组导电连接件150可形成在第二管芯140的第四组导电部件141和第二RDL 116的第二组导电部件118之间。在各种实施例中，第二管芯140可使用凸块下金属结构、微凸块下金属结构、金属柱或类似物连接至第二RDL 116。在各种实施例中，第二组导电连接件150可包括免铅焊料、共晶铅等，其中第二管芯140可使用回流焊工艺连接至第二RDL 116。在另一种实施例中，第二管芯140可使用热压缩工艺连接至第二RDL 116。在一种实施例中，MUF(未示出)可设置在第二管芯140和第二RDL 116之间。根据本发明的一种实施例，从第一管芯120前侧至第二RDL 116的导电部件组之间的高度可以为大约90μm，所述高度相比于采用TV将第二管芯电连接至第一管芯的存储器封装件可提供封装件高度改进。
如图13所示，第一部件封装件110可附接至切割胶带1310并且可去接合或者去除第二载体910。如图14所示，可对第一封装件进行第二功能测试以验证经由第一组导电连接件130、第一和第二RDL 113、116(以及相应的迹线)、第二和第四导电部件118、141和第二组导电连接150形成的通过导电通路至第二管芯140的连接性。还可进行第二功能测试以验证第二管芯140的功能。
在图15中，可沿划线1510进行分割以形成如图1所示的第一部件封装件110。可通过切割或者分割工艺进行分割，其中机械或者激光锯可用于将第一部件封装件110的多个实例相互分离。随着分割，可从切割胶带1310移除第一部件封装件110。
现在参照图16，第二部件封装件160可连接至第一封装件110以形成PoP结构100，如图1所示。连接可通过可电连接在第三组导电部件119和第六组导电部件167之间的第四组导电连接件170进行。回流焊工艺可用于形成将第二部件封装件160连接至第一部件封装件110的电连接。第二部件封装件160可使用所描述的与第一部件封装件110的部件和形成类似的工艺和技术形成。
在一种实施例中，提供了一种装置。所述装置包括第一半导体器件、第二半导体器件、电连接至所述第一半导体器件的第一侧的第一RDL、设置在所述第一半导体器件的第二侧的第二RDL，电连接至所述第二半导体器件的所述第二RDL；设置在所述第一RDL和所述第二RDL之间的第一材料，以及延伸穿过所述第一材料的多个通孔，所述通孔将所述第一RDL与所述第二RDL电连接。
在另一种实施例中，提供了另一种装置。所述装置包括第一封装部件和第二封装部件。所述第一封装部件包括具有第一侧和第二侧的第一半导体器件，电连接至第一半导体器件的第一侧的第一再分布层(RDL)；设置在所述第一半导体器件的所述第二侧的第二RDL，电连接至第二半导体器件的第二RDL，所述第二RDL具有形成在其上的多个第一导电部件，第一材料设置在第一RDL和第二RDL之间，多个通孔延伸穿过所述第一材料，所述通孔将所述第一RDL与所述第二RDL电连接。所述第二封装部件包括第三半导体器件，以及电连接至第三半导体器件的中介件，所述中介件具有形成在其上的多个第二导电部件，其中第二导电部件电连接至第二RDL的第一导电部件。
在另一种实施例中，提供了一种方法。所述方法包括在第一载体上形成第一金属层，在所述第一金属层上形成多个导电柱，将第一半导体器件的第一侧附接至第一金属层，封装所述第一半导体器件和所述多个导电柱，在所述第一半导体器件的第二侧形成第一RDL，其中所述第一RDL电连接至所述导电柱和所述第一半导体器件，将第二载体附接至所述第一RDL，去除第一载体和第一金属层，以及在第一半导体器件的第一侧形成第二RDL以形成第一封装部件，所述第二RDL电连接至所述多个导电柱。
应当理解的是，上述提供了各实施例的一般描述并且这些实施例可包括许多其他部件。例如，实施例可包括凸块下金属层、钝化层、模塑料、附加管芯和/或衬底，以及类似物。另外，仅为了示例说明的目的，分别提供了衬底、第一、第二和第三管芯120、140和161的布置和设置，因此其他实施例可使用不同的结构，布置和设置。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
例如，本领域技术人员容易理解上面描述的结构或者步骤的顺序可以变化而仍在本申请的范围内。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (11)

1.一种用于形成半导体装置的方法，包括：
在第一载体上形成第一金属层；
在所述第一金属层上形成多个导电柱；
将第一半导体器件的第一侧附接至所述第一金属层；
密封所述第一半导体器件和所述多个导电柱；
在所述第一半导体器件的第二侧形成第一再分布层(RDL)，其中所述第一再分布层与所述导电柱和所述第一半导体器件电连接；
将第二载体附接至所述第一再分布层；
去除所述第一载体和所述第一金属层；以及
在所述第一半导体器件的所述第一侧形成第二再分布层以形成第一封装部件，所述第二再分布层与所述多个导电柱电连接。
2.根据权利要求1所述的用于形成半导体装置的方法，进一步包括：
将第二半导体器件与所述第二再分布层连接。
3.根据权利要求1所述的用于形成半导体装置的方法，其中，所述多个导电柱设置在与所述第一半导体器件的垂直部分相邻的区域中。
4.根据权利要求1所述的用于形成半导体装置的方法，其中，所述多个导电柱由铜、铝、钨、金或它们的组合的材料制造。
5.根据权利要求1所述的用于形成半导体装置的方法，其中，所述第一半导体器件是应用处理器单元。
6.根据权利要求2所述的用于形成半导体装置的方法，其中，所述第二半导体器件是存储器IC管芯。
7.根据权利要求1所述的用于形成半导体装置的方法，其中，所述第一半导体器件和所述导电柱被密封在选自由树脂、环氧树脂、聚合物和它们的组合所组成的组的材料中。
8.根据权利要求1所述的用于形成半导体装置的方法，进一步包括：
将所述第一封装部件附接至切割胶带；
从所述第一封装部件去除所述第二载体；
分割所述第一封装部件；以及
将第二封装部件连接至所述第一封装部件以形成封装层叠(PoP)结构。
9.根据权利要求8所述的用于形成半导体装置的方法，所述连接进一步包括：
在所述第二再分布层上的第二组导电部件和所述第二封装部件上的第一组导电部件之间形成电连接。
10.根据权利要求8所述的用于形成半导体装置的方法，进一步包括：
通过所述第一再分布层上的多个导电连接件将所述封装层叠结构连接至印刷电路板。
11.根据权利要求8所述的用于形成半导体装置的方法，其中，所述第二封装部件包括一个或者多个存储器IC管芯。
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