CN102652358A - 基于面板的引线框封装方法和装置 - Google Patents
基于面板的引线框封装方法和装置 Download PDFInfo
- Publication number
- CN102652358A CN102652358A CN2010800573376A CN201080057337A CN102652358A CN 102652358 A CN102652358 A CN 102652358A CN 2010800573376 A CN2010800573376 A CN 2010800573376A CN 201080057337 A CN201080057337 A CN 201080057337A CN 102652358 A CN102652358 A CN 102652358A
- Authority
- CN
- China
- Prior art keywords
- lead
- wire
- tube core
- recess
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 239000012212 insulator Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 27
- 238000005538 encapsulation Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 15
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000011230 binding agent Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 33
- 239000011521 glass Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910000881 Cu alloy Inorganic materials 0.000 description 5
- 229910004856 P—O—P Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 244000137852 Petrea volubilis Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01043—Technetium [Tc]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
封装的半导体管芯具有预先形成的引线框,该引线框具有中央凹进部分和多个导电引线。集成电路管芯具有顶表面和与其相对的底表面,所述顶表面具有多个接合焊盘,用于电连接到管芯。管芯被布置在所述中央凹进部分中,其中所述顶表面具有面向上的接合焊盘,且所述底表面与凹进部分接触。每个引线具有顶部部分和底部部分。所述引线被间隔开并且与中央凹进部分绝缘。导电层被沉积在管芯的顶表面和引线的顶部部分上并且被图案化以将所述管芯的特定的接合焊盘电连接到特定的导电引线。绝缘体覆盖导电层。本发明还涉及一种封装这种集成电路管芯的方法。
Description
技术领域
本发明涉及用于使用引线框在面板上封装半导体管芯的方法。本发明还涉及通过这种方法制造的装置,特别地,其中该装置能够封装堆叠封装(package-on-package stacking)。
背景技术
使用引线框封装半导体管芯是本领域中众所周知的。参考图1,示出使用引线框的封装的半导体管芯的截面图。现有技术的引线框20的平面图在图20中示出。封装的管芯10包括具有中央凹进部分14和多个间隔开的引线12的引线框20。集成电路管芯22具有顶表面24和底表面26,顶表面24具有电连接到集成电路管芯24中的各个电路元件的多个接合焊盘。管芯22位于凹进部分14中,使得管芯22的底表面通过导电膏剂留在凹进部分14上并且电连接到凹进部分14。凹进部分14由导电材料形成。多个接合线30将管芯22的顶表面上的特定的接合焊盘连接到特定的引线12的顶面。每个引线12具有与顶面相对的底面32,其将连接到印刷电路板(PCB)上的各电焊盘用于系统应用。凹进部分14还连接到在与引线12的底面32相同侧的印刷电路板上的电接触,通常是地。
在现有技术的方法中,管芯22首先被放置在预先形成的引线框20的凹进部分14上。管芯22可以借助粘合剂附着到凹进部分14以防止管芯22在后续步骤中移动。线接合机器将管芯22的特定的接合焊盘接合到特定的引线12的顶面。一旦所有引线已经被如此接合,则将树脂注入到模膛中以包封管芯22、线30和引线12的顶面并将管芯22、线30和引线12的顶面绝缘。然后将该结构单体化或切割,然后每个封装的管芯可以用于借助众所周知的技术,例如通过将封装的管芯10焊接在印刷电路板PCB上来连接到其它封装的半导体器件。在那种情况下,引线12的底面32和凹进部分14的底表面可以被焊接到PCB。由此,现有技术的封装的半导体管芯,如图1所示,具有到封装的管芯的仅仅一侧的电连接以连接到印刷电路板。
参考图2a,示出另一个现有技术的形成封装的半导体管芯40的另一方法中的第一步骤,该方法非常类似于图1所示和所描述的方法。在该方法中,该方法开始于具有顶面和底面的铜合金块42。光致抗蚀剂44被施加到该顶面和底面,并且在两面上形成掩蔽步骤。在除去光致抗蚀剂的未被掩蔽的部分之后,可焊材料46,例如锡,被溅射以填充被除去的部分。所得到的结构在图2b中示出。
然后除去光致抗蚀剂44,在铜合金42上留下可焊材料46。所得到的结构在图2c中示出。利用可焊材料46作为掩模,对铜合金42的顶面执行铜的湿法蚀刻。该蚀刻形成凹进中央部分50。所得到的结构在图2d中示出。
管芯22被放置在凹进腔50中,其中管芯22的接合焊盘面向外。然后将线接合到管芯22的接合焊盘和顶面上的可焊柱46。然后将绝缘体包封材料施加到管芯22的顶面和在底面处被蚀刻的铜合金。所得到的结构然后被单体化或切割,结果在图2f中示出。
图1所示的方法与图2(a-f)所示的方法之间的不同之处之一在于在图1的方法中使用了预先形成的引线框20。相比之下,在图2(a-f)所示的方法中,蚀刻铜合金块来形成引线框。然而,在两个方法中,线接合都将管芯22的接合焊盘电连接到引线框的柱子的顶面。结果,所得到的封装的结构在PoP(堆叠封装)结构中或者在封装的管芯以堆叠的方式电连接到另一封装的管芯的情况下不能被电连接在一起。
最后,具有通过溅射或电镀用作到半导体管芯的接合焊盘的电连接的图案化的导体的基于面板的管芯封装也是本领域中众所周知的。例如参见美国专利US 7,224,061、7,514,767和7,557,437。
发明内容
因此,在本发明中,一种封装集成电路管芯的方法包括将多个集成电路管芯放置在具有平面表面的第一衬底上,其中该多个管芯中的每一个具有顶表面和底表面。该顶表面具有用于电连接到管芯的多个接合焊盘。该多个管芯被布置成顶表面与第一衬底的平面表面相接触。导电粘合剂被施加到每个管芯的底表面。多个预先形成的引线框被放置在该多个管芯上,每个引线框具有中央凹进部分和多个导电引线。每个引线具有顶面和底面,中央凹进部分借助用于导电性的连接被连接到该多个引线。中央凹进部分具有顶部部分和底部部分,该底部部分与该多个引线的底面基本共平面。引线框的中央凹进部分被放置在该多个管芯的导电粘合剂背面上,其中凹进部分的顶部部分与该导电粘合剂接触,直到每个引线的顶面与第一衬底的平面表面接触为止。然后除去第一衬底。该多个引线框被放置成该多个管芯在具有平面表面的第二衬底上、每个引线的底面和凹进部分的底部部分在该第二衬底的平面表面上。导电层被沉积在该管芯的顶表面和引线的顶面上并且被图案化以形成该多个管芯之一的特定的接触焊盘和与该一个管芯相关联的特定的导电引线之间的电连接。每个引线框的连接从其相邻的引线框被切割并且所述引线从所述凹进部分被切割。引线的底面和中央凹进部分被暴露以形成封装端子。
还公开了通过前述方法制造的封装的管芯。
附图说明
图1是利用现有技术的方法封装的具有引线框的封装的管芯的截面图。
图2(a-f)是现有技术的另一方法的截面图。
图3是本发明的方法中的第一步骤的截面图。
图4是本发明的方法中的下一步骤的截面图。
图5是本发明的方法中的下一步骤的截面图。
图6是本发明的方法中的下一步骤的截面图。
图7是本发明的方法中的下一步骤的截面图。
图8是本发明的方法中的下一步骤的截面图。
图9是本发明的方法中的下一步骤的截面图。
图10是本发明的方法中的下一步骤的截面图。
图11是本发明的方法中的下一步骤的截面图。
图12是本发明的方法中的下一步骤的截面图。
图13是本发明的方法中的下一步骤的截面图。
图14是本发明的方法中的下一步骤的截面图。
图15是本发明的方法中的下一步骤的截面图。
图16是本发明的方法中的下一步骤的截面图。
图17是本发明的方法中的下一步骤的截面图。
图18是本发明的堆叠封装的管芯的一种方法的截面图。
图19是本发明的堆叠封装的管芯的另一方法的截面图。
图20是现有技术的预先形成的引线框的顶视图。
图21是用在本发明的方法中的本发明的预先形成的引线框的顶视图。
图22是使用本发明的方法利用本发明的预先形成的引线框封装的管芯的顶视图,其中电感器被并入到该封装中。
具体实施方式
参考图3,示出本发明的方法中的第一步骤的截面图。该方法开始于第一衬底60。第一衬底60可以是玻璃或任何具有坚硬特性的材料。第一衬底60具有顶表面62和与其相对的底表面64。顶表面62被多个标记66标记。标记66对应于集成电路管芯70的接触焊盘将被放置的位置。所得到的结构在图3中示出。
PET 68层被施加到第一衬底60的顶表面62。材料PET 68可以是双面粘性膜。由此,PET层68附着到第一衬底60。被印刷的胶层69,例如来自Dow Corning公司的Q2-7406,然后被施加到PET层68。胶层69粘附到PET层68。另外,其将允许管芯70(在下一步骤中讨论)粘附到PET层68。PET层68以及胶层69的使用确保了强粘合层将管芯70附着到PET层68以防止管芯70的表面和PET层68之间的任何空隙。同时,PET层68的使用,以及其低粘合特性,使得PET层68能够在后续处理中被容易地从第一衬底60除去。所得到的结构在图4中示出。
然后多个集成电路管芯70被放置在层69上。每个集成电路管芯70具有接合焊盘72,每个管芯70被放置成其接合焊盘72与标记66对准。这借助常规的众所周知的管芯放置工具来完成。每个管芯70具有前表面74和后表面76。接合焊盘72位于前表面74上。在管芯70被放置在位于第一衬底60上的层68上的层69上时,导电银膏剂78被施加到每个管芯70的后表面76。所得到的结构在图6中示出。
然后将预先形成的引线框80施加到图6中示出的结构。预先形成的引线框80(其将被更详细地讨论)具有中央凹进部分14和多个间隔开的引线12。每个间隔开的引线12具有底面82和顶面84。每个凹进腔14具有顶部部分和底部部分,凹进腔14的底部部分与引线12的底面82基本共平面。引线框80被如此施加使得均具有其导电银膏剂78的管芯70被放置在引线框80的凹进腔14中,接触凹进腔14的顶部部分。引线框80然后被向下“按压”,即引线框80被压在导电银膏剂78上直到引线12的顶面84压在层69上为止。所得到的结构在图7中示出。
绝缘体90被施加到图7所示的结构上。可以使用的绝缘体90的实例包括X-35, TC-27或EF-342X或其它环氧树脂和化合物。所有这些材料具有这样的特性,即它们通常具有高导热率特性且相对容易流动,使得它们能够以液体或膏剂形式被施加。绝缘体90可以通过任何手段(包括印刷或扩散)被施加在图7之后形成的结构上。绝缘体90被施加在各处使得它甚至进入管芯70和相邻的引线12之间的凹进部分14中。所得到的结构在图8中示出。
然后除去第一玻璃衬底60。由于PET层68仅轻轻粘附到第一玻璃衬底60,第一玻璃衬底60可以被简单地“剥离”。所得到的结构在图9中示出。
然后通过常规手段除去层68和69。最后,包含引线12的底面82的引线框80的表面被平面化以除去过多的绝缘体90。过多的绝缘体90通过平面化工艺,例如通过任何研磨工艺来除去,所述研磨工艺包括针对引线框80的表面使用砂纸(或任何其它研磨材料)直到引线12的底面82被暴露为止。所得到的结构在图10中示出。
然后将该结构安装或放置到第二衬底92(例如玻璃)上,其中包含引线12的底面82的引线框80的表面在衬底92上。该结构可以利用Dow Corning公司的Q2-7406被放置在第二衬底92上。第二衬底92仅提供用于后续处理的坚硬机械支撑。所得到的结构在图11中示出。
SINR层、光敏介电材料层,例如SINR, PI, PBO,或其它材料的层94被施加。层94类似于光致抗蚀剂,并且被施加在包含引线12的顶面84的表面以及接合焊盘72上。层94被图案化以暴露特定的接合焊盘72和特定的引线12的特定的顶面84之间的期望的连接。所得到的结构在图12中示出。
然后导电层96被沉积在光致抗蚀剂层94上。在光致抗蚀剂图案被暴露的情况下,导电层94形成特定的接合焊盘72和特定的引线12的特定的顶面84之间的电连接。在特定的接合焊盘72和特定的引线12的特定的顶面84之间形成电连接的过程中,导电层94可以被图案化以形成绝缘体200。这在图22中示出。由此,本发明的方法和封装的明显好处之一在于作为集成电路管芯70的封装的一部分,诸如绝缘体200(或电阻器)的无源电路元件可以被形成并且与管芯70一起被封装在其中可以集成电容器的同一封装中。所得到的结构在图13中示出。
然后第二绝缘体98被施加到图13中形成的结构,并且特别是覆盖导电层96。所得到的结构在图14中示出。第二绝缘体98可以是另一SiNR层,其是光敏介电材料。在沉积层98之后,可以在层98中形成开口以暴露部分导电层94。
在第二绝缘体98的那些开口中,然后UBM(凸块下金属化)100被沉积。UBM 100形成用于焊料球102的反应势垒层,所述焊料球102形成在后续步骤中以电连接到导电层94的暴露部分。焊料球102然后被放置在UBM 100的层上的第二绝缘体98的相同开口中。球102可以借助常规放置工具或印刷方法被布置。所得到的结构在图15中示出。
其后,除去第二玻璃衬底92。另外,PET粘合层也被除去。然后清洁底面82。所得到的结构在图16中示出。
然后图16的结构被浸入锡电镀溶液中。锡将仅粘附到暴露的铜引线框并且将不粘附到绝缘体90。特别地,锡将粘附到每个引线12的底面82,以及凹进腔14的底部部分。所得到的结构在图17中示出。
本发明的方法和封装集成电路管芯的结构存在许多优点。首先,利用本发明的方法和装置,具有诸如电阻器和电感器和电容器的集成无源元件的封装的集成电路管芯可以与管芯直接封装。另外,利用本发明的方法和装置,可以获得P-O-P(堆叠封装)装置。参考图18,示出使用本发明的装置的P-O-P实施例的第一实施例。第一封装的集成电路管芯150a具有第一表面152a,其具有可焊球154a,可焊球154a电连接到接合焊盘72a。与第一表面152a相对的第二表面160a具有与引线12a的底面82a的导电接触。第二封装的集成电路管芯150b具有第一表面152b,其具有可焊球154b,可焊球154b电连接到接合焊盘72b。与第一表面152b相对的第二表面160b具有与引线12b的底面82b的导电接触。第一和第二封装150a和150b被如此布置使得表面152a和152b彼此面对且可焊球154a和154b彼此接触。以这样的方式,两个封装150a和150b可以被彼此焊接并且仍提供通过引线82a和82b的底部的电接触。
参考图19,示出使用本发明的装置的P-O-P实施例的第二实施例。第一封装的集成电路管芯150a具有第一表面152a,其具有可焊球154a,可焊球154a电连接到接合焊盘72a。与第一表面152a相对的第二表面160a具有与引线12a的底面82a的导电接触。第二封装的集成电路管芯150b具有第一表面152b,其具有可焊球154b,可焊球154b电连接到接合焊盘72b。与第一表面152b相对的第二表面160b具有与引线12b的底面82b的导电接触。第一和第二封装150a和150b被如此布置使得表面152a和160b彼此面对且可焊球154a与封装150b的底面82b相接触。以这样的方式,两个封装150a和150b可以被彼此焊接并且仍提供通过引线82a的底部和通过可焊球154b的电接触。
参考图21,示出用在本发明的方法和装置中的本发明的引线框80的顶视图。引线框80当用在本发明的方法中时包括凹进部分14。凹进部分14借助连接元件120连接到引线框80的其余部分。引线框80还包括多个引线12 (a-f)和另一引线12g,其电连接到凹进部分14。尽管仅6个引线12被示出,但是应当理解本发明可以使用具有任何数目的引线12的引线框80。当引线框80被单体化,即沿线122被切割时,所有引线12 (a-f)彼此电隔离,除了引线12(g)电连接到凹进部分14以外。以这样的方式,到凹进部分14的电连接可以通过电连接到凹进部分14或者电连接到引线12(g)的顶面来制作。以这样的方式,到管芯20的底部的连接可以从封装的管芯的任一侧来制作。
从上述可以看出本发明的方法提供一种封装集成电路管芯的紧凑装置,并由此制作紧凑的集成电路管芯。
Claims (13)
1.一种封装的半导体管芯,包括:
预先形成的引线框,其具有中央凹进部分和多个导电引线,每个导电引线具有顶部部分和底部部分,其中所述多个引线被间隔开并且与中央凹进部分绝缘,所述中央凹进部分具有顶面和底面,其中底面与所述多个引线的底部部分基本共平面;
集成电路管芯,其具有顶表面和与其相对的底表面,其中所述顶表面具有多个接合焊盘,用于电连接到所述管芯,所述管芯被布置在所述中央凹进部分中,其中所述管芯的所述底表面与所述凹进部分的所述顶面电接触;
导电层,其被沉积在所述管芯的所述顶表面和所述引线的所述顶部部分上,并且被图案化以将所述管芯的特定的所述接合焊盘电连接到特定的所述导电引线;和
覆盖导电层的绝缘体。
2.根据权利要求1的封装的半导体管芯,其中所述预先形成的引线框还包括:
接地引线,其具有顶部部分和底部部分,其中所述顶部部分与所述多个引线的顶部部分基本共平面,并且所述接地引线的底部部分与所述多个引线的底部部分和所述凹进部分的底面基本共平面,其中所述接地引线电连接到所述凹进部分。
3.根据权利要求1的封装的半导体管芯,其中所述管芯的所述顶表面与所述多个引线的顶部部分基本共平面。
4.根据权利要求3的封装的半导体管芯,还包括附着到每个引线的底部部分的焊料材料的导电凸块。
5.根据权利要求4的封装的半导体管芯,还包括附着到每个引线的顶部部分的焊料材料的导电凸块。
6.根据权利要求1的封装的半导体管芯,还包括形成在所述导电层中的无源电路元件,其连接所述管芯的特定的所述接合焊盘和特定的所述导电引线。
7.一种封装集成电路管芯的方法,包括:
a)将多个集成电路管芯放置在具有平面表面的第一衬底上,所述多个管芯的每一个具有顶表面和底表面,其中所述顶表面具有多个接合焊盘,用于电连接到所述管芯;所述多个管芯被布置成所述顶表面与所述第一衬底的所述平面表面接触;
b)将导电粘合剂施加到所述管芯的每一个的底表面;
c)将多个相连的引线框放置在所述多个管芯上;每个引线框具有中央凹进部分和多个导电引线,每个引线具有顶面和底面,所述中央凹进部分借助连接连接到所述多个引线,所述中央凹进部分具有顶部部分和底部部分,所述底部部分与所述多个引线的底面基本共平面,所述引线框的所述中央凹进部分被放置在所述多个管芯的所述导电粘合剂上,所述凹进部分的所述顶部部分与所述导电粘合剂接触直到每个引线的与所述第一衬底的所述平面表面接触为止;
d)除去所述第一衬底;
e)将所述多个引线框与所述多个管芯放置在具有平面表面的第二衬底上,每个引线的所述底面和所述凹进部分的底部部分在所述第二衬底的所述平面表面上;
f)将导电层沉积在所述管芯的所述顶表面和所述引线的所述顶面上;
g)图案化所述导电层以将所述多个管芯之一的特定的所述接合焊盘电连接到与所述一个管芯相关联的特定的导电引线;以及
h)从相连的引线框切割每个引线框的所述连接的每一个且从所述凹进部分切割所述引线。
8.根据权利要求7的方法,还包括利用绝缘体填充在步骤c)之后形成的结构以填充每个管芯和其相邻的、所关联的引线框的引线之间的空间的步骤。
9.根据权利要求8的方法,还包括平面化在步骤d)之后形成的结构以除去每个引线的底面和所述凹进部分的底部部分上的任何绝缘体的步骤。
10.根据权利要求8的方法,还包括在所述管芯的所述顶表面和所述引线的所述顶面上以及在每个管芯和相邻的、相关联的引线框的引线之间的所述绝缘体上方沉积导电层的步骤。
11.根据权利要求10的方法,其中所述导电层被图案化以形成无源电路元件,其连接所述多个管芯之一的特定的所述接合焊盘和与所述一个管芯相关联的特定的导电引线。
12.根据权利要求10的方法,还包括将焊料材料的导电凸块附着到每个引线的底面。
13.根据权利要求12的方法,还包括将焊料材料的导电凸块附着到每个引线的顶面。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/638827 | 2009-12-15 | ||
US12/638,827 US8435837B2 (en) | 2009-12-15 | 2009-12-15 | Panel based lead frame packaging method and device |
US12/638,827 | 2009-12-15 | ||
PCT/US2010/057026 WO2011075263A1 (en) | 2009-12-15 | 2010-11-17 | Panel based lead frame packaging method and device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102652358A true CN102652358A (zh) | 2012-08-29 |
CN102652358B CN102652358B (zh) | 2016-03-16 |
Family
ID=44141988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201080057337.6A Active CN102652358B (zh) | 2009-12-15 | 2010-11-17 | 基于面板的引线框封装方法和装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8435837B2 (zh) |
EP (1) | EP2513968B1 (zh) |
JP (1) | JP5615936B2 (zh) |
KR (1) | KR101377176B1 (zh) |
CN (1) | CN102652358B (zh) |
TW (1) | TWI435428B (zh) |
WO (1) | WO2011075263A1 (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8435837B2 (en) * | 2009-12-15 | 2013-05-07 | Silicon Storage Technology, Inc. | Panel based lead frame packaging method and device |
US8716873B2 (en) | 2010-07-01 | 2014-05-06 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
KR101538543B1 (ko) * | 2013-08-13 | 2015-07-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR102384863B1 (ko) | 2015-09-09 | 2022-04-08 | 삼성전자주식회사 | 반도체 칩 패키지 및 이의 제조 방법 |
US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
US10186467B2 (en) * | 2016-07-15 | 2019-01-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
JP6851239B2 (ja) * | 2017-03-29 | 2021-03-31 | エイブリック株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US10818635B2 (en) * | 2018-04-23 | 2020-10-27 | Deca Technologies Inc. | Fully molded semiconductor package for power devices and method of making the same |
CN109065520A (zh) * | 2018-06-26 | 2018-12-21 | 深圳信炜生物识别科技有限公司 | 一种芯片封装结构、芯片功能模组及电子设备 |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
DE102019103281B4 (de) * | 2019-02-11 | 2023-03-16 | Infineon Technologies Ag | Verfahren zum bilden eines die-gehäuses |
US10991621B2 (en) * | 2019-08-05 | 2021-04-27 | Texas Instruments Incorporated | Semiconductor die singulation |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030104653A1 (en) * | 2000-06-28 | 2003-06-05 | Farnworth Warren M. | Recessed encapsulated microelectronic devices and methods for formation |
US20040104473A1 (en) * | 2002-06-25 | 2004-06-03 | Farnworth Warren M. | Semiconductor component having conductors with wire bondable metalization layers |
CN101103460A (zh) * | 2005-01-20 | 2008-01-09 | 英飞凌科技股份公司 | 引线框架、半导体封装及其制造方法 |
CN101202274A (zh) * | 2006-11-28 | 2008-06-18 | 硅存储技术公司 | 多芯片电子电路模块及制造方法 |
US20090026603A1 (en) * | 2007-07-23 | 2009-01-29 | Headway Technologies, Inc. | Electronic component package and method of manufacturing same |
CN101533825A (zh) * | 2008-03-14 | 2009-09-16 | 日月光半导体制造股份有限公司 | 半导体封装结构及其工艺与表面粘着型半导体封装结构 |
US20090243082A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with planar interconnect |
US20090283881A1 (en) * | 2008-05-14 | 2009-11-19 | Harvatek Corporation | Semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process and method for making the same |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4796078A (en) * | 1987-06-15 | 1989-01-03 | International Business Machines Corporation | Peripheral/area wire bonding technique |
US6441495B1 (en) | 1997-10-06 | 2002-08-27 | Rohm Co., Ltd. | Semiconductor device of stacked chips |
KR100246366B1 (ko) * | 1997-12-04 | 2000-03-15 | 김영환 | 에리어 어레이형 반도체 패키지 및 그 제조방법 |
JP2000077563A (ja) | 1998-08-31 | 2000-03-14 | Sharp Corp | 半導体装置およびその製造方法 |
US6084297A (en) | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
KR100890534B1 (ko) * | 2000-02-25 | 2009-03-27 | 이비덴 가부시키가이샤 | 다층프린트배선판 및 다층프린트배선판의 제조방법 |
JP3609684B2 (ja) * | 2000-03-28 | 2005-01-12 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
DE10213296B9 (de) * | 2002-03-25 | 2007-04-19 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Halbleiterchip, Verfahren zu seiner Herstellung und Verfahren zur Herstellung eines Nutzens |
US6841854B2 (en) * | 2002-04-01 | 2005-01-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US7790500B2 (en) | 2002-04-29 | 2010-09-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7459781B2 (en) | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
US7514767B2 (en) | 2003-12-03 | 2009-04-07 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
US7061106B2 (en) * | 2004-04-28 | 2006-06-13 | Advanced Chip Engineering Technology Inc. | Structure of image sensor module and a method for manufacturing of wafer level package |
JP2006019441A (ja) * | 2004-06-30 | 2006-01-19 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
JP4575071B2 (ja) * | 2004-08-02 | 2010-11-04 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
US7224061B2 (en) | 2004-08-16 | 2007-05-29 | Advanced Chip Engineering Technology Inc. | Package structure |
WO2006044804A2 (en) | 2004-10-18 | 2006-04-27 | Chippac, Inc. | Multi chip leadframe package |
JP2006165252A (ja) * | 2004-12-07 | 2006-06-22 | Shinko Electric Ind Co Ltd | チップ内蔵基板の製造方法 |
US7598600B2 (en) * | 2005-03-30 | 2009-10-06 | Stats Chippac Ltd. | Stackable power semiconductor package system |
TWI287275B (en) * | 2005-07-19 | 2007-09-21 | Siliconware Precision Industries Co Ltd | Semiconductor package without chip carrier and fabrication method thereof |
JP5164362B2 (ja) * | 2005-11-02 | 2013-03-21 | キヤノン株式会社 | 半導体内臓基板およびその製造方法 |
US7426117B2 (en) * | 2005-12-21 | 2008-09-16 | Xerox Corporation | Chip on a board |
US7838395B2 (en) * | 2007-12-06 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same |
US8084299B2 (en) * | 2008-02-01 | 2011-12-27 | Infineon Technologies Ag | Semiconductor device package and method of making a semiconductor device package |
US8415789B2 (en) * | 2008-05-09 | 2013-04-09 | Kyushu Institute Of Technology | Three-dimensionally integrated semicondutor device and method for manufacturing the same |
US8435837B2 (en) * | 2009-12-15 | 2013-05-07 | Silicon Storage Technology, Inc. | Panel based lead frame packaging method and device |
US8349658B2 (en) * | 2010-05-26 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe |
-
2009
- 2009-12-15 US US12/638,827 patent/US8435837B2/en active Active
-
2010
- 2010-11-17 KR KR1020127015900A patent/KR101377176B1/ko active IP Right Grant
- 2010-11-17 EP EP10838085.8A patent/EP2513968B1/en active Active
- 2010-11-17 CN CN201080057337.6A patent/CN102652358B/zh active Active
- 2010-11-17 JP JP2012544534A patent/JP5615936B2/ja active Active
- 2010-11-17 WO PCT/US2010/057026 patent/WO2011075263A1/en active Application Filing
- 2010-11-25 TW TW099140762A patent/TWI435428B/zh active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030104653A1 (en) * | 2000-06-28 | 2003-06-05 | Farnworth Warren M. | Recessed encapsulated microelectronic devices and methods for formation |
US20040104473A1 (en) * | 2002-06-25 | 2004-06-03 | Farnworth Warren M. | Semiconductor component having conductors with wire bondable metalization layers |
CN101103460A (zh) * | 2005-01-20 | 2008-01-09 | 英飞凌科技股份公司 | 引线框架、半导体封装及其制造方法 |
CN101202274A (zh) * | 2006-11-28 | 2008-06-18 | 硅存储技术公司 | 多芯片电子电路模块及制造方法 |
US20090026603A1 (en) * | 2007-07-23 | 2009-01-29 | Headway Technologies, Inc. | Electronic component package and method of manufacturing same |
CN101533825A (zh) * | 2008-03-14 | 2009-09-16 | 日月光半导体制造股份有限公司 | 半导体封装结构及其工艺与表面粘着型半导体封装结构 |
US20090243082A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with planar interconnect |
US20090283881A1 (en) * | 2008-05-14 | 2009-11-19 | Harvatek Corporation | Semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process and method for making the same |
Also Published As
Publication number | Publication date |
---|---|
EP2513968B1 (en) | 2016-03-16 |
TW201126678A (en) | 2011-08-01 |
JP5615936B2 (ja) | 2014-10-29 |
US8435837B2 (en) | 2013-05-07 |
KR101377176B1 (ko) | 2014-03-25 |
EP2513968A4 (en) | 2015-04-01 |
US20110140254A1 (en) | 2011-06-16 |
EP2513968A1 (en) | 2012-10-24 |
TWI435428B (zh) | 2014-04-21 |
KR20120095449A (ko) | 2012-08-28 |
CN102652358B (zh) | 2016-03-16 |
WO2011075263A1 (en) | 2011-06-23 |
JP2013513969A (ja) | 2013-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102652358B (zh) | 基于面板的引线框封装方法和装置 | |
CN103715166B (zh) | 用于部件封装件的装置和方法 | |
CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
CN104253105B (zh) | 半导体器件和形成低廓形3d扇出封装的方法 | |
CN103681607B (zh) | 半导体器件及其制作方法 | |
CN102194740B (zh) | 半导体器件及其形成方法 | |
CN103515260B (zh) | 封装内封装及其形成方法 | |
CN100479135C (zh) | 半导体器件及其制造方法 | |
CN102130101B (zh) | 围绕凸块形成区形成具有多层ubm的凸块结构的半导体器件和方法 | |
CN101996896A (zh) | 半导体器件及其制造方法 | |
CN102194717A (zh) | 半导体器件和在半导体管芯周围形成绝缘层的方法 | |
CN101996895A (zh) | 半导体器件及其制造方法 | |
CN102163561A (zh) | 半导体器件和使用相同载体在wlcsp中形成tmv和tsv的方法 | |
CN208460752U (zh) | 半导体器件 | |
CN103824836A (zh) | 半导体承载元件及半导体封装件 | |
CN105621345A (zh) | Mems芯片集成的封装结构及封装方法 | |
CN106373934A (zh) | 半导体封装结构及制造方法 | |
CN107195555A (zh) | 一种芯片封装方法 | |
CN106571347A (zh) | 绝缘管芯 | |
CN105845585A (zh) | 一种芯片封装方法及芯片封装结构 | |
CN203351587U (zh) | 半导体器件 | |
CN113299613A (zh) | 半导体封装结构及其制造方法 | |
CN103594388A (zh) | 具有侧壁间隔物的接触垫及其制作方法 | |
CN105428507A (zh) | 芯片封装结构及方法 | |
CN104576402A (zh) | 封装载板及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |