TWI435428B - 平板式引線框封裝方法及裝置 - Google Patents

平板式引線框封裝方法及裝置 Download PDF

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Publication number
TWI435428B
TWI435428B TW099140762A TW99140762A TWI435428B TW I435428 B TWI435428 B TW I435428B TW 099140762 A TW099140762 A TW 099140762A TW 99140762 A TW99140762 A TW 99140762A TW I435428 B TWI435428 B TW I435428B
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Taiwan
Prior art keywords
leads
wafer
lead
conductive
wafers
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TW099140762A
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English (en)
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TW201126678A (en
Inventor
Chen Lung Tsai
Long-Ching Wang
Tze-Pin Lin
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Silicon Storage Tech Inc
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Publication of TW201126678A publication Critical patent/TW201126678A/zh
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Publication of TWI435428B publication Critical patent/TWI435428B/zh

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    • HELECTRICITY
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

平板式引線框封裝方法及裝置 技術領域
本發明有關於一種用以使用一引線框將半導體晶片封裝在一平板上之方法。本發明亦有關於一種藉由這種方法製成之裝置且特別地其中該裝置可以疊合式封裝(package-on-package)堆疊。
發明背景
使用一引線框封裝半導體晶片在此項技術中是眾所周知的。請參閱第1圖,其中顯示使用一引線框之一經封裝半導體晶片的一橫截面圖。在第20圖中顯示先前技術之一引線框20的一平面圖,該經封裝晶片10包含具有中央凹部14及多數分開引線12之一引線框20。一積體電路晶片22具有一頂表面24及一底表面26,且該頂表面24具有與在該積體電路晶片24中之各種電路元件電氣連接的多數接合墊。該晶片22被定位在該凹部14中,使得該晶片22之底表面26透過一導電糊放置在該凹部14上且與該凹部14電氣連接。該凹部14係由一導電材料形成。多數接合線30連接在該晶片22之頂表面上之某些接合墊與某些引線12之頂側,各引線12具有與該頂側相對之一底側32,底側32將與在一印刷電路板(PCB)上之各種電氣墊連接以供系統應用。該凹部14亦連接在與該等引線12之底側32相同側上之印刷電路板上的一電氣接頭,通常是接地。
在先前技術之方法中,該晶片22先被放置在一預成形引線框20之凹部14上。該晶片22可被黏著劑附接於該凹部14以便在隨後的步驟中防止該晶片22移動,一線接合機接合該晶片22之某些接合墊與某些引線12之頂側。一旦所有線已被如此接合,樹脂被注入一模箱中以便封閉且絕緣該晶片22、該等線30及該等引線12之頂側。該結構接著被單粒化或切割且各經封裝晶片可接著藉眾所周知之技術,例如藉將該經封裝晶片10焊接在一印刷電路板PCB上被用來連接另一經封裝半導體裝置。在這情況中,該等引線12之底側32及該凹部14之底表面可以焊接至該PCB上。如此,該先前技術之經封裝半導體晶片,如第1圖所示,具有僅通至經封裝晶片之一側用以連接一印刷電路板之多數電氣連接。
請參閱第2a圖,其中顯示在形成另一先前技術之一經封裝半導體晶片40之另一方法中的第一步驟,該另一方法非常類似於第1圖所示及所述之方法。在這方法中,該方法由具有一頂側及一底側之一片銅合金42開始。光阻劑44被施加至該頂側及該底側兩者上,且在兩側上形成一掩蔽步驟。在該光阻劑44之未掩蔽部份被移除後,濺鍍如錫之一可焊接材料46以便填補該等被移除之部份,所得到之結構顯示於第2b圖中。
接著移除該光阻劑44,將該可焊接材料46留在該銅合金42上,所得到之結構顯示在第2c圖中。利用該可焊接材料46作為一遮罩,在該銅合金42之頂側上進行該銅之一濕式蝕刻。該蝕刻形成一凹中央部50,所得到之結構顯示在第2d圖中。
將一晶片22放在該凹孔50中,且該晶片22之接合墊面向外。接著將多數線與該晶片22之接合墊接合且與在該頂側上之可焊接柱46接合,然後將一絕緣體封閉材料施加至該晶片22之頂側及在該底側之經蝕刻銅合金。所得到之結構接著被單粒化或切割且結果顯示於第2f圖中。
在第1圖所示之方法與在第2(a-f)圖所示之方法之間的其中一差異是在第1圖之方法中,使用一預成形之引線框20。相反地,在第2(a-f)圖所示之方法中,一片銅合金被蝕刻以便形成一引線框。但是,在兩種方法中,線接合電氣連接該晶片22之接合墊與該引線框之柱之頂側。因此,所得到之經封裝結構不能以一POP(疊合式封裝)構形電氣連接在一起,或其中在經封裝晶片上與另一經封裝晶片以一堆疊方式電氣連接。
最後,平板式封裝具有藉由濺鍍或電鍍圖案化之導體作為通至半導體晶片之接合墊之多數電氣連接的晶片亦在此項技術中是眾所周知的。請參見例如USP 7,224,061;7,514,767;及7,557,437。
發明概要
因此,在本發明中,一種封裝一積體電路晶片之方法包含將多數積體電路晶片放在具有一平坦表面之一第一基體上,且該等多數晶片之各晶片具有一頂表面及一底表面。該頂表面具有用以與該晶片電氣連接之多數接合墊,該等多數晶片被定位成使該頂表面與該第一基體之平坦表面接觸。將一導電黏著劑施加至各晶片之底表面,將多數預成形引線框放在該等多數晶片上且各引線框具有一中央凹部,及多數導電引線。各引線具有一頂側及一底側,且該中央凹部藉由一連接構件與該等多數引線連接以便進行電傳導。該中央凹部具有一頂部及一底部,且該底部與該等多數引線之底側實質共平面。該引線框之中央凹部被放在該等多數晶片之導電黏著劑背側上且該凹部之頂部與該導電黏著劑接觸,直到各引線之頂側與該第一基體之平坦表面接觸為止。該第一基體接著被移除,具有該等多數晶片之該等多數引線框被放在具有一平坦表面之一第二基體上,且各引線之底側及該凹部之底部在該第二基體之平坦表面上。一導電層被沈積在該晶片之頂表面及該等引線之頂側上且被圖案化以便在該等多數晶片之其中一晶片之某些接合墊及與該其中一晶片相關之某些導電引線之間電氣連接。各引線框與其相鄰引線框之連接被切斷且該等引線與該凹部之連接被切斷。該等引線之底側及中央凹部被暴露出來以便形成多數封裝端子。
在此亦揭露藉由前述方法製造之一經封裝晶片。
圖式簡單說明
第1圖是具有以先前技術之方法封裝之一引線框之一經封裝晶片的橫截面圖。
第2(a-f)圖是先前技術之另一方法之橫截面圖。
第3圖是在本發明之方法中之第一步驟的橫截面圖。
第4圖是在本發明之方法中之下一步驟的橫截面圖。
第5圖是在本發明之方法中之下一步驟的橫截面圖。
第6圖是在本發明之方法中之下一步驟的橫截面圖。
第7圖是在本發明之方法中之下一步驟的橫截面圖。
第8圖是在本發明之方法中之下一步驟的橫截面圖。
第9圖是在本發明之方法中之下一步驟的橫截面圖。
第10圖是在本發明之方法中之下一步驟的橫截面圖。
第11圖是在本發明之方法中之下一步驟的橫截面圖。
第12圖是在本發明之方法中之下一步驟的橫截面圖。
第13圖是在本發明之方法中之下一步驟的橫截面圖。
第14圖是在本發明之方法中之下一步驟的橫截面圖。
第15圖是在本發明之方法中之下一步驟的橫截面圖。
第16圖是在本發明之方法中之下一步驟的橫截面圖。
第17圖是在本發明之方法中之下一步驟的橫截面圖。
第18圖是堆疊本發明之經封裝晶片之一方法之橫截面圖。
第19圖是堆疊本發明之經封裝晶片之另一方法之橫截面圖。
第20圖是先前技術之一預成形引線框之俯視圖。
第21圖是用以使用在本發明之方法中之本發明之一預成形引線框之俯視圖。
第22圖是使用本發明之方法與本發明之一預成形引線框封裝在一起之一晶片的俯視圖,其中一電感器加入該封裝體中。
發明之詳細說明
請參閱第3圖,其中顯示在本發明之方法中之一第一步驟的橫截面圖。該方法由一第一基體60開始,該第一基體60可以是玻璃或具有剛性特性之任何材料。該第一基體60具有一頂表面62及與其相對之一底表面64,該頂表面62標記有多數記號66,該等記號66對應於一積體電路晶片70之接合墊72將被放置之多數位置。所得到之結構顯示在第3圖中。
一PET層68被施加至該第一基體60之頂表面62,該材料PET68可以是一雙面黏著膜。因此,該PET層68附接於該第一基體60。例如來自Dow Corning公司之Q2-7406的一印刷黏膠層69接著被施加至該PET層68,該黏膠層69黏著於該PET層68。此外,它將容許該晶片70(在下一步驟中說明)黏著於該PET層68。使用該PET層68及該黏膠層69是欲確使一強黏著層附接於該晶片70以附接於該PET層68,以便防止在該晶片70之表面與該PET層68之間的任何空隙。同時,利用該PET層68之低黏著性質使得該PET層68可以在隨後的步驟中輕易地由該第一基體60移除。所得到之結構顯示在第4圖中。
多數積體電路晶片70接著被放在該層69上。各積體電路晶片70具有多數接合墊72,且各晶片70被放置成使其接合墊72與該等記號66對齊,這是藉由習知之眾所周知晶片放置工具達成。各晶片70具有一前面74及一背面76,該等接合墊72位在該前面74上。在該等晶片70被放在位於在該第一基體60上之該層68的該層69上後,一導電銀糊78被施加至各晶片70之背面76。所得到之結構顯示在第6圖中。
一預成形引線框80接著被施加至第6圖所示之結構,將更詳細說明之該預成形引線框80具有一中央凹部14及多數分開引線12。各分開引線12具有一頂部及一底部,且該凹部14之底部與該等引線12之底側82實質共平面。該引線框80被施加成使得各具有其導電銀糊78之晶片70被放在該引線框80之凹部14中,接觸該凹部14之頂部。該引線框80接著被向下“壓”,即,該引線框80被壓抵於該導電銀糊78直到該等引線12之頂側84壓抵該層69為止。所得到之結構顯示在第7圖中。
一絕緣體90被施加在第7圖所示之結構上。可以被使用之絕緣體90之例子包括X-35,TC-27或EF-342X或其他環氧樹脂或化合物。所有這些材料具有它們通常具有一高導熱性性質之性質且相當容易流動,使得它們可以一液體或糊形式被施加。該絕緣體90可以藉由包括印刷或塗布在第7圖後形成之結構上的任何裝置施加,該絕緣體90到處被施加使得它均勻地進入該凹部14,在該晶片70與相鄰引線12之間。所得到之結構顯示在第8圖中。
該第一基體60接著被移除。由於該PET層68僅稍微黏著於該第一玻璃基體60,所以該第一玻璃基體60可簡單地被“剝離”。所得到之結構顯示在第9圖中。
該等層68與69接著被習知裝置被移除。最後,包含該等引線12之底側82之該引線框80的表面被平面化以便移除多餘絕緣體90。該多餘絕緣體90係藉由一平面化程序,例如藉由包括使用砂紙(或任何其他研磨材料)抵靠該引線框80之表面直到該等引線12之底側82暴露為止的任何研磨程序,被移除。所得到之結構顯示在第10圖中。
該結構接著被安裝或放置在如玻璃之一第二基體92上,且包含該等引線12之底側82之該引線框80的表面在該基體92上。該結構可利用如來自Dow Corning公司之Q2-7406的一黏著劑層被放置在該第二基體92上,該第二基體92僅為隨後之加工提供剛性機械支持。所得到之結構顯示在第11圖中。
施加一SINR,如SINR、PI、PBO等光敏介電材料層94。該層94類似於一光阻劑,且被施加在包含該等引線12之底側82的表面,及該等接合墊72上。該層94被圖案化以便暴露在某些接合墊72與某些引線12之頂側84之間的所需連接。所得到之結構顯示在第12圖中。
一導電層96接著被沈積在該光阻劑層94上。在該光阻劑圖案暴露處,該導電層94在某些接合墊72與某些引線12之頂側84之間形成一電氣連接。在某些接合墊72與某些引線12之頂側84之間形成一電氣連接之程序中,該導電層94可以被圖案化以便形成一電感器200,這顯示在第22圖中。因此,本發明之方法及封裝體之其中一明顯好處是作為該積體電路晶片70之封裝之一部份,如一電感器200(或電阻器)之一被動電路元件可形成且與該晶片70一起被封裝在其中可整合多數電容器之相同封裝體中。所得到之結構顯示在第13圖中。
一第二絕緣體98接著被施加於形成在第13圖中之結構,且特別地覆蓋該導電層96,所得到之結構顯示在第14圖中。該第二絕緣體98可以是為一光敏介電材料之SiNR之另一層,在該層98被沈積後,多數開口可形成在該第二絕緣體98中以便暴露該導電層94之多數部份。
在該第二絕緣體98之這些開口中,接著沈積UBM(凸塊底層金屬)100。該UBM100形成用於在隨後步驟中形成以便與該導電層94之暴露部份電氣連接之焊料球102的一反應障壁層,焊料球102接著被放置在位於該UBM100之層上之第二絕緣體98的相同開口中,該等球102可藉由一習知放置工具或印刷方法被定位。所得到之結構顯示在第15圖中。
然後,該第二玻璃基體92被移除。此外,該PET黏著劑層亦被移除,該底側82接著被清潔。所得到之結構顯示在第16圖中。
第16圖之結構接著被浸在一鍍錫溶液中。該錫將僅黏著於該暴露引線框且將不會黏著於該絕緣體90,詳而言之,錫將黏著於各引線12之底側82,且黏著於該凹部14之底部。所得到之結構顯示在第17圖中。
本發明之經封裝積體電路晶片之方法及結構有許多優點。首先,利用本發明之方法及裝置,具有如電阻器及電感器及電容器之整合被動元件的一經封裝積體電路晶片可以與該晶片直接封裝在一起。此外,利用本發明之方法及裝置,可實現一P-O-P(疊合式封裝)裝置。請參閱第18圖,其中顯示使用本發明之裝置之一P-O-P實施例之一第一實施例。一第一經封裝積體電路晶片150a具有一第一表面152a,該第一表面152a具有多數可焊接球154a,且該等可焊接球154a與該等接合墊72a電氣連接。與該第一表面152a相對之第二表面160a具有通至該等引線12a之底側82a之多數導電接頭。一第二經封裝積體電路晶片150b具有一第一表面152b,該第一表面152b具有多數可焊接球154b,且該等可焊接球154b與該等接合墊72b電氣連接。與該第一表面152b相對之第二表面160b具有通至該等引線12b之底側82b之多數導電接頭。該等第一與第二封裝體150a與150b被定位成使得該等表面152a與152b互相面對,且該等可焊接球154a與154b互相接觸。依這方式,兩封裝體150a與150b可以被互相焊接在一起且仍透過該等引線之底側82a與82b提供電氣接觸。
請參閱第19圖,其中顯示使用本發明之裝置之一P-O-P實施例之一第二實施例。一第一經封裝積體電路晶片150a具有一第一表面152a,該第一表面152a具有多數可焊接球154a,且該等可焊接球154a與該等接合墊72a電氣連接。與該第一表面152a相對之第二表面160a具有通至該等引線12a之底側82a之多數導電接頭。一第二經封裝積體電路晶片150b具有一第一表面152b,該第一表面152b具有多數可焊接球154b,且該等可焊接球154b與該等接合墊72b電氣連接。與該第一表面152b相對之第二表面160b具有通至該等引線12b之底側82b之多數導電接頭。該等第一與第二封裝體150a與150b被定位成使得該等表面152a與160b互相面對,且該等可焊接球154a與該封裝體150b之底側82b接觸。依這方式,兩封裝體150a與150b可以被互相焊接在一起且仍透過該等引線之底側82a及該等可焊接球154b提供電氣接觸。
請參閱第21圖,其中顯示用以使用在本發明之方法及裝置中之本發明之一引線框80的俯視圖。該引線框80在使用於本發明之方法中時包含一凹部14,該凹部14藉一連接構件120與該引線框80之其餘部份連接。該引線框80亦包含多數引線12(a-f)及與該凹部14連接之另一引線12(g)。雖然僅顯示6個引線12,但是可了解的是本發明可以使用具有任何數目之引線12的一引線框80。該引線框80被單粒化,即,沿著該線122切割時,所有引線12(a-f)互相電絕緣,但是該引線12(g)與該凹部14電氣連接。依這方式,與該凹部14之電氣連接可以藉與該凹部14或與該引線12(g)之頂側電氣連接來達成。依這方式,與該晶片20之底部連接可以由該經封裝晶片之任一側達成。
由前述可看出本發明之方法提供用以封裝積體電路晶片之一緊緻裝置,且一緊緻積體電路晶片因此製成。
10...經封裝晶片
12,12a-g...引線
14...凹部
20...引線框
22...晶片
24...頂表面
26...底表面
30...接合線
32...底側
40...經封裝半導體晶片
42...銅合金
44...光阻劑
46...可焊接材料;可焊接柱
50...凹中央部;凹孔
60...第一基體
62...頂表面
64...底表面
66...記號
68...PET層
69...黏膠層
70...晶片
72,72a,72b...接合墊
74...前面
76...背面
78...導電銀糊
80...引線框
82,82a,82b...底側
84...頂側
90...絕緣體
92...第二基體
94...層
96...導電層
98...第二絕緣體
100...UBM(凸塊底層金屬)
102...焊料球
120...連接構件
122...線
150a...第一經封裝積體電路晶片
150b...第二經封裝積體電路晶片
152a,152b...第一表面
154a,154b...可焊接球
160a,160b...第二表面
200...電感器
第1圖是具有以先前技術之方法封裝之一引線框之一經封裝晶片的橫截面圖。
第2(a-f)圖是先前技術之另一方法之橫截面圖。
第3圖是在本發明之方法中之第一步驟的橫截面圖。
第4圖是在本發明之方法中之下一步驟的橫截面圖。
第5圖是在本發明之方法中之下一步驟的橫截面圖。
第6圖是在本發明之方法中之下一步驟的橫截面圖。
第7圖是在本發明之方法中之下一步驟的橫截面圖。
第8圖是在本發明之方法中之下一步驟的橫截面圖。
第9圖是在本發明之方法中之下一步驟的橫截面圖。
第10圖是在本發明之方法中之下一步驟的橫截面圖。
第11圖是在本發明之方法中之下一步驟的橫截面圖。
第12圖是在本發明之方法中之下一步驟的橫截面圖。
第13圖是在本發明之方法中之下一步驟的橫截面圖。
第14圖是在本發明之方法中之下一步驟的橫截面圖。
第15圖是在本發明之方法中之下一步驟的橫截面圖。
第16圖是在本發明之方法中之下一步驟的橫截面圖。
第17圖是在本發明之方法中之下一步驟的橫截面圖。
第18圖是堆疊本發明之經封裝晶片之一方法之橫截面圖。
第19圖是堆疊本發明之經封裝晶片之另一方法之橫截面圖。
第20圖是先前技術之一預成形引線框之俯視圖。
第21圖是用以使用在本發明之方法中之本發明之一預成形引線框之俯視圖。
第22圖是使用本發明之方法與本發明之一預成形引線框封裝在一起之一晶片的俯視圖,其中一電感器加入該封裝體中。

Claims (13)

  1. 一種封裝之半導體晶片(die),包含:一預成形引線框,其具有一中央凹部,及各具有一頂部及一底部之多數導電引線,而該等多數引線與該中央凹部分開且絕緣,該中央凹部具有一頂側及一底側,且該底側與該等多數引線之底部實質共平面;一積體電路晶片,其具有一頂表面及與其相對之一底表面,而該頂表面具有用以與該晶片電氣連接之多數接合墊,該晶片被定位在該中央凹部中而該晶片之底表面與該凹部之頂側電氣接觸;一導電層,其被積設在該晶片之頂表面及該等引線之頂部上且被圖案化以將該等晶片之某些接合墊電氣連接至某些導電引線;以及一絕緣體,其覆蓋該導電層。
  2. 如申請專利範圍第1項之封裝之半導體晶片,其中該預成形引線框更包含:一接地引線,其具有一頂部及一底部,且該頂部與該等多數引線之頂部實質共平面,並且該接地引線之底部與該等多數引線之底部且與該凹部之底側實質共平面;其中該接地引線與該凹部電氣連接。
  3. 如申請專利範圍第1項之封裝之半導體晶片,其中該晶片之頂表面與該等多數引線之頂部實質共平面。
  4. 如申請專利範圍第3項之封裝之半導體晶片,更包含與各引線之底部附接的一焊接材料之一導電凸塊。
  5. 如申請專利範圍第4項之封裝之半導體晶片,更包含與各引線之頂部附接的一焊接材料之一導電凸塊。
  6. 如申請專利範圍第1項之封裝之半導體晶片,更包含形成在該導電層中將該晶片之某些接合墊連接至某些導電引線的被動電氣電路元件。
  7. 一種封裝積體電路晶片(die)之方法,包含:a)將多數積體電路晶片放在具有一平坦表面之一第一基體上,該等多數晶片之各晶片具有一頂表面及一底表面,而該頂表面具有用以與該晶片電氣連接之多數接合墊,該等多數晶片被定位成使該頂表面與該第一基體之平坦表面接觸;b)將一導電黏著劑施用至各晶片之底表面;c)將多數經連接之引線框放在該等多數晶片上,各引線框具有一中央凹部,及多數導電引線,而各引線具有一頂側及一底側,該中央凹部藉由一連接構件與該等多數引線連接,而該中央凹部具有一頂部及一底部而該底部與該等多數引線之底側實質共平面,該引線框之中央凹部被放在該等多數晶片之導電黏著劑上而該凹部之頂部與該導電黏著劑接觸,直到各引線之頂側與該第一基體之平坦表面接觸為止;d)移除該第一基體;e)將具有該等多數晶片之該等多數引線框放在具有一平坦表面之一第二基體上,而各引線之底側及該凹部之底部在該第二基體之平坦表面上; f)將一導電層積設在該晶片之頂表面及該等引線之頂側上;g)將該導電層圖案化以將該等多數晶片之其中一晶片之某些接合墊電氣連接至與該其中一晶片相關之某些導電引線;以及h)切斷各引線框與相鄰引線框及該等引線與該凹部之連接。
  8. 如申請專利範圍第7項之方法,更包含以一絕緣體填充在步驟c)後形成之結構以填充在各晶片與相關引線框之其相鄰引線之間之空間的步驟。
  9. 如申請專利範圍第8項之方法,更包含將在步驟(d)後形成之結構加以平面化以移除在各引線之底側及該凹部之底部上之任何絕緣體的步驟。
  10. 如申請專利範圍第8項之方法,其中該積設步驟係在該晶片之頂表面及該等引線之頂側上且在各晶片與該相關引線框之相鄰引線之間之該絕緣體上方積設一導電層。
  11. 如申請專利範圍第10項之方法,其中該導電層被圖案化以形成將該等多數晶片之其中一晶片之某些接合墊連接至與該其中一晶片相關之某些導電引線的多數被動電路元件。
  12. 如申請專利範圍第10項之方法,更包含:將一焊接材料之一導電凸塊與各引線之底側附接。
  13. 如申請專利範圍第12項之方法,更包含: 將一焊接材料之一導電凸塊與各引線之頂側附接。
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EP2513968B1 (en) 2016-03-16
TW201126678A (en) 2011-08-01
JP5615936B2 (ja) 2014-10-29
US8435837B2 (en) 2013-05-07
CN102652358A (zh) 2012-08-29
KR101377176B1 (ko) 2014-03-25
EP2513968A4 (en) 2015-04-01
US20110140254A1 (en) 2011-06-16
EP2513968A1 (en) 2012-10-24
KR20120095449A (ko) 2012-08-28
CN102652358B (zh) 2016-03-16
WO2011075263A1 (en) 2011-06-23
JP2013513969A (ja) 2013-04-22

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