KR20140043651A - 콤포넌트 패키지용 장치 및 방법 - Google Patents

콤포넌트 패키지용 장치 및 방법 Download PDF

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KR20140043651A
KR20140043651A KR1020130000680A KR20130000680A KR20140043651A KR 20140043651 A KR20140043651 A KR 20140043651A KR 1020130000680 A KR1020130000680 A KR 1020130000680A KR 20130000680 A KR20130000680 A KR 20130000680A KR 20140043651 A KR20140043651 A KR 20140043651A
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rdl
semiconductor device
conductive
package
die
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KR1020130000680A
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KR101522763B1 (ko
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치-화 첸
첸-쉬엔 첸
칭-웬 샤오
밍 훙 쳉
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/351—Thermal stress

Abstract

콤포넌트 패키지 및 그 형성 방법이 제공된다. 제1 콤포넌트 패키지는 제1 반도체 기판의 대향 면 상에서 제1 반도체 소자에 부착되는 인터포저 쌍을 갖는 제1 반도체 소자를 포함할 수 있다. 각각의 인터포저는 그 내에 형성된 도전 트레이스를 포함하여 각 인터포저의 표면 상에 형성된 도전 특징부로의 전기적 결합을 제공한다. 복수의 스루 비어는 인터포저를 서로 전기적으로 접속할 수 있다. 제1 인터포저는 인쇄 회로 기판 또는 후속의 반도체 소자로의 전기적 접속을 제공할 수 있다. 제2 인터포저는 제2 반도체 소자 및 제2 콤포넌트 패키지로의 전기적 접속을 제공할 수 있다. 제1 및 제2 콤포넌트 패키지는 결합되어 패키지 온 패키지(PoP) 구조물을 형성할 수 있다.

Description

콤포넌트 패키지용 장치 및 방법{APPARATUS AND METHOD FOR A COMPONENT PACKAGE}
본 발명은 콤포넌트 패키지용 장치 및 방법에 관한 것이다.
집적 회로(IC)의 사이즈, 형성, 밀도 및 패키징의 개선은 반도체 산업을 급격하게 성장시켜 왔다. 집적 밀도의 개선은 IC 최소 배선폭(feature size)을 감소시켜 더 많은 콤포넌트를 주어진 공간에 통합시킬 수 있다.
회로 밀도를 증가시키는 하나의 개선법은 2개의 IC 다이를 서로의 상부에 스택하여 3차원(3D) IC라 불리우는 것을 형성하는 것이다. 일반적인 3D IC 형성 프로세스에서, 2개의 다이는 서로 본딩되고 전기적 접속부가 각 다이 및 기판 상의 접촉 패드 사이에 형성된다. 예를 들어, 2개의 다이는 서로의 상부에 본딩되고 하부의 다이는 기판에 결합된다. 기판 내의 스루 비아(through via; TV)는 다이를 기판의 대향 면 상의 도전 패드에 접속한다. 그 후, 접속 패드는 전기적 접속부를 이용하여 인쇄 회로 기판(PCB) 등에 전기적으로 결합될 수 있다.
회로 밀도를 증가시키는 또 다른 3D 패키지는 "패키지 온 패키지(PoP) 구조라 하고, 여기서, 각각의 기판에 결합된 다수의 다이가 서로의 상부에 "스택"되어 함께 결합된다. PoP 구조물을 형성하기 위하여, 제1 다이는 제1 기판에 전기적으로 결합되어 제1 회로를 형성한다. 제1 회로는 제2 회로에 접속하기 위한 제1 접속 포인트를 포함한다. 제2 회로는 기판의 각 측면 상의 접속 포인트를 갖는 제2 다이 및 기판을 포함한다. 제1 회로는 제2 회로 상에 스택되고 전기적으로 결합되어 PoP 구조물을 형성한다. PoP 구조물은 전기적 접속부를 이용하여 PCB 등에 전기적으로 결합될 수 있다.
메모리 회로는 다양한 다른 회로 콤포넌트와 함께 3D IC 내에 스택되어 메모리 모듈을 형성한다. 이러한 메모리 모듈은 종종 로직 회로, 하나 이상의 프로세서 또는 사용자 정의 ASIC(application specific integrated circuit)으로서 개발된 하나 이상의 애플리케이션 프로세서 유닛(APU)을 포함할 수 있다. 3D IC 내에 배치된 메모리 모듈은 APU를 기판의 대향면 상의 솔더 패드에 접속하는 TV로 기판에 결합된 APU를 포함한다. TV는 3D IC의 전체 높이 뿐만 아니라 3D IC의 설계 및 제조 복잡성을 증가시킨다. 또한 TV는 메모리 회로에 대한 스루풋을 저감시킨다.
본 발명의 목적은 3D IC의 전체 높이를 감소시킬 수 있고 3D IC의 설계 및 제조 복잡성을 감소시킬 수 있는 콤포넌트 패키지용 장치 및 방법을 제공하는 것이다.
일 실시예에서, 장치가 제공된다. 장치는 제1 반도체 소자, 제2 반도체 소자, 상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 RDL, 상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고 상기 제2 반도체 소자에 전기적으로 결합된 제2 RDL, 상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질, 및 상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합시키는 복수의 스루 비아(through via)를 포함한다.
또 다른 실시예에서, 또 다른 장치가 제공된다. 장치는 제1 패키지 콤포넌트, 및 제2 패키지 콤포넌트를 포함한다. 제1 패키지 콤포넌트는 제1 및 제2 측면을 갖는 제1 반도체 소자, 상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 RDL, 상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고, 제2 반도체 소자에 전기적으로 결합되고, 그 위에 형성된 복수의 제1 도전 특징부를 갖는 제2 RDL, 상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질, 및 상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합하는 복수의 스루 비아를 포함한다. 제2 패키지 콤포넌트는 제3 반도체 소자, 및 상기 제3 반도체 소자에 전기적으로 결합되고, 그 위에 형성된 복수의 제2 도전 특징부를 갖는 인터포저를 포함하고, 상기 제2 도전 특징부는 상기 제2 RDL의 제1 도전 특징부에 전기적으로 결합된다.
또 다른 실시예에서, 방법이 제공된다. 방법은 제1 캐리어 상에 제1 금속층을 형성하는 단계, 상기 제1 금속층 상에 복수의 도전 필러를 형성하는 단계, 제1 반도체 소자의 제1 측면을 상기 제1 금속층에 부착하는 단계, 상기 제1 반도체 소자 및 상기 복수의 도전 필러를 캡슐화하는 단계, 상기 제1 반도체 소자의 제2 측면 상에 제1 재분배층(RDL)을 형성하는 단계 - 상기 제1 RDL은 상기 도전 필러 및 상기 제1 반도체 소자에 전기적으로 결합됨 -, 제2 캐리어를 상기 제1 RDL에 부착하는 단계, 상기 제1 캐리어 및 상기 제1 금속층을 제거하는 단계, 및 상기 제1 반도체 소자의 제1 측면 상에 제2 RDL을 형성하여 제1 패키지 콤포넌트를 형성하는 단계 - 상기 제2 RDL은 상기 복수의 도전 필러에 전기적으로 결합됨 - 를 포함한다.
본 발명에 따르면, 3D IC의 전체 높이를 감소시킬 수 있고 3D IC의 설계 및 제조 복잡성을 감소시킬 수 있다. 또한, PoP 구조물에 대한 제조 수율을 증가시킬 수 있다.
본 실시예 및 그 이점의 더 완벽한 이해를 위하여 첨부된 도면을 참조하여 다음의 설명을 참조한다.
도 1은 실시예를 설명하는데 이용되는 구조물의 단면도.
도 2 내지 16은 실시예를 형성하는 다양한 중간 단계를 나타내는 도면.
본 실시예를 만들고 이용하는 것을 이하에서 설명한다. 그러나, 본 개시물은 다양한 특정 컨텍스트에서 구현될 수 있는 많은 적용가능한 진보적 개념을 제공한다는 것을 인정해야 한다. 기재된 특정한 실시예는 단지 개시물을 만들고 사용하는 특정한 방법을 설명하기 위한 것이며 상이한 실시예의 범위를 제한하지 않는다.
도 1을 먼저 참조하면, 실시예의 애플리케이션을 나타내는데 사용되는 예시적인 PoP 구조물(100)이 도시된다. PoP 구조물(100)은 제1 콤포넌트 패키지(110) 및 제2 콤포넌트 패키지(160)를 포함할 수 있다. 제1 콤포넌트 패키지(110) 및 제2 콤포넌트 패키지(160)는 여기에서 더 상세히 설명하는 바와 같이 함께 전기적으로 결합되어 PoP 구조물(100)을 형성한다.
제1 콤포넌트 패키지(110)는 제1 다이(120)를 포함할 수 있다. 제1 다이(120)는 제1 측면 및 제2 측면을 가질 수 있다. 제1 측면은 또한 "전면"이라고 하고 제2 측면은 또한 "후면"이라고 한다. 제1 다이(120)의 전면은 이하에서 더 상세히 설명하는 바와 같이 제1 재분배층(RDL)(113)에 전기적으로 결합될 수 있다. 제2 RDL(116)은 제1 다이(120)의 후면 상에 형성될 수 있다. 제2 다이(140)는 이하에서 더 상세히 설명하는 바와 같이 제2 RDL(116)에 전기적으로 결합될 수 있다. 제1 및 제2 RDL(113, 116)은 제1 다이(120)를 둘러싸는 제1 캡슐화 물질(112) 내에 위치 지정될 수 있는 스루 어셈블리 비아 등의 제1 세트의 TV(111)를 이용하여 함께 전기적으로 결합될 수 있다.
제1 RDL(113)은 그 내에 형성된 제1 금속화 트레이스(114)를 갖는 하나 이상의 유전층을 포함할 수 있다. 제1 트레이스(114)는 구리, 알루미늄, 금 또는 다른 유사한 물질로 형성되어 제1 RDL(113)을 통해 도전 경로를 제공한다. 제1 RDL(113)은 하나 이상의 감법(subtractive) 에칭 프로세스, 단일 다마신(Damascene) 기술 및/또는 듀얼-다마신 기술을 이용하여 형성될 수 있다. 제1 RDL(113)은 그 위에 형성된 제1 세트의 도전 특징부(115)를 가질 수 있고, 도전 특징부는 또한 제1 트레이스(114)에 결합될 수 있다. 제1 세트의 도전 특징부(115)는 구리, 알루미늄, 금 또는 다른 유사한 물질로 형성될 수 있다. 제1 세트의 도전 특징부(115)는 그 위에 형성된 제1 세트의 도전 접속부(130)를 갖고, 이 도전 접속부는 PCB, 고밀도 배선, 기판, 실리콘 기판, 유기 기판, 세라믹 기판, 적층 기판, 또 다른 반도체 패키지로의 PoP 구조물(100)의 전기적 접속을 제공할 수 있다. 다양한 실시예에서, 제1 세트의 도전 접속부(130)는 납이 없는(lead free) 솔더, 공융(eutectic) 납, 도전 필러(conductive pillar), 그 조합 등을 포함할 수 있다.
제1 RDL(113) 뿐만 아니라 해당 제1 트레이스(114) 및 제1 세트의 도전 특징부(115)는 제1 다이(120)에 신호 리맵핑(signal remapping) 및 추가의 지지를 제공할 수 있다. 제1 RDL(113)은 또한 제1 다이(120) 및 PCB 또는 PoP 구조물(100)이 장착될 수 있는 다른 전자 장치 사이의 열적 스트레스 완화를 제공할 수 있다. 실시예에서, MUF(molding under fill)(미도시)는 제1 세트의 제1 도전 특징부(115) 사이에 도포되어 특징부 간의 영역을 환경 또는 외부 오염물로부터 보호한다. 실시예에서, 제1 패시베이션층(미도시)는 제1 다이(120) 및 제1 RDL(113) 사이에 형성될 수 있다. 제1 패시베이션층은 폴리이미드 층, PBO, BCB, 비감광성 폴리머일 수 있고, 다른 실시예에서, 나이트라이드, 카바이드 또는 다른 유전체로 형성될 수 있다.
도 1에 도시된 바와 같이, 제1 RDL(113)에는 TV가 없을 수 있고, 이는 제1 패키지(110)의 전체 높이를 감소시킬 수 있고 제1 콤포넌트 패키지(110)의 설계 및 제조 복잡성을 감소시킬 수 있다. 추가의 이점으로서, 제1 RDL(113) 내의 TV의 부재(absence)는 유사하게 위치하는 인터포저(interposer) 내에 TV를 포함하는 설계에 비하여 PoP 구조물에 대한 제조 수율을 증가시킬 수 있다.
제1 RDL(116)은 그 내에 형성되는 제1 금속화 트레이스(117)를 갖는 하나 이상의 유전층을 포함할 수 있다. 제2 트레이스(117)는 구리, 알루미늄, 금 또는 다른 유사 물질로 형성되어 제2 RDL(116)을 통해 도전 경로를 제공한다. 제2 RDL(116)은 하나 이상의 감법 에칭 프로세스, 단일 다마신 기술 및/또는 듀얼-다마신 기술을 이용하여 형성될 수 있다. 제2 RDL(116)은 그 위에 형성된 제2 세트의 도전 특징부(118) 및 제3 세트의 도전 특징부(119)를 가질 수 있고, 그 각각은 제2 트레이스(117)에 결합될 수 있다. 제2 다이(140)는 그 위에 형성된 제4 세트의 도전 특징부(141)를 가질 수 있다. 제2, 제3 및/또는 제4 세트의 도전 특징부(118, 119, 141)는 각각 구리, 알루미늄, 금 또는 다른 유사 물질로 형성될 수 있다. 제2 다이(140)는 제2 세트의 도전 접속부(150)를 통해 제2 RDL(116)에 결합될 수 있고, 제2 세트의 도전 접속부(150)는 제2 RDL(116) 상에 형성된 제2 세트의 도전 특징부(118) 및 제2 다이(140)의 제4 세트의 도전 특징부(141)에 결합될 수 있다. 일 실시예에서, 패시베이션층(미도시)은 제1 다이(120) 및 제2 RDL(116) 사이에 형성될 수 있다.
제2 다이(140)는 제4 세트의 도전 특징부(141), 제2 세트의 도전 접속부(150), 제2 세트의 도전 특징부(118), 제2 트레이스(117), 제1 세트의 TV, 제1 트레이스(114) 및 제1 다이(120)의 전면 상에 형성된 도전 특징부(미도시)에 의해 형성된 도전 채널을 통해 제1 다이(120)에 전기적으로 결합될 수 있다. 제2 트레이스(117), 제1 세트의 TV(111), 제1 트레이스(114), 제1 세트의 도전 특징부(115) 및 제1 세트의 도전 접속부(130)는 또한 제1 다이(140) 및 PoP 구조물(100)이 장착될 수 있는 인터포저 또는 PCB 사이에 전기적 접속을 제공할 수 있다.
일 실시예에서, 제1 다이(120)는 APU일 수 있다. 일 실시예에서, 제2 다이(140)는 메모리 IC, 예를 들어, 와이드 데이터 워드(와이드 I/O) DRAM 또는 DDR RAM 등의 동적 RAM일 수 있다. 다른 실시예에서, 제2 다이(140)는 SRAM 등의 정적 RAM 또는 EPROM 또는 FLASH 메모리 등의 비휘발성 장치일 수 있다.
설명하는 바와 같이, TV(111)은 제1 다이를 통해 라우팅될 필요가 없다. 제1 다이(120)가 APU이고 제2 다이가 메모리 IC일 수 있는 임의의 실시예에서, 제1 다이(120)를 통한 TV 라우팅을 제거하면, 이러한 다이를 통한 TV 라우팅을 포함하는 패키지보다 더 높은 I/O 대역폭 메모리 IC를 지원할 수 있다. 제1 다이(120)를 통한 TV 라우팅을 제거함으로써 실현될 수 있는 또 다른 이점은 제1 콤포넌트 패키지(110)의 비용이 드는 재설계없이 상이한 반도체 물질(즉, GaAs)로 이루어지거나 상이한 제조 프로세스(즉, 45nm, 65nm, 등)에 따라 형성된 제1 다이(120) 및 제2 다이(140)에 대한 상이한 다이 타입을 지원하도록 제1 콤포넌트 패키지(110)를 적응하도록 증가된 유연성이다. 이 증가된 유연성은 제조 및 테스트 비용(즉, TV 신호 완전성 특성)을 감소시킬 뿐만 아니라 제1 다이(120)를 통해 TV를 이용하는 기술과 비교하여 기술 재설계에 대한 마케팅 시간을 감소시킬 수 있다. 또한, 제1 다이(120)를 통한 TV 라우팅을 제거하면 제1 콤포넌트 패키지(110)에 대한 제조 수율을 증가시킬 수 있다.
다양한 실시예에서, 제1 세트의 TV(111)는 구리, 알루미늄, 금 또는 다른 유사 물질로 형성될 수 있다. 다양한 실시예에서, 제2 다이(140)는 언더 버프 금속화 구조물, 마이크로 언더 범프 금속화 구조물, 금속 필러, 금속 필러 범프 등을 이용하여 제2 RDL(116)에 결합될 수 있다. 다양한 실시예에서, 제2 세트의 도전 접속부(150)는 납이 없는 솔더, 공융 납 등을 포함할 수 있다. 다양한 실시예에서, 제1 캡슐화 물질(112)은 예를 들어 수지, 에폭시, 폴리머 등을 포함할 수 있고 제1 콤포넌트 패키지(11) 내의 콤포넌트를 환경 또는 오염물로부터 보호할 수 있다. 일 실시예에서, 제1 콤포넌트 패키지(110)는 제1 세트의 도전 특징부(115) 및 제1 세트의 도전 접속부(130) 사이에 위치 지정된 캡슐 재료 또는 언더 필(under fill)(미도시)을 포함할 수 있다.
상술한 바와 같이, PoP 구조물(100)은 제2 콤포넌트 패키지(160)를 포함할 수 있다. 제2 콤포넌트 패키지(160)는 인터포저(162)에 전기적으로 결합된 하나 이상의 제3 다이(들)(161)를 포함할 수 있다. 제2 콤포넌트 패키지(160)는 여기에서 더 설명하는 바와 같이 제1 콤포넌트 패키지(110)에 전기적으로 결합될 수 있다. 인터포저(162)는 세라믹, 플라스틱, 적층체, 필름, 유전체 또는 다른 유사한 층일 수 있고 제3 금속화 트레이스 또는 RDL(165)을 포함할 수 있다. 인터포저(162)는 또한 PCB, 기판, 실리콘 기판, 유기 기판, 세라믹 기판, 정측 기판, 또 다른 반도체 패키지 등일 수 있다. 제3 트레이스(165)는 구리, 알루미늄, 금 또는 다른 유사한 물질로 형성되어 인터포저(162)를 통해 도전 경로를 제공할 수 있다. 인터포저(162)는 또한 구리, 알루미늄, 니켈 또는 다른 유사한 물질로 형성될 수 있는 TV(166)를 포함할 수 있다.
제1 측면 상에, 인터포저(162)는 그 위에 형성된 제5 세트의 도전 특징부(163)를 갖고, 이 제5 세트의 도전 특징부(163)는 또한 제3 트레이스(165)에 전기적으로 결합될 수 있다. 대향하는 제2 측면 상에, 인터포저(162)는 그 위에 형성된 제6 세트의 도전 특징부(167)를 갖고, 이 제6 세트의 도전 특징부(167)는 또한 제3 트레이스(165)에 전기적으로 결합될 수 있다. 제5 및 제6 세트의 도전 특징부는 구리, 알루미늄, 금 또는 다른 유사한 물질로 형성될 수 있다. 하나 이상의 제3 다이(들)(161)는 제3 세트의 도전 접속부(164)를 통해 제5 세트의 도전 특징부(163)에 결합될 수 있다. 제3 세트의 도전 접속부(164)는 예를 들어 모세관 와이어 본드를 포함할 수 있고, 이 모세관 와이어 본드는 알루미늄, 구리, 금 또는 다른 와이어 본딩 물질로 형성될 수 있다. 일 실시예에서, 제3 세트의 도전 접속부(164)는 예를 들어 열압축 본드(TCB)를 이용하여 제5 세트의 도전 특징부(163)에 결합될 수 있다.
도 1은 설명의 목적으로 와이어 본딩 기술을 이용하여 (즉, 제3 세트의 도전 접속부(164)를 통해) 제3 다이(들)(161) 사이에 형성된 전기적 접속부를 나타낸다. 다른 실시예는 플립플롭, 볼 그리드 어레이, TV, 언더 범프 금속화, 도전 필러 등의 다른 방법을 이용할 수 있다.
제2 콤포넌트 패키지(160)는 콤포넌트 상에 형성되어 콤포넌트를 환경 및/또는 외부 오염물로부터 보호할 수 있는 제2 캡슐화 물질(168)을 더 포함할 수 있다. 다양한 실시예에서, 제2 캡슐화 물질(168)은 예를 들어, 수지, 에폭시, 폴리머 등을 포함할 수 있다. 제2 콤포넌트 패키지(160)는 제3 세트의 도전 특징부(119) 및 제6 세트의 도전 특징부(167) 사이에 결합된 제4 세트의 도전 접속부(170)를 통해 제1 콤포넌트 패키지(110)에 결합될 수 있다. 제4 세트의 도전 접속부(170)는 예를 들어 납이 없는 솔더, 공융 납, 도전 필러, 그 조합 등을 포함할 수 있다. 일 실시예에서, 제3 및 제6 세트의 도전 특징부(119 및 167) 중의 하나 또는 둘다의 표면에 플럭스(미도시)를 인가할 수 있다. 플럭스는 제2 RDL(116) 또는 인터포저(162) 중의 하나의 표면이 플럭스 내에 담기거나 코팅될 수 있는 동작시 인가될 수 있다. 플럭스는 인터포저의 도전 특징부의 표면을 정화하는 것을 도와 도전 특징부(119 및 167)의 제3 및 제6 세트의 각 도전 특징부 사이의 전기 콘택의 형성을 도울 수 있다. 다른 실시예에서, MUF(180)는 제1 및 제2 콤포넌트 패키지(110, 160) 사이에 위치 지정되어 제2 RDL(116) 및 인터포저(162) 사이의 영역을 환경 또는 외부 오염물로부터 보호할 수 있다.
일 실시예에서, 제3 다이(들)(161)는 와이드 데이터 워드 DRAM, DDR RAM 또는 저전력 DDR(LPDDR) RAM 등의 동적 RAM일 수 있다. 다른 실시예에서, 제3 다이(들)(161)는 SRAM 등의 정적 RAM 또는 EPROM 또는 FLASH 메모리 등의 비휘발성 장치일 수 있다.
도 2 내지 16은 실시예를 형성하는데 있어서의 중간 단계의 단면도이다. 도 2는 본 개시물의 실시예에 따라 제1 패키지(110)의 형성을 시작하기 위하여 제1 캐리어(210) 상에 제1 금속층(220)을 배치하는 단면도이다. 제1 캐리어(210)는, 제한되지 않지만, 글래스 실리콘, 세라믹, 그 조합 등을 포함하는 다양한 물질로 형성될 수 있다. 도 2에 도시된 바와 같이, 제1 금속층(220)은 제1 접착층(230)을 이용하여 제1 캐리어(210) 상에 일시적으로 장착되거나 그에 부착될 수 있다. 도 2에 도시된 바와 같이 제1 금속층(220) 및 제1 접착층(230)의 두께는 설명의 목적으로 과장되었다.
다양한 실시예에서, 제1 금속층(220)은 예를 들어 구리 포일, 구리 합금, 알루미늄, 텅스텐, 은, 그 조합 등의 도전 물질로 형성될 수 있다. 다양한 실시예에서, 제1 접착층(230)은 예를 들어 에폭시 등으로 형성될 수 있다.
일 실시예에서, 제1 금속층(220)은 전기 화학 또는 도금 프로세스를 통해 형성될 수 있다. 이러한 프로세스를 위하여, 제1 포토레지스트 마스크(미도시)가 제1 접착층(230) 또는 (제1 접착층(230)이 없는 실시예에서) 제1 캐리어(210) 상에 형성될 수 있다. 제1 마스크는 제1 금속층을 위한 영역을 제공하기 위하여 에칭될 수 있고, 그 후, 제1 금속층은 예를 들어 전기 도금 기술을 이용하여 그 위에 형성될 수 있다.
도 3은 제1 금속층(220) 상에 제1 세트의 TV(111)를 형성하는 단면도이다. 금속층(220)은 그로부터 형성될 수 있는 제1 세트의 TV(111)에 대한 시드층으로서 동작할 수 있다. 일 실시예에서, TV(111)은 전기 화학 증착 또는 도금 프로세스를 통해 형성될 수 있다. 이러한 프로세스를 위하여, 제2 포토레지스트 마스크(미도시)는 제1 금속층(220) 상에 형성될 수 있다. 제2 마스크는 에칭되어 제1 금속층(220) 상에 TV(111)를 위치 지정하는 개구를 제공할 수 있다. TV(111)은 그후 예를 들어 전기 도금 기술을 이용하여 제1 금속층(220) 상에 형성되고 그 후 마스크는 제거될 수 있다. TV(111)가 형성된 후에, 제1 다이(120)의 후면은 제1 금속층(220) 상에 장착 또는 부착될 수 있다. 제1 다이(120)의 전면 상에, 제1 패시베이션층(210), 및 제1 다이(120)로의 전기 접속을 제공할 수 있는 제7 세트의 도전 특징부(312)가 형성될 수 있다.
다양한 실시예에서, 제1 세트의 TV(111)는 구리, 알루미늄, 텅스텐, 금, 그 조합 등으로 형성될 수 있다. 다양한 실시예에서, 제1 패시베이션층(310)은 폴리이미드층, PBO, BCB, 비감광성 폴리머일 수 있고, 다른 실시예에서, 나이트라이드, 카바이드 또는 다른 유전체로 형성될 수 있다. 도 3에 도시된 바와 같이 TV(111)는 또한 도전 필러라 할 수 있다. (도 4에 대하여 후술하는 바와 같이) 도전 필러 주변에 캡슐화 물질을 형성할 때, 필러는 TV(111)라 할 수 있다.
도 4에 도시된 바와 같이, 제1 캡슐화 물질(112)은, 제한되지 않지만, 제1 다이(120) 및 제1 세트의 TV(111)를 포함하는 제1 패키지 내의 콤포넌트 상에 형성될 수 있다. 제1 캡슐화 물질(112)은 주입(injection), 몰딩, 또는 다른 유사한 프로세스를 이용하여 콤포넌트 상에 형성될 수 있다. 일 실시예에서, 제1 캡슐화 물질(112)은 제1 다이(120)의 전면 표면을 소정의 높이까지 커버할수 있다. 다양한 실시예에서, 제1 캡슐화 물질(112)은 예를 들어 수지, 에폭시, 폴리드 등을 포함할 수 있다 제1 콤포넌트 패키지(110) 내의 콤포넌트를 환경 또는 오염물로부터 보호할 수 있다. 도 5를 참조하면, 제1 캡슐화 물질(112)은 연마, 랩핑(lapping), 또는 다른 유사한 프로세스를 통해 제1 다이(120)의 전면 표면으로부터 제거하여 제1 다이(120) 및 제7 세트의 도전 특징부(312)의 상면을 노출시킬 수 있다.
도 6은 제1 다이(120)의 전면 상의 제1 RDL(113)의 형성을 나타낸다. 제1 RDL(113)은 하나 이상의 감법 에칭 프로세스, 단일 다마신 기술 및/또는 듀얼-다마신 기술을 이용하여 형성될 수 있다. 기재한 바와 같이, 제1 RDL(113)은 제1 금속화 트레이스(114)를 포함할 수 있고 그 위에 형성된 제1 세트의 도전 특징부(115)를 가질 수 있다. 본 개시물의 실시예에 따르면, 제1 RDL(113)은 대략 60μm의 높이까지 형성될 수 있고, 그 높이는, 제한되지 않지만, 제1 RDL(113)을 통한 제1 트레이스(114)의 라우팅 요구사항을 포함하는 다양한 설계 인자에 따라 결정됨에 따라 변경될 수 있다.
도 7에 도시된 바와 같이, 제1 세트의 도전 특징부(115)는 그 위에 형성된 제1 세트의 도전 접속부(130)를 가질 수 있다. 다양한 실시예에서, 제1 세트의 도전 접속부(130)는 납이 없는 솔더, 공융 납, 도전 필러, 그 조합 등을 포함할 수 있다. 일 실시예에서, MUF(710)는 제1 세트의 도전 특징부(115) 및/또는 제1 세트의 도전 접속부(130) 사이에 위치 지정되어 제1 RDL(113)을 환경 또는 외부 오염물로부터 보호할 수 있다. MUF(710)는 예를 들어 폴리머, 에폭시 또는 다른 유사한 물질로 형성될 수 있다.
도 8을 참조하면, 제1 기능 테스트는 제1 세트의 도전 접속부(130)를 통해 제1 다이(120)에 대하여 수행될 수 있다. 기능 테스트는 제1 트레이스(114)를 통해 제1 RDL(113)을 통한 제1 다이(120)로의 접속을 확인하기 위하여 수행될 수 있다. 기능 테스트는 또한 제1 다이(120)의 소정의 기능을 확인하기 위하여 수행될 수 있다.
도 9에 도시된 바와 같이, 제2 캐리어(910)가 제1 캐리어(210)에 대향하는 측면 상에 부착되거나 본딩될 수 있다. 제2 캐리어(910)는, 제한되지 않지만, 글래스, 실리콘, 세라믹, 그 조합 등을 포함하는 다양한 물질로 형성될 수 있다. 도 10을 참조하면, 제1 캐리어(210)는 제1 다이(120)의 후면 영역으로부터 제거되거나 디본딩(debonded)될 수 있다. 랩핑 또는 연마 스포세스가 수행되어 후면 영역으로부터 제1 금속층(220) 및 제1 접착층(230)(도 2에 도시됨)을 제거할 수 있다.
도 11은 제1 다이(120)의 후면 상의 제2 RDL(116)의 형성을 도시한다. 제2 RDL(116)은 하나 이상의 감법 에칭 프로세스, 단일 다마신 기술 및/또는 듀얼-다마신 기술을 이용하여 수행될 수 있다. 상술한 바와 같이, 제2 RDL(116)은 그 위에 형성된 제2 및 제3 세트의 도전 특징부(118 및 119)를 가질 수 있고, 이들 도전 특징부의 각각은 또한 제2 트레이스(117)에 결합될 수 있다.
도 12에 도시된 바와 같이, 제2 다이(140)는 제2 RDL(116)에 전기적으로 결합될 수 있다. 제2 세트의 도전 접속부(150)는 제2 다이(140)의 제4 세트의 도전 특징부(141) 및 제2 RDL(116)의 제2 세트의 도전 특징부(118) 사이에 형성될 수 있다. 다양한 실시예에서, 제2 다이(140)는 언더 범프 금속화 구조물, 마이크로 언더 범프 금속화 구조물, 금속 필러 등을 이용하여 제2 RDL(116)에 결합될 수 있다. 다양한 실시예에서, 제2 세트의 도전 접속부(150)는 납이 없는 솔더, 공융 납 등을 포함할 수 있고, 제2 다이(140)는 리플로우(reflow) 프로세스를 이용하여 제2 RDL(116)에 결합될 수 있다. 다른 실시예에서, 제2 다이(140)는 열 압착 프로세스를 이용하여 제2 RDL(116)에 결합될 수 있다. 일 실시예에서, MUF(미도시)는 제2 다이(140) 및 제2 RDL(116) 사이에 위치 지정될 수 있다. 본 개시물의 실시예에 따라, 제1 다이(120)의 전면으로부터 제2 RDL(116)의 도전 특징부 세트까지의 높이는 약 90μm일 수 있고, 이는 제2 다이를 제1 다이에 전기적으로 결합하기 위한 TV를 채용하는 메모리 패키지보다 패키지 개선을 제공할 수 있다.
도 13에 도시된 바와 같이, 제1 콤포넌트 패키지(110)는 다이싱(dicing) 테이프(1310)에 부착될 수 있고 제2 캐리어(910)는 디본딩 또는 제거될 수 있다. 도 14에 도시된 바와 같이, 제2 기능 테스트는 제1 세트의 도전 접속부(130), 제1 및 제2 RDL(113, 116)(및 해당 트레이스), 제2 및 제4 도전 특징부(118, 141) 및 제2 세트의 도전 접속부(150)를 통해 형성된 제2 다이(140)로의 도전 경로를 통한 접속을 확인하기 위하여 제1 패키지에 대하여 수행될 수 있다. 제2 기능 테스트는 또한 제2 다이(140)의 기능을 확인하기 위하여 수행될 수 있다.
도 15에서, 스크라이브 라인(scribe line)(1510)을 따라 단일화를 수행하여 도 1에 도시된 바와 같이 제1 콤포넌트 패키지(110)를 형성할 수 있다. 단일화는 절단 또는 단일화 프로세스를 통해 수행될 수 있고, 기계적 또는 레이저 톱은 제1 콤포넌트 패키지(110)의 다수의 인스턴스(multiple instances)를 서로 분리하는데 사용될 수 있다. 제1 콤포넌트 패키지(110)는 단일화 후에 다이싱 테이프(1310)로부터 제거될 수 있다.
도 16을 참조하면, 도 1에 도시된 바와 같이, 제2 콤포넌트 패키지(160)는 제1 패키지(110)에 결합되어 PoP 구조물(100)을 형성할 수 있다. 결합은 제3 세트의 도전 특징부(119) 및 제6 세트의 도전 특징부(167) 사이에 전기적으로 접속될 수 있는 제4 세트의 도전 접속부(170)를 통해 수행될 수 있다. 리플로우 프로세스는 제2 콤포넌트 패키지(160)를 제1 콤포넌트 패키지(110)로 결합하는 전기적 접속부를 형성하는데 사용될 수 있다. 제2 콤포넌트 패키지(160)는 제1 콤포넌트 패키지(110)의 콤포넌트 및 형성에 기재된 유사한 프로세스 및 기술을 이용하여 형성될 수 있다.
일 실시예에서, 장치가 제공된다. 장치는 제1 반도체 소자, 제2 반도체 소자, 상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 RDL, 상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고 상기 제2 반도체 소자에 전기적으로 결합된 제2 RDL, 상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질, 및 상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합시키는 복수의 스루 비아(through via)를 포함한다.
또 다른 실시예에서, 또 다른 장치가 제공된다. 장치는 제1 패키지 콤포넌트, 및 제2 패키지 콤포넌트를 포함한다. 제1 패키지 콤포넌트는 제1 및 제2 측면을 갖는 제1 반도체 소자, 상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 RDL, 상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고, 제2 반도체 소자에 전기적으로 결합되고, 그 위에 형성된 복수의 제1 도전 특징부를 갖는 제2 RDL, 상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질, 및 상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합하는 복수의 스루 비아를 포함한다. 제2 패키지 콤포넌트는 제3 반도체 소자, 및 상기 제3 반도체 소자에 전기적으로 결합되고, 그 위에 형성된 복수의 제2 도전 특징부를 갖는 인터포저를 포함하고, 상기 제2 도전 특징부는 상기 제2 RDL의 제1 도전 특징부에 전기적으로 결합된다.
또 다른 실시예에서, 방법이 제공된다. 방법은 제1 캐리어 상에 제1 금속층을 형성하는 단계, 상기 제1 금속층 상에 복수의 도전 필러를 형성하는 단계, 제1 반도체 소자의 제1 측면을 상기 제1 금속층에 부착하는 단계, 상기 제1 반도체 소자 및 상기 복수의 도전 필러를 캡슐화하는 단계, 상기 제1 반도체 소자의 제2 측면 상에 제1 재분배층(RDL)을 형성하는 단계 - 상기 제1 RDL은 상기 도전 필러 및 상기 제1 반도체 소자에 전기적으로 결합됨 -, 제2 캐리어를 상기 제1 RDL에 부착하는 단계, 상기 제1 캐리어 및 상기 제1 금속층을 제거하는 단계, 및 상기 제1 반도체 소자의 제1 측면 상에 제2 RDL을 형성하여 제1 패키지 콤포넌트를 형성하는 단계 - 상기 제2 RDL은 상기 복수의 도전 필러에 전기적으로 결합됨 - 를 포함한다.
상기 설명은 실시예의 일반적인 설명을 제공하고 실시예가 수많은 다른 특징을 포함할 수 있는 것을 이해해야 한다. 예를 들어, 실시예는 언더 범프 금속화층, 패시베이션층, 몰딩 컴파운드, 추가의 다이 및/또는 기판 등을 포함할 수 있다. 추가적으로, 제1, 제2 및 제3 다이(120, 140 및 161)의 구조, 배치 및 위치 지정은 단지 설명의 목적으로 제공되고, 따라서, 다른 실시예는 상이한 구조, 배치 및 위치를 이용할 수 있다.
본 실시예 및 그 이점이 상세히 기재되지만, 첨부된 청구범위에 의해 정의된 개시물의 사상 및 범위를 벗어나지 않고 다양한 변형, 대체, 변경이 가능함을 인식해야 한다. 예를 들어, 상술한 바와 같은 구조 및 단계의 순서는 본 개시물의 범위 내에서 변경될 수 있음을 당업자는 쉽게 이해할 것이다.
또한, 본 출원의 범위는 본 명세서에 기재된 프로세스, 머신, 제조, 물질의 구성, 수단, 방법 및 단계의 특정 실시예에 한정되는 것으로 의도되지 않는다. 당업자가 개시물로부터 용이하게 인식하는 바와 같이 여기에 기재된 해당 실시예와 동일한 결과를 실질적으로 달성하거나 동일한 기능을 실질적으로 수행하고 현재 존재하거나 미래에 개발될 프로세스, 머신, 제조, 물질의 구성, 수단, 방법 또는 단계는 본 개시물에 따라 이용될 수 있다. 따라서, 첨부된 청구범위는 이러한 프로세스, 머신, 제조, 물질의 구성, 수단, 방법 또는 단계를 그 범위 내에 포함하도록 의도된다.
100: PoP 구조물
110: 제1 콤포넌트 패키지
160: 제2 콤포넌트 패키지
120: 제1 다이
113: 제1 RDL
116: 제 RDL
112: 제1 캡슐화 물질
114: 제1 금속화 트레이스

Claims (10)

  1. 제1 반도체 소자;
    제2 반도체 소자;
    상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 재분배층(redistribution layer; RDL);
    상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고 상기 제2 반도체 소자에 전기적으로 결합된 제2 RDL;
    상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질; 및
    상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합시키는 복수의 스루 비아(through via)를
    포함하는 장치.
  2. 제1항에 있어서, 상기 복수의 스루 비아는 상기 제1 반도체 소자에 인접한 하나 이상의 영역 내에서 상기 제1 물질을 통해 연장하는 것인 장치.
  3. 제1항에 있어서, 상기 스루 비아는 구리, 알루미늄, 금, 텅스텐 및 그 조합으로 구성되는 그룹으로부터 선택된 물질로 이루어지는 것인 장치.
  4. 제1항에 있어서, 상기 제1 반도체 소자는 애플리케이션 프로세서 유닛이고, 상기 제2 반도체 소자는 메모리 IC 다이인 것인 장치.
  5. 제1 패키지 콤포넌트 및 제2 패키지 콤포넌트를 포함하는 장치에 있어서,
    상기 제1 패키지 콤포넌트는,
    제1 측면 및 제2 측면을 갖는 제1 반도체 소자;
    상기 제1 반도체 소자의 제1 측면에 전기적으로 결합된 제1 재분배층(redistribution layer; RDL);
    상기 제1 반도체 소자의 제2 측면 상에 위치 지정되고, 제2 반도체 소자에 전기적으로 결합되고, 위에 형성된 복수의 제1 도전 특징부를 갖는 제2 RDL;
    상기 제1 RDL 및 상기 제2 RDL 사이에 위치 지정된 제1 물질; 및
    상기 제1 물질을 통해 연장하고 상기 제1 RDL을 상기 제2 RDL에 전기적으로 결합하는 복수의 스루 비아를 포함하고,
    상기 제2 패키지 콤포넌트는,
    제3 반도체 소자; 및
    상기 제3 반도체 소자에 전기적으로 결합되고, 위에 형성된 복수의 제2 도전 특징부 - 상기 제2 도전 특징부는 상기 제2 RDL의 제1 도전 특징부에 전기적으로 결합됨 - 를 갖는 인터포저를
    포함하는 것인 장치.
  6. 제1 캐리어 상에 제1 금속층을 형성하는 단계;
    상기 제1 금속층 상에 복수의 도전 필러(pillar)를 형성하는 단계;
    제1 반도체 소자의 제1 측면을 상기 제1 금속층에 부착하는 단계;
    상기 제1 반도체 소자 및 상기 복수의 도전 필러(pillar)를 캡슐화하는 단계;
    상기 제1 반도체 소자의 제2 측면 상에 제1 재분배층(redistribution layer; RDL) - 상기 제1 RDL은 상기 도전 필러 및 상기 제1 반도체 소자에 전기적으로 결합됨 - 을 형성하는 단계;
    제2 캐리어를 상기 제1 RDL에 부착하는 단계;
    상기 제1 캐리어 및 상기 제1 금속층을 제거하는 단계; 및
    상기 제1 반도체 소자의 제1 측면 상에 제2 RDL - 상기 제2 RDL은 상기 복수의 도전 필러에 전기적으로 결합됨 - 을 형성하여 제1 패키지 콤포넌트를 형성하는 단계를
    포함하는 방법.
  7. 제6항에 있어서, 상기 복수의 도전 필러는 상기 제1 반도체 소자의 수직부에 인접하는 영역 내에 위치 지정되는 것인 방법.
  8. 제6항에 있어서, 상기 제1 반도체 소자 및 상기 도전 필러는 수지, 에폭시, 폴리머 및 그 조합을 구성되는 그룹으로부터 선택된 물질 내에 캡슐화되는 것인 방법.
  9. 제6항에 있어서,
    상기 제1 패키지 콤포넌트를 다이싱(dicing) 테이프에 부착하는 단계;
    상기 제1 패키지 콤포넌트로부터 상기 제2 캐리어를 제거하는 단계;
    상기 제1 패키지 콤포넌트를 단일화하는(singulating) 단계; 및
    패키지 온 패키지(package-on-package; PoP) 구조물을 형성하기 위하여 제2 패키지 콤포넌트를 상기 제1 패키지 콤포넌트에 결합하는 단계를
    더 포함하는 방법.
  10. 제9항에 있어서, 상기 제1 RDL 상의 복수의 도전 접속부를 통해 상기 PoP 구조물을 인쇄 회로 기판에 접속하는 단계를 더 포함하는 방법.
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US9748216B2 (en) 2017-08-29
US20140091471A1 (en) 2014-04-03
US8889484B2 (en) 2014-11-18

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