CN102763217A - 半导体裸片封装结构 - Google Patents

半导体裸片封装结构 Download PDF

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CN102763217A
CN102763217A CN201180009172XA CN201180009172A CN102763217A CN 102763217 A CN102763217 A CN 102763217A CN 201180009172X A CN201180009172X A CN 201180009172XA CN 201180009172 A CN201180009172 A CN 201180009172A CN 102763217 A CN102763217 A CN 102763217A
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nude film
flip
sept
semiconductor nude
filler
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皮尤沙·古普塔
尚塔努·卡尔丘里
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Qualcomm Inc
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Qualcomm Inc
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种系统级封装，其包含：倒装芯片半导体裸片，其处于封装衬底上；间隔物，其处于所述封装衬底上；及导线接合半导体裸片，其由所述间隔物及所述倒装芯片半导体裸片支撑。

Description

半导体裸片封装结构
技术领域
本发明大体上涉及经封装半导体裸片。更具体来说，本发明涉及改进的半导体裸片封装，在所述半导体裸片封装中，第一裸片置放在第二裸片及间隔物上。
背景技术
按照惯例，芯片封装包括多个半导体裸片。一些芯片封装包括一具有小形状因数的射频(RF)裸片及一较大数字裸片。在图1中展示一个现有技术芯片封装。所述芯片封装100包括RF裸片101及数字裸片102。在图1中，所述较大数字裸片102经结构化为倒装芯片球状栅格阵列(BGA)，并且所述RF裸片101使用若干导线接合结构。所述芯片封装100使用毛细底填料103，所述毛细底填料103增加生产成本并导致较大总封装，因为所述毛细底填料103从所述较大数字裸片102的长度尺寸及宽度尺寸稍微向外延伸。此外，因为导线的电感极高且在RF裸片101中导致非线性，所以将若干导线接合用于所述堆叠的RF裸片101倾向于使RF性能降级。另一做法(未在本文中展示)以若干导线接合结构实施裸片101及102两者。此做法也遭受降低的RF性能。
又一做法(也未在本文中展示)将裸片101及102两者并排置放于所述封装中。然而，所述并排做法是以增加的封装大小为代价，与图1中所展示的实施例相比更是如此。
发明内容
本发明的各种实施例包括一种系统级封装，所述系统级封装具有：倒装芯片半导体裸片，其处于封装衬底上；间隔物，其处于所述封装衬底上；及导线接合半导体裸片，其由所述间隔物及所述倒装芯片半导体裸片支撑。
根据另一实施例，一种芯片封装包括：倒装芯片半导体裸片，其处于封装衬底上；用于散热的装置，其处于所述封装衬底上；及导线接合半导体裸片，其由所述散热装置及所述倒装芯片半导体裸片支撑。
根据本发明的另一实施例，一种用于组装系统级封装的方法包括：在封装衬底上安置倒装芯片半导体裸片；在所述封装衬底上安置倒装芯片间隔物；及将导线接合半导体裸片安置到所述间隔物及所述倒装芯片半导体裸片上。
根据本发明的又一实施例，一种系统级封装包含：倒装芯片半导体裸片，其处于封装衬底上；用于提供机械支撑的装置，其安置于所述封装衬底上；及导线接合半导体裸片，其安置于所述机械支撑装置及所述倒装芯片半导体裸片上。
前文已相当广泛地概述了本发明的特征及技术优势以便可较好地理解下文的详细描述。下文将描述形成本发明的权利要求书的标的物的额外特征及优点。所属领域的技术人员应了解，所揭示的概念及特定实施例可容易用作用于修改或设计用于进行本发明的相同目的的其它结构的基础。所属领域的技术人员还应认识到，这些等效构造并不脱离如在随附权利要求书中所阐述的本发明的技术。当结合附图考虑时，从以下描述将较好地理解据信为本发明所特有的新颖特征(关于其组织及操作方法两者)以及另外的目的及优点。然而，应明确理解，所述图中的每一者仅是出于说明及描述目的而加以提供，且既定不界定对本发明的限制。
附图说明
为实现对本发明的较全面理解，现参考结合附图进行的以下描述。
图1为现有技术芯片封装的说明。
图2为展示一示范性无线通信系统的框图，在所述无线通信系统中，可有利地使用本发明的一实施例。
图3A及3B分别为根据本发明的一个实施例而调适的一示范性芯片封装的俯视图框图及侧视图框图。
图4为根据本发明的一个实施例而调适的一示范性芯片封装的说明。
图5为根据本发明的一个实施例而调适的用于制造芯片封装的示范性过程的说明。
具体实施方式
图2展示示范性无线通信系统200，在所述无线通信系统200中，可有利地使用本发明的实施例。出于说明的目的，图1展示三个远程单元220、230及240以及两个基站250及260。应认识到，无线通信系统可具有更多的远程单元及基站。远程单元220、230及240分别包括改进的半导体裸片封装225A、225B及225C，所述改进的半导体裸片封装是如下文进一步论述的实施例。图2展示从基站250及260到远程单元220、230及240的前向链路信号280以及从远程单元220、230及240到基站250及260的反向链路信号290。
在图2中，将远程单元220展示为移动电话，将远程单元230展示为便携式计算机，且将远程单元240展示为无线本地回路系统中的计算机。举例来说，所述远程单元可为移动电话、手持式个人通信系统(PCS)单元、例如个人数据助理等便携式数据单元、具有GPS能力的装置、导航装置、机顶盒、例如音乐播放器、视频播放器等媒体播放器及娱乐单元、例如仪表读取设备等固定位置数据单元、或者存储或检索数据或计算机指令的任何其它装置，或其任何组合。虽然图2说明根据本发明的教示的若干远程单元，但本发明不限于这些示范性所说明的单元。本发明可适合地用于包括半导体裸片封装的任何装置中。
图3A及3B分别为根据本发明的一个实施例而调适的示范性芯片封装300的俯视图框图及侧视图框图。图3A展示芯片封装300的俯视图。图3B展示芯片封装300的侧视图。
芯片封装300包括实施为倒装芯片BGA的RF裸片301、具有导线接合304的数字裸片302及安置于封装衬底305上的间隔物303。在芯片封装300中，数字裸片302安置于间隔物303及RF芯片301上，并由间隔物303及RF芯片301支撑。因为RF裸片301被实施为倒装芯片BGA，所以其并不遭受图1中所展示的实施例的降低的RF性能。
此外，在一些实施例中，因为仅模制底填料(Mold-Only Underfill，MUF)306包住且充分支撑芯片301及302两者，所以芯片封装300可放弃使用毛细底填料而改为使用仅模制底填料306。通常，仅模制底填充工艺限于用于小裸片及高间距裸片。在图3中，较小裸片(301)是具有较大间距的倒装芯片裸片以使得所述较小裸片适于与仅模制底填充工艺一起使用。相比来说，在图1中，较大数字裸片102为具有小间距的倒装芯片裸片，从而使得仅模制底填充工艺比毛细底填料103不合需要。如此项技术中已知，底填料将一裸片附着到一封装上所述底填料的触点以免受热膨胀效应及机械冲击效应。仅模制底填料306是囊封整个封装而非单个裸片的底填料。图3A及3B中所展示的实施例利用仅模制底填料306作为RF裸片301的底填料，借此消除由图1的现有技术所采取的涂覆毛细底填料的步骤。但应注意，各种实施例并不排除使用毛细底填料。
RF裸片301被置放于封装300的略偏心处，以使得可易于将来自RF裸片301的信号路由到封装300的边缘。然而，假如从封装300去除间隔物303，则数字裸片302的悬垂量会过度。因而，在一个方面中，间隔物303对数字裸片302提供机械支撑，同时允许RF裸片301置放于偏心处。此外，在图3A及3B的实施例中，仅模制底填料306由具有例如硅石粒子等微粒的环氧树脂制成。在本实施例中，间隔物303由比仅模制底填料306的环氧树脂化合物更有效地传导热的硅制成。因而，间隔物303凭借其材料提供了用于将热从数字裸片302传递到衬底305的路径，借此提供散热。在另一实施例中，间隔物303在通孔中包括例如铜等导热材料以进一步提高间隔物303的热传递能力。
图4为根据本发明的一个实施例而调适的示范性芯片封装400的说明。在许多实施例中，有可能使用薄膜沉积工艺在一个或一个以上间隔物上实施无源装置。举例来说，无源装置包括电感器、电容器及电阻器。芯片封装400包括实施为倒装芯片BGA的间隔物403，间隔物403具有集成于其上的无源装置(图中未展示)。所述无源装置通过间隔物403的倒装芯片触点与芯片封装400中的其它组件电连通，且间隔物403提供如上文关于图3A及3B所论述的机械支撑及热传递。在一些实施例中，在例如间隔物403等间隔物上实施无源装置可通过以其它方式将置放于外部的无源装置移动到所述间隔物的占据面积内来节省空间。
上文所展示的实施例包括一个导线接合裸片、一个间隔物及一个较小倒装芯片裸片，但实施例不限于此。举例来说，芯片封装可包括两个或两个以上导线接合裸片、间隔物及较小倒装芯片裸片。因而，一些实施例可包括各自包括安置于一间隔物及一倒装芯片裸片的顶部上的导线接合裸片的两个或两个以上结构。此外，其它实施例可包括各自包括安置于一个或一个以上间隔物及一个或一个以上倒装芯片裸片上的导线接合裸片的结构。此外，虽然已在上文中提及若干特定材料，但应注意，可将现在已知或稍后开发的用于衬底、裸片、间隔物及底填料的其它适合的材料并入到本发明的各种实施例中。
图5为根据本发明的一个实施例而调适的用于制造芯片封装的示范性过程500的说明。举例来说，可在一制造设施中通过一个或一个以上机器及计算机控制的过程来执行过程500。
在框501中，在封装衬底上安置倒装芯片半导体裸片。在一些实施例中，所述倒装芯片半导体裸片包括RF裸片。框501可包括用于安置所述半导体裸片的各种适合技术中的任一者，包括但不限于，将所述半导体裸片上的焊料凸块与所述封装衬底上的触点对准，且在对准之后使焊料材料流动。
在框502中，在所述封装衬底上安置间隔物。在所述间隔物具有集成于其上的无源装置的实施例中，可以相似于框501中的用于在所述封装衬底上安置所述裸片的技术的方式来在所述封装衬底上安置所述间隔物。在所述间隔物为虚拟间隔物的实施例中，可通过(例如)使用环氧树脂裸片附接材料来在所述封装衬底上安置所述间隔物。
在框503中，通过(例如)使用环氧树脂裸片附接材料来将导线接合半导体裸片安置到所述间隔物及倒装芯片半导体裸片上。数字裸片的类型的实例包括(但不限于)数字信号处理器(DSP)、专用集成电路(ASIC)、通用处理器及其类似物。在一些实施例中，框503还包括在所述导线接合半导体裸片及所述封装衬底的触点之间形成导线接合连接。
在框504中，将仅模制底填料涂覆到所述封装以使得所述模制底填料包围所述倒装芯片半导体裸片、间隔物及导线接合裸片，如图3A、3B及4中所展示。一旦完成所述封装本身，即可准备在例如蜂窝式电话、导航装置、媒体播放器、个人数字助理(PDA)、计算机或其类似物等一个或一个以上装置中安装所述封装。
虽然将过程500展示为一系列离散过程，但是实施例未必限于图5中所展示的过程。一些实施例可在过程500中增加、省略、重布置或修改一个或一个以上框。举例来说，可将框501与502调换或同时执行框501与框502。此外，在一些实施例中，可将毛细底填料涂覆到所述倒装芯片半导体裸片，而在其它实施例中可省略所述毛细底填料而改为仅模制底填料。此外，各种实施例可包括通过(例如)薄膜处理而在所述间隔物上集成无源装置。
各种实施例包括与现有技术芯片封装相比的若干优点。举例来说，一些实施例通过将RF芯片实施为倒装芯片BGA(而非导线接合结构)来提高RF性能，而不会总体上增加所述封装的大小。事实上，一些实施例通过利用垂直堆叠及消除毛细底填料而利用比图1中所展示的封装小的封装。另外，一些实施例通过将间隔物用于导线接合裸片的散热而利用间隔物中的硅(或其它)材料的导热特性。
尽管已详细地描述本发明及其优点，但应理解，在不脱离如由所附权利要求书所界定的本发明的技术的情况下，可在本文中进行各种改变、替代及变更。此外，本申请案的范围既定不限于本说明书中描述的过程、机器、制品、物质组成、手段、方法及步骤的特定实施例。如一般所属领域的技术人员将易于从本发明而了解，可根据本发明利用执行与本文中所描述的对应实施例实质上相同的功能或实现与所述对应实施例实质上相同的结果的当前现有或稍后待开发的过程、机器、制品、物质组成、手段、方法或步骤。因此，所附权利要求书既定在其范围内包括这些过程、机器、制品、物质组成、手段、方法或步骤。

Claims (20)

1.一种系统级封装，其包含：
倒装芯片半导体裸片，其处于封装衬底上；
间隔物，其处于所述封装衬底上；及
导线接合半导体裸片，其由所述间隔物及所述倒装芯片半导体裸片支撑。
2.根据权利要求1所述的系统，其进一步包含模制底填料，所述模制底填料包围所述倒装芯片半导体裸片、所述间隔物及所述导线接合半导体裸片。
3.根据权利要求2所述的系统，其中所述模制底填料包含环氧树脂材料。
4.根据权利要求1所述的系统，其进一步包含毛细底填料，所述毛细底填料包围所述倒装芯片半导体裸片的至少一部分。
5.根据权利要求1所述的系统，其中所述间隔物包含集成的无源装置。
6.根据权利要求1所述的系统，其中所述系统级封装安置于选自由以下各者组成的群组的项目中：
手持型装置；及
个人计算机。
7.根据权利要求1所述的系统，其中所述倒装芯片半导体裸片包含射频RF裸片。
8.根据权利要求1所述的系统，其中所述导线接合半导体裸片包含数字裸片。
9.根据权利要求1所述的系统，其中所述间隔物与所述导线接合半导体裸片经热耦合。
10.根据权利要求9所述的系统，其中所述间隔物包含一材料，所述材料具有比安置于所述封装衬底上的模制底填料的热导率大的热导率。
11.一种用于组装系统级封装的方法，其包含：
在封装衬底上安置倒装芯片半导体裸片；
在所述封装衬底上安置间隔物；及
将导线接合半导体裸片安置到所述间隔物及所述倒装芯片半导体裸片上。
12.根据权利要求11所述的方法，其进一步包含：
将模制底填料涂覆到所述封装以使得所述模制底填料包围所述倒装芯片半导体裸片、所述间隔物及所述导线接合半导体裸片。
13.根据权利要求11所述的方法，其进一步包含：
在所述间隔物上集成至少一个无源装置。
14.根据权利要求11所述的方法，其进一步包含在选自由以下各者组成的群组的装置中安装所述系统级封装：
媒体播放器；
导航装置；
通信装置；
个人数字助理PDA；及
计算机。
15.一种系统级封装，其包含：
倒装芯片半导体裸片，其处于封装衬底上；
用于散热的装置，其处于所述封装衬底上；及
导线接合半导体裸片，其由所述散热装置及所述倒装芯片半导体裸片支撑。
16.根据权利要求15所述的系统，其进一步包含模制底填料，所述模制底填料包围所述倒装芯片半导体裸片、所述散热装置及所述导线接合半导体裸片。
17.根据权利要求15所述的系统，其不包含包围所述倒装芯片半导体裸片的毛细底填料。
18.一种系统级封装，其包含：
倒装芯片半导体裸片，其处于封装衬底上；
用于提供机械支撑的装置，其安置于所述封装衬底上；及
导线接合半导体裸片，其安置于所述机械支撑装置及所述倒装芯片半导体裸片上。
19.根据权利要求18所述的系统，其中所述机械支撑装置包含集成的无源装置及球状栅格阵列。
20.根据权利要求18所述的系统，其中所述倒装芯片半导体裸片包含射频RF裸片。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369678A (zh) * 2016-05-13 2017-11-21 北京中电网信息技术有限公司 一种系统级封装方法及其封装单元
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130286595A1 (en) * 2012-04-27 2013-10-31 Qualcomm Incorporated Thermal management floorplan for a multi-tier stacked ic package
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US9978732B2 (en) * 2014-09-30 2018-05-22 Skyworks Solutions, Inc. Network with integrated passive device and conductive trace in packaging substrate and related modules and devices
US10037970B2 (en) 2016-09-08 2018-07-31 Nxp Usa, Inc. Multiple interconnections between die
US20190287881A1 (en) * 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
KR102540050B1 (ko) 2018-07-05 2023-06-05 삼성전자주식회사 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040145040A1 (en) * 2003-01-29 2004-07-29 Toshiyuki Fukuda Semiconductor device and manufacturing method for the same
US20040195591A1 (en) * 2002-11-22 2004-10-07 John Gehman Digital and RF system and method therefor
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320014A (ja) * 2000-05-11 2001-11-16 Seiko Epson Corp 半導体装置及びその製造方法
US7262077B2 (en) * 2003-09-30 2007-08-28 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
JP2005197491A (ja) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd 半導体装置
JP2005303056A (ja) * 2004-04-13 2005-10-27 Toshiba Corp 半導体集積回路装置
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
JP4408832B2 (ja) * 2005-05-20 2010-02-03 Ｎｅｃエレクトロニクス株式会社 半導体装置
KR100665217B1 (ko) * 2005-07-05 2007-01-09 삼성전기주식회사 반도체 멀티칩 패키지
KR100764682B1 (ko) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) 집적회로 칩 및 패키지.
JP4331179B2 (ja) * 2006-03-20 2009-09-16 パナソニック株式会社 半導体装置
US7592702B2 (en) * 2006-07-31 2009-09-22 Intel Corporation Via heat sink material
TWI319618B (en) * 2006-12-18 2010-01-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7851906B2 (en) * 2007-03-26 2010-12-14 Endicott Interconnect Technologies, Inc. Flexible circuit electronic package with standoffs
US7691747B2 (en) * 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
US7867819B2 (en) * 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8405197B2 (en) * 2009-03-25 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US9093391B2 (en) * 2009-09-17 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with fan-in package and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040195591A1 (en) * 2002-11-22 2004-10-07 John Gehman Digital and RF system and method therefor
US20040145040A1 (en) * 2003-01-29 2004-07-29 Toshiyuki Fukuda Semiconductor device and manufacturing method for the same
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107369678A (zh) * 2016-05-13 2017-11-21 北京中电网信息技术有限公司 一种系统级封装方法及其封装单元
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备
US11705432B2 (en) 2019-08-28 2023-07-18 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices

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TW201140769A (en) 2011-11-16
BR112012020055A2 (pt) 2016-05-10
WO2011100351A1 (en) 2011-08-18
KR20120125370A (ko) 2012-11-14
JP2013519238A (ja) 2013-05-23

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