BR112012020055A2 - estrutura de pacote de pastilha semicondutora. - Google Patents

estrutura de pacote de pastilha semicondutora.

Info

Publication number
BR112012020055A2
BR112012020055A2 BR112012020055A BR112012020055A BR112012020055A2 BR 112012020055 A2 BR112012020055 A2 BR 112012020055A2 BR 112012020055 A BR112012020055 A BR 112012020055A BR 112012020055 A BR112012020055 A BR 112012020055A BR 112012020055 A2 BR112012020055 A2 BR 112012020055A2
Authority
BR
Brazil
Prior art keywords
semiconductor wafer
package structure
wafer package
semiconductor
package
Prior art date
Application number
BR112012020055A
Other languages
English (en)
Inventor
Piyush Gupta
Shantanu Kalchuri
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112012020055A2 publication Critical patent/BR112012020055A2/pt

Links

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    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

estrutura de pacote de pastilha semicondutora. um sistema de pacote compreendendo uma pastilha semicondutora de flip chip em um substrato de pacote, um espaçador no substrato de pacote, e uma pastilha semicondutora de ligação por fios suportada pelo espaçador e a pastilha de flip chip.
BR112012020055A 2010-02-10 2011-02-09 estrutura de pacote de pastilha semicondutora. BR112012020055A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/703,403 US20110193243A1 (en) 2010-02-10 2010-02-10 Unique Package Structure
PCT/US2011/024226 WO2011100351A1 (en) 2010-02-10 2011-02-09 Semiconductor die package structure

Publications (1)

Publication Number Publication Date
BR112012020055A2 true BR112012020055A2 (pt) 2016-05-10

Family

ID=43917093

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112012020055A BR112012020055A2 (pt) 2010-02-10 2011-02-09 estrutura de pacote de pastilha semicondutora.

Country Status (8)

Country Link
US (1) US20110193243A1 (pt)
EP (1) EP2534686A1 (pt)
JP (1) JP2013519238A (pt)
KR (1) KR20120125370A (pt)
CN (1) CN102763217A (pt)
BR (1) BR112012020055A2 (pt)
TW (1) TW201140769A (pt)
WO (1) WO2011100351A1 (pt)

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US20130286595A1 (en) * 2012-04-27 2013-10-31 Qualcomm Incorporated Thermal management floorplan for a multi-tier stacked ic package
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US9978732B2 (en) * 2014-09-30 2018-05-22 Skyworks Solutions, Inc. Network with integrated passive device and conductive trace in packaging substrate and related modules and devices
CN107369678A (zh) * 2016-05-13 2017-11-21 北京中电网信息技术有限公司 一种系统级封装方法及其封装单元
US10037970B2 (en) 2016-09-08 2018-07-31 Nxp Usa, Inc. Multiple interconnections between die
US20190287881A1 (en) * 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
KR102540050B1 (ko) 2018-07-05 2023-06-05 삼성전자주식회사 반도체 패키지
US11081468B2 (en) * 2019-08-28 2021-08-03 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320014A (ja) * 2000-05-11 2001-11-16 Seiko Epson Corp 半導体装置及びその製造方法
US7479407B2 (en) * 2002-11-22 2009-01-20 Freescale Semiconductor, Inc. Digital and RF system and method therefor
JP3819851B2 (ja) * 2003-01-29 2006-09-13 松下電器産業株式会社 半導体装置およびその製造方法
US7262077B2 (en) * 2003-09-30 2007-08-28 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
JP2005197491A (ja) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd 半導体装置
JP2005303056A (ja) * 2004-04-13 2005-10-27 Toshiba Corp 半導体集積回路装置
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
JP4408832B2 (ja) * 2005-05-20 2010-02-03 Ｎｅｃエレクトロニクス株式会社 半導体装置
KR100665217B1 (ko) * 2005-07-05 2007-01-09 삼성전기주식회사 반도체 멀티칩 패키지
KR100764682B1 (ko) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) 집적회로 칩 및 패키지.
JP4331179B2 (ja) * 2006-03-20 2009-09-16 パナソニック株式会社 半導体装置
US7592702B2 (en) * 2006-07-31 2009-09-22 Intel Corporation Via heat sink material
TWI319618B (en) * 2006-12-18 2010-01-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7851906B2 (en) * 2007-03-26 2010-12-14 Endicott Interconnect Technologies, Inc. Flexible circuit electronic package with standoffs
US7691747B2 (en) * 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
US7867819B2 (en) * 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8405197B2 (en) * 2009-03-25 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US9093391B2 (en) * 2009-09-17 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with fan-in package and method of manufacture thereof

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JP2013519238A (ja) 2013-05-23
WO2011100351A1 (en) 2011-08-18
US20110193243A1 (en) 2011-08-11
EP2534686A1 (en) 2012-12-19
KR20120125370A (ko) 2012-11-14

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