BRPI1014755A2 - pacote com múltiplos chips e método para proporcionar interco-nexões de matriz com matriz no mesmo - Google Patents
pacote com múltiplos chips e método para proporcionar interco-nexões de matriz com matriz no mesmoInfo
- Publication number
- BRPI1014755A2 BRPI1014755A2 BRPI1014755A BRPI1014755A BRPI1014755A2 BR PI1014755 A2 BRPI1014755 A2 BR PI1014755A2 BR PI1014755 A BRPI1014755 A BR PI1014755A BR PI1014755 A BRPI1014755 A BR PI1014755A BR PI1014755 A2 BRPI1014755 A2 BR PI1014755A2
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- BR
- Brazil
- Prior art keywords
- matrix
- same
- chip package
- interconnections
- providing
- Prior art date
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PCT/US2010/027035 WO2010151350A1 (en) | 2009-06-24 | 2010-03-11 | Multi-chip package and method of providing die-to-die interconnects in same |
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Families Citing this family (207)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7612443B1 (en) * | 2003-09-04 | 2009-11-03 | University Of Notre Dame Du Lac | Inter-chip communication |
US8466550B2 (en) * | 2008-05-28 | 2013-06-18 | Agency For Science, Technology And Research | Semiconductor structure and a method of manufacturing a semiconductor structure |
TWI413223B (zh) * | 2008-09-02 | 2013-10-21 | Unimicron Technology Corp | 嵌埋有半導體元件之封裝基板及其製法 |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
WO2011007507A1 (ja) | 2009-07-17 | 2011-01-20 | 日本電気株式会社 | 半導体パッケージ用基板および半導体パッケージ用基板の製造方法 |
TWI455265B (zh) * | 2010-11-01 | 2014-10-01 | 矽品精密工業股份有限公司 | 具微機電元件之封裝結構及其製法 |
US8823133B2 (en) | 2011-03-29 | 2014-09-02 | Xilinx, Inc. | Interposer having an inductor |
US8970956B2 (en) | 2011-03-30 | 2015-03-03 | Intel Corporation | On-chip diffraction grating prepared by crystallographic wet-etch |
US9406738B2 (en) | 2011-07-20 | 2016-08-02 | Xilinx, Inc. | Inductive structure formed using through silicon vias |
US9236278B2 (en) | 2011-09-23 | 2016-01-12 | Stats Chippac Ltd. | Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof |
KR101589843B1 (ko) | 2011-09-30 | 2016-01-28 | 인텔 코포레이션 | 3d 집적 회로 적층을 위한 층간 통신들 |
US9163995B2 (en) | 2011-10-21 | 2015-10-20 | Santa Barbara Infrared, Inc. | Techniques for tiling arrays of pixel elements |
US9748214B2 (en) | 2011-10-21 | 2017-08-29 | Santa Barbara Infrared, Inc. | Techniques for tiling arrays of pixel elements and fabricating hybridized tiles |
US10163877B2 (en) * | 2011-11-07 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | System in package process flow |
US9391427B2 (en) | 2011-11-18 | 2016-07-12 | Intel Corporation | Thermal management in packaged VCSELs |
US8927333B2 (en) * | 2011-11-22 | 2015-01-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Die carrier for package on package assembly |
US9330823B1 (en) | 2011-12-19 | 2016-05-03 | Xilinx, Inc. | Integrated circuit structure with inductor in silicon interposer |
CN104011851B (zh) | 2011-12-22 | 2017-06-27 | 英特尔公司 | 具有窗口插入器的3d集成电路封装 |
US9059179B2 (en) | 2011-12-28 | 2015-06-16 | Broadcom Corporation | Semiconductor package with a bridge interposer |
US9799627B2 (en) * | 2012-01-19 | 2017-10-24 | Semiconductor Components Industries, Llc | Semiconductor package structure and method |
US8704364B2 (en) * | 2012-02-08 | 2014-04-22 | Xilinx, Inc. | Reducing stress in multi-die integrated circuit structures |
US8704384B2 (en) | 2012-02-17 | 2014-04-22 | Xilinx, Inc. | Stacked die assembly |
US8742576B2 (en) * | 2012-02-15 | 2014-06-03 | Oracle International Corporation | Maintaining alignment in a multi-chip module using a compressible structure |
US9337138B1 (en) | 2012-03-09 | 2016-05-10 | Xilinx, Inc. | Capacitors within an interposer coupled to supply and ground planes of a substrate |
US8957512B2 (en) | 2012-06-19 | 2015-02-17 | Xilinx, Inc. | Oversized interposer |
US8869088B1 (en) | 2012-06-27 | 2014-10-21 | Xilinx, Inc. | Oversized interposer formed from a multi-pattern region mask |
US9026872B2 (en) | 2012-08-16 | 2015-05-05 | Xilinx, Inc. | Flexible sized die for use in multi-die integrated circuit |
US8659167B1 (en) * | 2012-08-29 | 2014-02-25 | Freescale Semiconductor, Inc. | Sensor packaging method and sensor packages |
US8872349B2 (en) | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
US9136236B2 (en) | 2012-09-28 | 2015-09-15 | Intel Corporation | Localized high density substrate routing |
US8912670B2 (en) | 2012-09-28 | 2014-12-16 | Intel Corporation | Bumpless build-up layer package including an integrated heat spreader |
US8963339B2 (en) | 2012-10-08 | 2015-02-24 | Qualcomm Incorporated | Stacked multi-chip integrated circuit package |
US20140131854A1 (en) * | 2012-11-13 | 2014-05-15 | Lsi Corporation | Multi-chip module connection by way of bridging blocks |
US9190380B2 (en) | 2012-12-06 | 2015-11-17 | Intel Corporation | High density substrate routing in BBUL package |
US9064705B2 (en) | 2012-12-13 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging with interposers |
US8866308B2 (en) * | 2012-12-20 | 2014-10-21 | Intel Corporation | High density interconnect device and method |
US9236366B2 (en) * | 2012-12-20 | 2016-01-12 | Intel Corporation | High density organic bridge device and method |
US9171798B2 (en) | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
MX346385B (es) * | 2013-02-14 | 2017-03-16 | Nanopareil Llc | Fieltros hibridos de nanofibras electrohiladas. |
EP2775523A1 (en) | 2013-03-04 | 2014-09-10 | Dialog Semiconductor GmbH | Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate |
US8901748B2 (en) * | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
US9646894B2 (en) | 2013-03-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US9070644B2 (en) * | 2013-03-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
DE102013106965B4 (de) * | 2013-03-15 | 2021-12-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiter-Die-Package und Verfahren zum Bilden desselben |
DE102013108106B4 (de) | 2013-03-15 | 2021-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verpackungsmechanismen für Chips mit Verbindern |
KR102029682B1 (ko) | 2013-03-15 | 2019-10-08 | 삼성전자주식회사 | 반도체 장치 및 반도체 패키지 |
US9844139B2 (en) | 2013-03-16 | 2017-12-12 | Indiana Integrated Circuits, LLC | Method of interconnecting microchips |
US9673131B2 (en) | 2013-04-09 | 2017-06-06 | Intel Corporation | Integrated circuit package assemblies including a glass solder mask layer |
US9147663B2 (en) * | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
US9607938B2 (en) * | 2013-06-27 | 2017-03-28 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof |
US9041205B2 (en) * | 2013-06-28 | 2015-05-26 | Intel Corporation | Reliable microstrip routing for electronics components |
US9547034B2 (en) | 2013-07-03 | 2017-01-17 | Xilinx, Inc. | Monolithic integrated circuit die having modular die regions stitched together |
US20150048515A1 (en) * | 2013-08-15 | 2015-02-19 | Chong Zhang | Fabrication of a substrate with an embedded die using projection patterning and associated package configurations |
US9159690B2 (en) | 2013-09-25 | 2015-10-13 | Intel Corporation | Tall solders for through-mold interconnect |
US9349703B2 (en) | 2013-09-25 | 2016-05-24 | Intel Corporation | Method for making high density substrate interconnect using inkjet printing |
US9508636B2 (en) | 2013-10-16 | 2016-11-29 | Intel Corporation | Integrated circuit package substrate |
US9209165B2 (en) * | 2013-10-21 | 2015-12-08 | Oracle International Corporation | Technique for controlling positions of stacked dies |
US9642259B2 (en) * | 2013-10-30 | 2017-05-02 | Qualcomm Incorporated | Embedded bridge structure in a substrate |
US9275955B2 (en) * | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
CN104730653B (zh) | 2013-12-23 | 2016-08-31 | 华为技术有限公司 | 光互连系统和方法 |
US9601456B2 (en) * | 2014-01-20 | 2017-03-21 | Etron Technology, Inc. | System-in-package module and manufacture method for a system-in-package module |
US10038259B2 (en) * | 2014-02-06 | 2018-07-31 | Xilinx, Inc. | Low insertion loss package pin structure and method |
KR101815489B1 (ko) | 2014-02-26 | 2018-01-05 | 인텔 코포레이션 | 스루 브리지 도전성 비아 신호 접속에 의한 임베딩된 멀티디바이스 브리지 |
US20150255411A1 (en) * | 2014-03-05 | 2015-09-10 | Omkar G. Karhade | Die-to-die bonding and associated package configurations |
US10121768B2 (en) | 2015-05-27 | 2018-11-06 | Bridge Semiconductor Corporation | Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same |
US10354984B2 (en) | 2015-05-27 | 2019-07-16 | Bridge Semiconductor Corporation | Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same |
US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
JP6434494B2 (ja) | 2014-03-10 | 2018-12-05 | 三菱重工業株式会社 | マルチチップモジュール、オンボードコンピュータ、センサインターフェース基板、及びマルチチップモジュール製造方法 |
DE102014003462B4 (de) * | 2014-03-11 | 2022-12-29 | Intel Corporation | Substrat-Routing mit lokaler hoher Dichte und Verfahren zum Herstellen einer entsprechenden Vorrichtung |
CN104952838B (zh) * | 2014-03-26 | 2019-09-17 | 英特尔公司 | 局部高密度基底布线 |
CN106463467B (zh) | 2014-06-16 | 2019-12-10 | 英特尔公司 | 不使用穿硅通孔(tsv)将存储器管芯直接集成到逻辑管芯的方法 |
US9915869B1 (en) | 2014-07-01 | 2018-03-13 | Xilinx, Inc. | Single mask set used for interposer fabrication of multiple products |
US9603247B2 (en) * | 2014-08-11 | 2017-03-21 | Intel Corporation | Electronic package with narrow-factor via including finish layer |
US9666559B2 (en) | 2014-09-05 | 2017-05-30 | Invensas Corporation | Multichip modules and methods of fabrication |
US9542522B2 (en) * | 2014-09-19 | 2017-01-10 | Intel Corporation | Interconnect routing configurations and associated techniques |
EP3195355B1 (en) | 2014-09-19 | 2020-11-25 | Intel Corporation | Semiconductor packages with embedded bridge interconnects |
DE102014118214B4 (de) | 2014-12-09 | 2024-02-22 | Snaptrack, Inc. | Einfach herstellbares elektrisches Bauelement und Verfahren zur Herstellung eines elektrischen Bauelements |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
CN104637909A (zh) * | 2015-01-30 | 2015-05-20 | 华进半导体封装先导技术研发中心有限公司 | 一种三维芯片集成结构及其加工工艺 |
US9379090B1 (en) * | 2015-02-13 | 2016-06-28 | Qualcomm Incorporated | System, apparatus, and method for split die interconnection |
KR20160103394A (ko) | 2015-02-24 | 2016-09-01 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
KR20180008379A (ko) * | 2015-03-11 | 2018-01-24 | 인텔 코포레이션 | 스트레인 재분배 층을 갖는 신장가능 전자 장치 제조 방법 |
US9418966B1 (en) * | 2015-03-23 | 2016-08-16 | Xilinx, Inc. | Semiconductor assembly having bridge module for die-to-die interconnection |
US10074630B2 (en) | 2015-04-14 | 2018-09-11 | Amkor Technology, Inc. | Semiconductor package with high routing density patch |
US9595494B2 (en) | 2015-05-04 | 2017-03-14 | Qualcomm Incorporated | Semiconductor package with high density die to die connection and method of making the same |
US9368450B1 (en) * | 2015-08-21 | 2016-06-14 | Qualcomm Incorporated | Integrated device package comprising bridge in litho-etchable layer |
KR20230020008A (ko) | 2015-08-28 | 2023-02-09 | 쇼와덴코머티리얼즈가부시끼가이샤 | 반도체 장치 및 그 제조 방법 |
US10410975B1 (en) | 2015-09-04 | 2019-09-10 | Microsemi Solutions (U.S.), Inc. | Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits |
US9761533B2 (en) * | 2015-10-16 | 2017-09-12 | Xilinx, Inc. | Interposer-less stack die interconnect |
US10438881B2 (en) * | 2015-10-29 | 2019-10-08 | Marvell World Trade Ltd. | Packaging arrangements including high density interconnect bridge |
WO2017074392A1 (en) | 2015-10-29 | 2017-05-04 | Intel Corporation | Metal-free frame design for silicon bridges for semiconductor packages |
US9971089B2 (en) | 2015-12-09 | 2018-05-15 | Intel Corporation | Chip-to-chip interconnect with embedded electro-optical bridge structures |
WO2017099788A1 (en) * | 2015-12-11 | 2017-06-15 | Intel Corporation | Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate |
DE112015007216T5 (de) * | 2015-12-22 | 2018-09-13 | Intel Corporation | Elektronische Baugruppen mit einer Brücke |
US9806014B2 (en) * | 2016-01-27 | 2017-10-31 | Advanced Micro Devices, Inc. | Interposer with beyond reticle field conductor pads |
TWI701782B (zh) * | 2016-01-27 | 2020-08-11 | 美商艾馬克科技公司 | 半導體封裝以及其製造方法 |
WO2017164810A1 (en) | 2016-03-21 | 2017-09-28 | Agency For Science, Technology And Research | Semiconductor package and method of forming the same |
JP6741063B2 (ja) | 2016-03-25 | 2020-08-19 | 日立化成株式会社 | 有機インターポーザ及び有機インターポーザの製造方法 |
KR101966328B1 (ko) * | 2016-03-29 | 2019-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US9721923B1 (en) | 2016-04-14 | 2017-08-01 | Micron Technology, Inc. | Semiconductor package with multiple coplanar interposers |
US10892219B2 (en) * | 2016-07-01 | 2021-01-12 | Intel Corporation | Molded embedded bridge for enhanced EMIB applications |
US11355427B2 (en) * | 2016-07-01 | 2022-06-07 | Intel Corporation | Device, method and system for providing recessed interconnect structures of a substrate |
US10177107B2 (en) | 2016-08-01 | 2019-01-08 | Xilinx, Inc. | Heterogeneous ball pattern package |
KR102549402B1 (ko) * | 2016-08-04 | 2023-06-28 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
KR102632563B1 (ko) | 2016-08-05 | 2024-02-02 | 삼성전자주식회사 | 반도체 패키지 |
EP3288076B1 (en) * | 2016-08-25 | 2021-06-23 | IMEC vzw | A semiconductor die package and method of producing the package |
CN109791916A (zh) | 2016-09-26 | 2019-05-21 | 日立化成株式会社 | 树脂组合物、半导体用配线层层叠体和半导体装置 |
US9978735B2 (en) | 2016-09-28 | 2018-05-22 | Altera Corporation | Interconnection of an embedded die |
WO2018063261A1 (en) | 2016-09-29 | 2018-04-05 | Qian Zhiguo | Die interconnect structures and methods |
WO2018063351A1 (en) * | 2016-09-30 | 2018-04-05 | Elsherbini Adel A | Semiconductor packaging with high density interconnects |
DE102016224747A1 (de) * | 2016-12-12 | 2018-06-14 | Robert Bosch Gmbh | Steuergerät |
KR20180070786A (ko) * | 2016-12-16 | 2018-06-27 | 삼성전자주식회사 | 반도체 패키지 |
US10109616B2 (en) * | 2016-12-22 | 2018-10-23 | Intel Corporation | High bandwidth, low profile multi-die package |
US11195806B2 (en) * | 2016-12-29 | 2021-12-07 | Intel Corporation | High frequency waveguide structure |
US20180240778A1 (en) * | 2017-02-22 | 2018-08-23 | Intel Corporation | Embedded multi-die interconnect bridge with improved power delivery |
US11742293B2 (en) * | 2017-03-22 | 2023-08-29 | Intel Corporation | Multiple die package using an embedded bridge connecting dies |
US11031341B2 (en) | 2017-03-29 | 2021-06-08 | Intel Corporation | Side mounted interconnect bridges |
WO2018182610A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Package architecture utilizing photoimageable dielectric (pid) for reduced bump pitch |
US10468374B2 (en) | 2017-03-31 | 2019-11-05 | Intel Corporation | Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate |
WO2018182658A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | A die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate |
US10134677B1 (en) | 2017-05-16 | 2018-11-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US11211345B2 (en) | 2017-06-19 | 2021-12-28 | Intel Corporation | In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same |
EP3688800A4 (en) * | 2017-09-29 | 2021-05-19 | INTEL Corporation | HORIZONTAL STEP SHIFTING USING INTEGRATED BRIDGE CHIPS |
US10886263B2 (en) | 2017-09-29 | 2021-01-05 | Advanced Semiconductor Engineering, Inc. | Stacked semiconductor package assemblies including double sided redistribution layers |
US10483156B2 (en) | 2017-11-29 | 2019-11-19 | International Business Machines Corporation | Non-embedded silicon bridge chip for multi-chip module |
US10784202B2 (en) | 2017-12-01 | 2020-09-22 | International Business Machines Corporation | High-density chip-to-chip interconnection with silicon bridge |
US11327259B2 (en) * | 2017-12-07 | 2022-05-10 | Intel Corporation | Integrated circuit package with electro-optical interconnect circuitry |
CN108091629B (zh) * | 2017-12-08 | 2020-01-10 | 华进半导体封装先导技术研发中心有限公司 | 一种光电芯片集成结构 |
US10651126B2 (en) | 2017-12-08 | 2020-05-12 | Applied Materials, Inc. | Methods and apparatus for wafer-level die bridge |
US10643945B2 (en) * | 2017-12-28 | 2020-05-05 | Intel Corporation | Pitch translation architecture for semiconductor package including embedded interconnect bridge |
DE112017008326T5 (de) | 2017-12-29 | 2020-10-08 | Intel Corporation | Mikroelektronische Anordnungen |
US11569173B2 (en) * | 2017-12-29 | 2023-01-31 | Intel Corporation | Bridge hub tiling architecture |
DE112017008336T5 (de) | 2017-12-29 | 2020-09-17 | Intel Corporation | Mikroelektronische Anordnungen |
DE112017008327T5 (de) | 2017-12-29 | 2020-10-08 | Intel Corporation | Mikroelektronische anordnungen |
US11494682B2 (en) | 2017-12-29 | 2022-11-08 | Intel Corporation | Quantum computing assemblies |
US10741532B2 (en) | 2018-03-12 | 2020-08-11 | International Business Machines Corporation | Multi-chip modules |
US10580738B2 (en) * | 2018-03-20 | 2020-03-03 | International Business Machines Corporation | Direct bonded heterogeneous integration packaging structures |
KR102066721B1 (ko) * | 2018-03-23 | 2020-01-16 | 주식회사 웨이브피아 | 큐에프엔 알에프 칩 패키지 |
US10490503B2 (en) | 2018-03-27 | 2019-11-26 | Intel Corporation | Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same |
US10796999B2 (en) * | 2018-03-30 | 2020-10-06 | Intel Corporation | Floating-bridge interconnects and methods of assembling same |
US10515869B1 (en) * | 2018-05-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure having a multi-thermal interface material structure |
US10438894B1 (en) | 2018-05-30 | 2019-10-08 | Globalfoundries Inc. | Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devices |
US11469206B2 (en) | 2018-06-14 | 2022-10-11 | Intel Corporation | Microelectronic assemblies |
WO2020010265A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US10535608B1 (en) | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
KR102530320B1 (ko) * | 2018-11-21 | 2023-05-09 | 삼성전자주식회사 | 반도체 패키지 |
KR102538704B1 (ko) * | 2018-12-04 | 2023-06-01 | 에스케이하이닉스 주식회사 | 플렉시블 브리지 다이를 포함한 스택 패키지 |
US10916507B2 (en) * | 2018-12-04 | 2021-02-09 | International Business Machines Corporation | Multiple chip carrier for bridge assembly |
CN111372369B (zh) | 2018-12-25 | 2023-07-07 | 奥特斯科技(重庆)有限公司 | 具有部件屏蔽的部件承载件及其制造方法 |
US11652060B2 (en) * | 2018-12-28 | 2023-05-16 | Intel Corporation | Die interconnection scheme for providing a high yielding process for high performance microprocessors |
US10833051B2 (en) | 2019-01-24 | 2020-11-10 | International Business Machines Corporation | Precision alignment of multi-chip high density interconnects |
US11209598B2 (en) * | 2019-02-28 | 2021-12-28 | International Business Machines Corporation | Photonics package with face-to-face bonding |
RU2705229C1 (ru) * | 2019-03-05 | 2019-11-06 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Петрозаводский государственный университет" | Способ трехмерного многокристального корпусирования интегральных микросхем памяти |
KR102644598B1 (ko) | 2019-03-25 | 2024-03-07 | 삼성전자주식회사 | 반도체 패키지 |
US10879155B2 (en) * | 2019-05-09 | 2020-12-29 | Texas Instruments Incorporated | Electronic device with double-sided cooling |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US10991635B2 (en) | 2019-07-20 | 2021-04-27 | International Business Machines Corporation | Multiple chip bridge connector |
US11094654B2 (en) | 2019-08-02 | 2021-08-17 | Powertech Technology Inc. | Package structure and method of manufacturing the same |
KR20210019308A (ko) | 2019-08-12 | 2021-02-22 | 삼성전자주식회사 | 반도체 패키지 |
US10957650B2 (en) * | 2019-08-21 | 2021-03-23 | International Business Machines Corporation | Bridge support structure |
US11270946B2 (en) | 2019-08-30 | 2022-03-08 | Stmicroelectronics Pte Ltd | Package with electrical interconnection bridge |
US11410894B2 (en) | 2019-09-06 | 2022-08-09 | International Business Machines Corporation | Polygon integrated circuit (IC) packaging |
KR20210029422A (ko) * | 2019-09-06 | 2021-03-16 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐층을 포함하는 반도체 패키지 |
US11257776B2 (en) * | 2019-09-17 | 2022-02-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11393759B2 (en) | 2019-10-04 | 2022-07-19 | International Business Machines Corporation | Alignment carrier for interconnect bridge assembly |
US11164817B2 (en) | 2019-11-01 | 2021-11-02 | International Business Machines Corporation | Multi-chip package structures with discrete redistribution layers |
US11094637B2 (en) | 2019-11-06 | 2021-08-17 | International Business Machines Corporation | Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers |
US11171105B2 (en) * | 2019-11-13 | 2021-11-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method of the same |
US11101191B2 (en) * | 2019-11-22 | 2021-08-24 | International Business Machines Corporation | Laminated circuitry cooling for inter-chip bridges |
TWI726500B (zh) * | 2019-11-25 | 2021-05-01 | 東捷科技股份有限公司 | 封裝結構的製造方法 |
US11171006B2 (en) | 2019-12-04 | 2021-11-09 | International Business Machines Corporation | Simultaneous plating of varying size features on semiconductor substrate |
US11239167B2 (en) | 2019-12-04 | 2022-02-01 | International Business Machines Corporation | Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate |
KR20210072939A (ko) | 2019-12-10 | 2021-06-18 | 삼성전기주식회사 | 패키지 기판 및 이를 포함하는 멀티 칩 패키지 |
US11133259B2 (en) | 2019-12-12 | 2021-09-28 | International Business Machines Corporation | Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network |
US11302644B2 (en) * | 2019-12-31 | 2022-04-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US11315902B2 (en) * | 2020-02-12 | 2022-04-26 | International Business Machines Corporation | High bandwidth multichip module |
US11367103B2 (en) * | 2020-03-02 | 2022-06-21 | Yieldmo, Inc. | Method for modeling digital advertisement consumption |
US20210305133A1 (en) * | 2020-03-24 | 2021-09-30 | Intel Coporation | Open cavity bridge power delivery architectures and processes |
CN111554623A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554656A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
CN111554657B (zh) * | 2020-04-30 | 2023-07-14 | 通富微电子股份有限公司 | 一种半导体封装器件 |
JP2023527290A (ja) | 2020-05-20 | 2023-06-28 | エフ. ホフマン-ラ ロシュ アーゲー | 露出可能なクラウドベースのレジストリを使用した治療のためのインテリジェントなワークフロー分析 |
US20210375845A1 (en) * | 2020-05-27 | 2021-12-02 | Qualcomm Incorporated | Package cavity for enhanced device performance with an integrated passive device |
CN113766731A (zh) * | 2020-06-02 | 2021-12-07 | 苏州旭创科技有限公司 | 一种电路板组件的组装方法 |
US11923307B2 (en) | 2020-06-16 | 2024-03-05 | Intel Corporation | Microelectronic structures including bridges |
US11804441B2 (en) | 2020-06-16 | 2023-10-31 | Intel Corporation | Microelectronic structures including bridges |
US11791274B2 (en) | 2020-06-16 | 2023-10-17 | Intel Corporation | Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects |
US11373972B2 (en) | 2020-06-16 | 2022-06-28 | Intel Corporation | Microelectronic structures including bridges |
US11887962B2 (en) * | 2020-06-16 | 2024-01-30 | Intel Corporation | Microelectronic structures including bridges |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
TWI722959B (zh) | 2020-08-20 | 2021-03-21 | 欣興電子股份有限公司 | 晶片封裝結構 |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
CN112201647A (zh) * | 2020-09-09 | 2021-01-08 | 苏州通富超威半导体有限公司 | 一种高密度互连芯片结构 |
WO2022070389A1 (ja) | 2020-10-01 | 2022-04-07 | 昭和電工マテリアルズ株式会社 | 配線基板の製造方法、半導体装置の製造方法、及び樹脂シート |
CN112490209A (zh) * | 2020-11-25 | 2021-03-12 | 通富微电子股份有限公司 | 一种半导体封装器件 |
CN112490212A (zh) * | 2020-11-25 | 2021-03-12 | 通富微电子股份有限公司 | 多芯片封装器件 |
WO2022153433A1 (ja) | 2021-01-14 | 2022-07-21 | 昭和電工マテリアルズ株式会社 | 配線層付き基板の製造方法、配線層付き基板、半導体装置の製造方法、及び、半導体装置 |
US11842935B2 (en) | 2021-02-18 | 2023-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a reconstructed package substrate comprising substrates blocks |
US20220310518A1 (en) * | 2021-03-25 | 2022-09-29 | Intel Corporation | Embedded bridge architecture with thinned surface |
CN116670824A (zh) * | 2021-03-26 | 2023-08-29 | 华为技术有限公司 | 多芯片模组及具有该多芯片模组的电子设备 |
US11791270B2 (en) * | 2021-05-10 | 2023-10-17 | International Business Machines Corporation | Direct bonded heterogeneous integration silicon bridge |
CN117296144A (zh) | 2021-05-21 | 2023-12-26 | 株式会社力森诺科 | 半导体装置的制造方法及半导体装置 |
US11735575B2 (en) | 2021-05-27 | 2023-08-22 | International Business Machines Corporation | Bonding of bridge to multiple semiconductor chips |
US20230035627A1 (en) * | 2021-07-27 | 2023-02-02 | Qualcomm Incorporated | Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods |
US11791434B2 (en) * | 2021-11-09 | 2023-10-17 | Advanced Semiconductor Engineering, Inc. | Electronic package, optoelectronic package and method of manufacturing the same |
Family Cites Families (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2582013B2 (ja) * | 1991-02-08 | 1997-02-19 | 株式会社東芝 | 樹脂封止型半導体装置及びその製造方法 |
JPH0719970B2 (ja) * | 1988-05-09 | 1995-03-06 | 日本電気株式会社 | 多層印刷配線板の製造方法 |
SU1691912A1 (ru) * | 1989-02-10 | 1991-11-15 | Войсковая часть 67947 | Корпус дл двухкристальной интегральной схемы |
JPH0364060A (ja) * | 1989-08-02 | 1991-03-19 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5198963A (en) * | 1991-11-21 | 1993-03-30 | Motorola, Inc. | Multiple integrated circuit module which simplifies handling and testing |
JPH07302859A (ja) * | 1994-04-29 | 1995-11-14 | Ibiden Co Ltd | 半導体チップ搭載用多層配線基板の製造方法及び半導体チップ搭載装置の製造方法 |
US5608262A (en) * | 1995-02-24 | 1997-03-04 | Lucent Technologies Inc. | Packaging multi-chip modules without wire-bond interconnection |
KR970013137A (ko) * | 1995-08-30 | 1997-03-29 | 김광호 | 칩 캐비티(cavity)가 형성된 멀티칩 패키지의 제조방법 |
US5760478A (en) * | 1996-08-20 | 1998-06-02 | International Business Machines Corporation | Clock skew minimization system and method for integrated circuits |
JPH10303363A (ja) * | 1997-04-30 | 1998-11-13 | Sony Corp | 電子部品及びその製造方法 |
JPH11289047A (ja) | 1998-04-02 | 1999-10-19 | Hitachi Ltd | マルチチップモジュールおよびその製造方法 |
US6369444B1 (en) | 1998-05-19 | 2002-04-09 | Agere Systems Guardian Corp. | Packaging silicon on silicon multichip modules |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
JP2000100851A (ja) | 1998-09-25 | 2000-04-07 | Sony Corp | 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法 |
JP2001044654A (ja) | 1999-07-26 | 2001-02-16 | Sumitomo Wiring Syst Ltd | 電気接続箱 |
JP2001176928A (ja) | 1999-12-20 | 2001-06-29 | Nec Corp | 半導体装置 |
US6731009B1 (en) | 2000-03-20 | 2004-05-04 | Cypress Semiconductor Corporation | Multi-die assembly |
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
JP3511982B2 (ja) * | 2000-06-14 | 2004-03-29 | 株式会社村田製作所 | 多層配線基板の製造方法 |
JP3650001B2 (ja) * | 2000-07-05 | 2005-05-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
JP2002359345A (ja) * | 2001-03-30 | 2002-12-13 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003124431A (ja) | 2001-10-17 | 2003-04-25 | Sony Corp | ウェーハ状シート、チップ状電子部品、およびそれらの製造方法 |
US20030197285A1 (en) | 2002-04-23 | 2003-10-23 | Kulicke & Soffa Investments, Inc. | High density substrate for the packaging of integrated circuits |
JP2003324183A (ja) | 2002-05-07 | 2003-11-14 | Mitsubishi Electric Corp | 半導体装置 |
US6906415B2 (en) * | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
US6659512B1 (en) * | 2002-07-18 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Integrated circuit package employing flip-chip technology and method of assembly |
JP4380130B2 (ja) * | 2002-09-13 | 2009-12-09 | ソニー株式会社 | 半導体装置 |
US20040201970A1 (en) | 2003-04-10 | 2004-10-14 | International Business Machines Corporation | Chip interconnection method and apparatus |
US6873040B2 (en) * | 2003-07-08 | 2005-03-29 | Texas Instruments Incorporated | Semiconductor packages for enhanced number of terminals, speed and power performance |
TWI229434B (en) * | 2003-08-25 | 2005-03-11 | Advanced Semiconductor Eng | Flip chip stacked package |
JP3891297B2 (ja) | 2003-10-02 | 2007-03-14 | セイコーエプソン株式会社 | 半導体装置製造用治具 |
US7098542B1 (en) * | 2003-11-07 | 2006-08-29 | Xilinx, Inc. | Multi-chip configuration to connect flip-chips to flip-chips |
US7061121B2 (en) | 2003-11-12 | 2006-06-13 | Tessera, Inc. | Stacked microelectronic assemblies with central contacts |
DE102004013681B3 (de) * | 2004-03-18 | 2005-11-17 | Infineon Technologies Ag | Halbleitermodul mit einem Kopplungssubstrat und Verfahren zur Herstellung desselben |
CN100511672C (zh) | 2004-03-25 | 2009-07-08 | 日本电气株式会社 | 芯片层叠型半导体装置 |
US20050230842A1 (en) * | 2004-04-20 | 2005-10-20 | Texas Instruments Incorporated | Multi-chip flip package with substrate for inter-die coupling |
US7525199B1 (en) * | 2004-05-21 | 2009-04-28 | Sun Microsystems, Inc | Packaging for proximity communication positioned integrated circuits |
JP4865197B2 (ja) | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI425604B (zh) | 2004-07-26 | 2014-02-01 | Rambus Inc | 半導體裝置 |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
US7763963B2 (en) * | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
US7994619B2 (en) | 2005-11-01 | 2011-08-09 | Stats Chippac Ltd. | Bridge stack integrated circuit package system |
JP4559993B2 (ja) | 2006-03-29 | 2010-10-13 | 株式会社東芝 | 半導体装置の製造方法 |
JP4742938B2 (ja) * | 2006-03-29 | 2011-08-10 | エプソントヨコム株式会社 | 圧電デバイス及びその製造方法 |
JP4858692B2 (ja) * | 2006-06-22 | 2012-01-18 | 日本電気株式会社 | チップ積層型半導体装置 |
US7554203B2 (en) * | 2006-06-30 | 2009-06-30 | Intel Corporation | Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture |
US20080088030A1 (en) * | 2006-10-16 | 2008-04-17 | Formfactor, Inc. | Attaching and interconnecting dies to a substrate |
JP5559452B2 (ja) * | 2006-12-20 | 2014-07-23 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP2008187050A (ja) * | 2007-01-30 | 2008-08-14 | Toshiba Corp | システムインパッケージ装置 |
US8237289B2 (en) * | 2007-01-30 | 2012-08-07 | Kabushiki Kaisha Toshiba | System in package device |
US8064224B2 (en) | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
TW201041105A (en) | 2009-05-13 | 2010-11-16 | Advanced Semiconductor Eng | Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
JP2011044654A (ja) | 2009-08-24 | 2011-03-03 | Shinko Electric Ind Co Ltd | 半導体装置 |
US9236366B2 (en) * | 2012-12-20 | 2016-01-12 | Intel Corporation | High density organic bridge device and method |
US9177903B2 (en) * | 2013-03-29 | 2015-11-03 | Stmicroelectronics, Inc. | Enhanced flip-chip die architecture |
US10163798B1 (en) * | 2017-12-22 | 2018-12-25 | Intel Corporation | Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same |
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