TWI455265B - 具微機電元件之封裝結構及其製法 - Google Patents
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Description
本發明係有關於一種封裝結構及其製法,尤指一種具微機電元件之封裝結構及其製法。
微機電系統(Micro Electro Mechanical System,簡稱MEMS)是一種兼具電子與機械功能的微小裝置,在製造上則藉由各種微細加工技術來達成,其係將微機電元件設置於基板的表面上,並以保護罩或底膠進行封裝保護,俾使內部之微機電元件不受外界環境的破壞,而得到一具微機電元件之封裝結構。
請參閱第1圖,係習知具微機電元件之封裝結構之剖視圖。如圖所示,習知之具微機電元件之封裝結構係將例如為壓力感測元件的微機電元件11接置於平面柵格陣列(land grid array,簡稱LGA)型態之基板10上,並利用打線方式從微機電元件11之電性連接端111電性連接至該LGA基板10之電性連接端101,而使該微機電元件11與基板10電性連接,最終再於封裝基板10表面形成金屬蓋12,以將該微機電元件11包覆於其中,而該金屬蓋12係用以保護該微機電元件11不受外界環境之污染破壞,而該微機電元件封裝結構之缺點為體積過大,無法符合終端產品輕薄短小之需求。
請參閱第2圖,故為了縮小具微機電壓力感測元件之整體封裝結構體積,FINEMEMS公司於西元2005年申請一晶圓級壓力感測封裝結構之專利案(公開號為US 2006/0185429),該封裝結構係將例如為壓力感測元件的微機電元件11直接製作於矽基板13上,最後並於該微機電元件11上接合玻璃蓋體14。
惟,於該矽基板13中形成感測腔體131及貫通矽基板13兩表面之通孔132,因此需要使用矽貫孔(Through Silicon Via,簡稱TSV)技術,而該技術係應用氫氧化鉀(KOH)作為蝕刻劑以形成通孔或凹槽。
相較於前述第一種習知技術結構,第2006/0185429號專利案所揭示之結構雖可大幅縮小具微機電元件之封裝結構之整體體積,但是以TSV技術形成通孔及凹槽所花費的成本相當昂貴。
遂而如第3C圖所示,現今MEMS產業更演進至藉由銲線221提供矽基板20上之微機電感測元件202之電性連接路徑至封裝結構表面,如此不僅能製作出體積大幅縮小的具微機電元件之封裝結構,且不需使用TSV技術,使製作成本大幅降低。
惟,請參閱第3A至3C圖之習知具微機電元件之封裝結構及其製法之剖視圖,此第三種習知技術結構之製法需先以複數條銲線22電性連接矽封蓋21與該矽基板20上之電性連接墊201,之後再以封裝層23包覆該矽封蓋21及銲線22,藉以保護該銲線22不受外界環境破壞,之後再以研磨製程移除部份該封裝層23與銲線22,以露出銲線221之一端,此時容易產生所露出銲線221之一端位置不一致的問題,這是因為該銲線221之外露一端位置乃取決於該銲線22的打線弧度及打線高度,其兩者的掌控須非常精確,方能使該銲線221之外露一端位置保持一致。
因此,如何避免上述習知技術中之種種問題,使具微機電元件之封裝結構所外露銲線之一端位置較一致,並降低製作成本,實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失,本發明提供一種具微機電元件之封裝結構,係包括:微機電元件,具有複數電性接點;封裝層,係包覆該微機電元件與其電性接點,且該微機電元件之底面外露於該封裝層之下表面;複數銲線,係嵌設於該封裝層中,且各該銲線之一端連接該微機電元件之電性接點,而另一端外露於該封裝層之下表面;以及增層結構,係設於該封裝層之下表面上,該增層結構係包括至少一介電層、及複數形成於該介電層中並電性連接該銲線一端之導電盲孔。
本發明復揭露一種具微機電元件之封裝結構之製法,係包括:於一具有相對第一表面與第二表面之承載板之第一表面上設置複數微機電元件,各該微機電元件具有複數電性接點;以複數銲線連接該電性接點與承載板之第一表面;於該承載板之第一表面上形成封裝層,以包覆該微機電元件、電性接點與銲線;移除該承載板,以外露該銲線之一端;以及於外露該銲線的封裝層表面上形成增層結構,該增層結構係包括至少一介電層、及複數形成於該介電層中並電性連接該銲線一端之導電盲孔。
由上可知,本發明之具微機電元件之封裝結構係先以銲線電性連接至微機電元件,接著以封裝層包覆該銲線與微機電元件,並移除承載版以使該銲線之一端外露,且利用該銲線之外露端以電性連接至外界。由於本發明銲線外露端的位置較容易控制,且本發明之製法也與現行之線路增層的流程相容性高,而有利於整體成本的降低。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上、下”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第一實施例
請參閱第4A至4G圖,係本發明之具微機電元件之封裝結構及其製法的第一實施例之剖視圖,其中,第4B’與4C’圖分別係第4B與4C圖之俯視圖,第4G’圖係第4G圖之另一實施態樣。
首先,如第4A圖所示,準備一具有相對第一表面30a與第二表面30b之承載板30,該承載板30係可包括一基材301及貼附其上的黏著層302,且該黏著層302之外露表面為該第一表面30a,該基材301之外露表面為該第二表面30b,其中,該基材301可為含矽之材質。
如第4B與4B’圖所示,於該承載板30之第一表面30a上設置複數微機電元件31,各該微機電元件31具有複數設於頂面之電性接點32,該微機電元件31可為陀螺儀(gyroscope)、加速度計(accelerometer)或射頻微機電(RF MEMS)元件等。
另外要注意的是,該微機電元件31另可具有設於其上的蓋體(未圖示),以作為保護之用。
如第4C與4C’圖所示,以複數銲線33連接該電性接點32與承載板30之第一表面30a,藉由該基材301上之黏著層302固定銲線33之一端,使其不偏移。
如第4D圖所示,之後於該承載板30之第一表面30a上形成封裝層34,以包覆該微機電元件31、電性接點32與銲線33。
如第4E圖所示,移除該承載板30,以外露該銲線33之一端,其中,移除該承載板30(使黏著層302與其上之結構分離)之方式可為照光、加熱、蝕刻或研磨(lapping)。
如第4F圖所示,於外露該銲線33的封裝層34表面上形成增層結構35,該增層結構35係包括至少一介電層351、及複數形成於該介電層351中並電性連接該銲線33一端之導電盲孔353,且於該增層結構35上形成防銲層36,該防銲層36中形成有複數防銲層開孔360,以令各該導電盲孔353之部分表面外露於對應之該防焊層開孔360,再於各該防焊層開孔360中外露之導電盲孔353上植接銲球37。
要注意的是,第4F圖所示之實施態樣係將對外電性連接之銲球37直接設置於連接該銲線33外露位置處的導電盲孔353上;然而,於其他實施態樣中,該增層結構35復可包括形成於該至少一介電層351上之線路層352(請先參考第4G’圖),且該導電盲孔353電性連接該線路層352與銲線33一端,並令該線路層352之部分表面(例如,非導電盲孔353端之表面)外露於該防焊層開孔360,亦即先藉由該線路層352將該銲線33一端向外扇出(fan out),再於各該防焊層開孔360中外露之線路層352上植接銲球37(請先參考第4G’圖),上述之態樣係本發明所屬技術領域之通常知識者能輕易了解,故在此不加以贅述。
如第4G圖所示,進行切單製程,以得到複數個具微機電元件之封裝結構。
如第4G’圖所示,其係為於外露該銲線33的封裝層34表面上形成增層結構35之另一實施態樣,其中該增層結構35復包括形成於該至少一介電層351上之線路層352,且該導電盲孔353電性連接該線路層352與銲線33一端,如此以完成線路重佈(Redistribution Line,簡稱RDL)製程。
第二實施例
請參閱第5A至5D圖,係本發明之具微機電元件之封裝結構及其製法的第二實施例之剖視圖。
本實施例大致與前一實施例相同,主要不同之處在於:本實施例之承載板30係單一材質所構成,且該承載板30之材質係為金屬,其中該金屬係以鋁為較佳,如此,該銲線33之一端即可與金屬材質之承載板30接著固定而不會偏移,其餘可類推適用第一實施例,故在此不加以贅述。
本發明復揭露一種具微機電元件之封裝結構,係包括:微機電元件31,具有複數電性接點32;封裝層34,係包覆該微機電元件31與其電性接點32,且該微機電元件31之底面310外露於該封裝層34之下表面340;複數銲線33,係嵌設於該封裝層34中,且各該銲線33之一端連接該微機電元件31之電性接點32,而另一端外露於該封裝層34之下表面340;以及增層結構35,係設於該封裝層34之下表面340上,該增層結構35係包括至少一介電層351、及複數形成於該介電層351中並電性連接該銲線33一端之導電盲孔353。
於上述之具微機電元件之封裝結構中,復可包括防銲層36,係設於該增層結構35上,該防銲層36中形成有複數防銲層開孔360,以令各該導電盲孔353之部分表面外露於對應之該防焊層開孔360。
又於前述之封裝結構中,該增層結構35復可包括形成於該至少一介電層351上之線路層,且該導電盲孔353電性連接該線路層與銲線33一端,又復可包括防銲層36,係設於該增層結構35上,該防銲層36中形成有複數防銲層開孔360,以令各該線路層之部分表面外露於對應之該防焊層開孔360。
於所述之具微機電元件之封裝結構中,復可包括銲球37,係設於各該防焊層開孔360中外露之線路層上。
所述之具微機電元件之封裝結構中,該微機電元件31可為陀螺儀、加速度計或射頻微機電元件。
綜上所述,本發明之具微機電元件之封裝結構係先以銲線電性連接至微機電元件,接著以封裝層包覆該銲線與微機電元件,並移除承載版以外露出該銲線之一端,且利用該銲線之一端以電性連接至外界。相較於習知技術,由於本發明銲線外露端的位置容易控制,所以容易控制整體的精度與良率;此外,本發明之製法也與現行之線路增層的流程相容性高,而有利於整體成本的降低。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
10...基板
11、31...微機電元件
101、111...電性連接端
12...金屬蓋
13、20...矽基板
131...感測腔體
132...通孔
14...玻璃蓋體
202...微機電感測元件
22、221、33...銲線
21...矽封蓋
201...電性連接墊
23、34...封裝層
30...承載板
30a...第一表面
30b...第二表面
301...基材
302...黏著層
32...電性接點
35...增層結構
351...介電層
352...線路層
353...導電盲孔
36...防銲層
360...防銲層開孔
37...銲球
310...底面
340...下表面
第1圖係一種習知具微機電元件之封裝結構之剖視圖;
第2圖係另一種習知具微機電元件之封裝結構之剖視圖;
第3A至3C圖係又一種習知具微機電元件之封裝結構及其製法之剖視圖;
第4A至4G圖係本發明之具微機電元件之封裝結構及其製法的第一實施例之剖視圖,其中,第4B’與4C’圖分別係第4B與4C圖之俯視圖,第4G’圖係第4G圖之另一實施態樣;以及
第5A至5D圖係本發明之具微機電元件之封裝結構及其製法的第二實施例之剖視圖。
31...微機電元件
310...底面
32...電性接點
33...銲線
34...封裝層
340...下表面
35...增層結構
351...介電層
353...導電盲孔
36...防銲層
360...防銲層開孔
37...銲球
Claims (20)
- 一種具微機電元件之封裝結構,係包括:微機電元件,具有複數電性接點;封裝層,係包覆該微機電元件與其電性接點,且該微機電元件之底面外露於該封裝層之下表面;複數銲線,係嵌設於該封裝層中,且各該銲線之一端連接該微機電元件之電性接點,而另一端外露於該封裝層之下表面;以及增層結構,係設於該封裝層之下表面上,該增層結構係包括至少一介電層、及複數形成於該介電層中並電性連接該銲線一端之導電盲孔。
- 如申請專利範圍第1項所述之具微機電元件之封裝結構,復包括防銲層,係設於該增層結構上,該防銲層中形成有複數防銲層開孔,以令各該導電盲孔之部分表面外露於對應之該防焊層開孔。
- 如申請專利範圍第2項所述之具微機電元件之封裝結構,復包括銲球,係設於各該防焊層開孔中外露之導電盲孔上。
- 如申請專利範圍第1項所述之具微機電元件之封裝結構,其中,該增層結構復包括形成於該至少一介電層上之線路層,且該導電盲孔電性連接該線路層與銲線一端。
- 如申請專利範圍第4項所述之具微機電元件之封裝結構,復包括防銲層,係設於該增層結構上,該防銲層中形成有複數防銲層開孔,以令該線路層之部分表面外露於該防焊層開孔。
- 如申請專利範圍第5項所述之具微機電元件之封裝結構,復包括銲球,係設於各該防焊層開孔中外露之線路層上。
- 如申請專利範圍第1項所述之具微機電元件之封裝結構,其中,該微機電元件為陀螺儀、加速度計或射頻微機電元件。
- 一種具微機電元件之封裝結構之製法,係包括:於一具有相對第一表面與第二表面之承載板之第一表面上設置複數微機電元件,各該微機電元件具有複數電性接點;以複數銲線連接該電性接點與承載板之第一表面;於該承載板之第一表面上形成封裝層,以包覆該微機電元件、電性接點與銲線;移除該承載板,以外露該銲線之一端;以及於外露該銲線的封裝層表面上形成增層結構,該增層結構係包括至少一介電層、及複數形成於該介電層中並電性連接該銲線一端之導電盲孔。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,其中,該承載板係包括一基材及貼附其上的黏著層,且該黏著層之外露表面為該第一表面,該基材之外露表面為該第二表面。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,復於該增層結構上形成包括防銲層,該防銲層中形成有複數防銲層開孔,以令各該導電盲孔之部分表面外露於對應之該防焊層開孔。
- 如申請專利範圍第10項所述之具微機電元件之封裝結構之製法,復包括銲球,係形成於各該防焊層開孔中外露之導電盲孔上。
- 如申請專利範圍第11項所述之具微機電元件之封裝結構之製法,復包括進行切單製程,以得到複數個具微機電元件之封裝結構。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,其中,該增層結構復包括形成於該至少一介電層上之線路層,且該導電盲孔電性連接該線路層與銲線一端。
- 如申請專利範圍第13項所述之具微機電元件之封裝結構之製法,復包括於該增層結構上形成防銲層,該防銲層中具有複數防銲層開孔,以令該線路層之部分表面外露於該防焊層開孔。
- 如申請專利範圍第14項所述之具微機電元件之封裝結構之製法,復包括於各該防焊層開孔中外露之線路層上植接銲球。
- 如申請專利範圍第15項所述之具微機電元件之封裝結構之製法,復包括進行切單製程,以得到複數個具微機電元件之封裝結構。
- 如申請專利範圍第9項所述之具微機電元件之封裝結構之製法,其中,該基材為含矽之材質。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,其中,該承載板之材質係鋁。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,其中,移除該承載板之方式係照光、加熱、蝕刻或研磨。
- 如申請專利範圍第8項所述之具微機電元件之封裝結構之製法,其中,該微機電元件為陀螺儀、加速度計或射頻微機電元件。
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US8741693B2 (en) | 2014-06-03 |
US20120104517A1 (en) | 2012-05-03 |
US8610272B2 (en) | 2013-12-17 |
US20140080242A1 (en) | 2014-03-20 |
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