TWI455279B - 多晶片封裝及提供多晶片封裝中之晶粒至晶粒互連之方法 - Google Patents

多晶片封裝及提供多晶片封裝中之晶粒至晶粒互連之方法 Download PDF

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TWI455279B
TWI455279B TW099109406A TW99109406A TWI455279B TW I455279 B TWI455279 B TW I455279B TW 099109406 A TW099109406 A TW 099109406A TW 99109406 A TW99109406 A TW 99109406A TW I455279 B TWI455279 B TW I455279B
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Taiwan
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die
substrate
bridge
active
attached
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TW099109406A
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English (en)
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TW201121025A (en
Inventor
Henning Braunisch
Chia-Pin Chiu
Aleksandar Aleksov
Hinmeng Au
Stefanie M Lotz
Johanna M Swan
Sujit Sharan
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Intel Corp
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Publication of TW201121025A publication Critical patent/TW201121025A/zh
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Publication of TWI455279B publication Critical patent/TWI455279B/zh

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Description

多晶片封裝及提供多晶片封裝中之晶粒至晶粒互連之方法
本發明之揭示的實施例大致有關多晶片封裝，且更特別地，有關該等封裝中的互連結構。
微電子產業的持續焦點係具有更大密度，更高性能，及更低成本之電腦晶片(亦稱為晶粒)的致能。做為此努力之部分，已發展出包含多晶粒的微電子封裝。該等多晶片封裝(MCP)以降低的成本來提供增加之架構彈性的潛能，但為達成此，則必須以成本有效的方式來提供適當的晶粒至晶粒互連密度。互連密度係重要的考慮，因為不足之晶粒連接的數目將限制受影響之晶粒介面的帶寬能力，且因此，邏輯-邏輯及/或邏輯-記憶體通訊將遭受損失。
 【發明內容及實施方式】
針對描繪之簡單性和透澈性，圖式將描繪結構的通用方式，且熟知之特性和技術的說明和細節可能被省略，以避免不必要地混淆本發明所述實施例的解說。此外，在圖式中之元件未必繪製成比例。例如，為協助改善本發明實施例之瞭解，在圖式中之若干元件的尺寸會相對於其他元件而被誇大。在不同圖式中之相同的參考符號表示相同的元件，而相似的參考符號可表示，但未必一定表示相似的元件。
若有的話，在說明書中及在申請專利範圍中之〝第一〞、〝第二〞、〝第三〞、〝第四〞、及其類似者的用語係使用於相似元件之間的區別，且未必一定用以敘述特定順序或按時間先後之次序。應瞭解的是，所使用之該等用語可在適當的情況下互換，使得此處所敘述之本發明的實施例能以例如除了在此所描繪或所敘述的該等順序之外的順序操作。同樣地，若方法係在此敘述成為包含一連串的步驟時，則如此處所呈現之該等步驟的順序無需一定係其中可執行該等步驟的唯一順序，且若干所陳述的步驟可予以省略及/或若干未被敘述於此的其他步驟可予以添加至方法。再者，〝包括〞、〝包含〞、〝具有〞、及其任何變化者的用語係打算涵蓋非唯一之包含，使得包括元件列之處理、方法、物品、或設備無需受限於該等元件，而是可包含未被明確表列或固有於該處理、方法、物品、或設備的其他元件。
若有的話，在說明書中及在申請專利範圍中之〝左邊〞、〝右邊〞、〝正面〞、〝背面〞、〝頂部〞、〝底部〞、〝在…之上〞、〝在…之下〞、及其類似者的用語係使用於描繪性之目的，且未必一定用以敘述永久的相對位置。應瞭解的是，所使用之該等用語可在適當的情況下互換，使得此處所敘述之本發明的實施例能以例如除了在此所描繪或所敘述的該等取向之外的取向操作。如在此所使用之〝耦接〞的用語係定義成為以電性或非電性之方式直接地或間接地連接。此處敘述成為相互〝毗鄰〞之物體可針對其中使用該用語之情況而為彼此相互實體接觸、彼此相互極為接近、或在彼此大致相同的地區或區域中。此處之〝在一實施例中〞的用語之出現無需一定均述及同一實施例。
在本發明之一實施例中，多晶片封裝包含：基板，其具有第一側、相對的第二側、及第三側，該第三側自第一側延伸至第二側；第一晶粒，係附著至基板之第一側，及第二晶粒，亦係附著至基板之第一側；以及橋接器，係毗鄰基板之第三側且附著至第一晶粒及至第二晶粒。基板並不具有在橋接器之下面的部分。橋接器產生連接於第一晶粒與第二晶粒之間。選擇性地，橋接器可設置於基板中的空穴之中或在基板與晶粒層之間。橋接器可建構主動晶粒，且可使用線焊而附著至基板。
縮小晶粒尺寸以及增加晶粒性能之需求所要求的是，必須增加對應之晶粒至晶粒互連的密度。例如可預期的是，為了要達成此目標，必須解決若干的製造問題。一種此問題係固有於製造互連於有機基板材料之內的困難度。為了要克服此問題，已提出插入於晶粒與封裝基板之間的矽插入物。標準之銅鑲嵌處理的使用允許次微米尺寸之線和間隔的製造。然而，大的矽插入物面積及用於貫穿矽之通孔(TSV)的需求使得此方法變得昂貴，因而抵消了所感覺之MCP衍生的成本助益。
本發明之實施例藉由嵌入於封裝基板中或附著至封裝基板的矽橋接器(或由其他材料所製成的橋接器)，以便致能互連結構的密度縮放，而顯示出在現有技術世代上之加速的改善。該等橋接器僅需由晶粒邊緣至晶粒邊緣來支撐濃密的晶粒至晶粒互連，且因此，可比矽插入物更小。矽橋接器概念亦排除TSV技術的需求。除了由於高密度的互連結構而大大增加通訊帶寬之外，本發明之實施例亦可由於(至少部分地)矽處理技術的成熟而致能改善的總成處理。
本發明之若干實施例可致能具有前所未有之晶粒至晶粒互連密度的MCP之製造，該等晶粒至晶粒互連密度將依序致能MCP型之成本節省、模組性、及架構彈性。此等潛在之好處的實例包含藉由晶粒縱橫比最適化之改善的光罩及晶圓實用性，組合使用不同之最適化的矽(或其他)處理之晶粒或結合不同或不可相容的設計方法學之晶粒於單一封裝內的能力，組合非矩形或大的〝超級晶粒〞之能力，以不同高度來結合晶粒或晶粒堆疊的能力，及其類似者。
本發明之實施例亦致能包含矽橋接器之橋接器對封裝基板的精確對齊。在用於隨後晶粒附著之整個良好界定的凸塊場之產生中，尤其就目標在矽橋接器上之高互連密度而言，此對齊係重要的。再者，在晶粒上型之密度可允許以最小的修正來再使用現有的電路設計，且在晶粒-封裝介面處之許多可用的接腳可致能簡單的協定以及良好的輸入/輸出(I/O)功率效率。
本發明之若干實施例使用混合覆晶/線焊組合之主動〝衛星〞晶粒，其中晶粒係覆晶連接到至少一處理單元晶粒，且亦係藉由線焊而直接連接至封裝基板。處理單元晶粒係使用覆晶互連而組合至封裝基板。在衛星晶粒與處理單元晶粒間的覆晶互連致能高密度、高速度的通訊於衛星晶粒與處理單元晶粒之間，且除了提供衛星晶粒的主動功能性至一或更多個處理單元晶粒之外，亦(其中包含多重處理單元晶粒於該處)允許衛星晶粒扮演高速度的矽橋接器之角色，而致能高速度、高密度的連接性於二或更多個處理單元晶粒之間。除了藉由覆晶連接提供功率至處理單元晶粒之外，對衛星晶粒的線焊連接允許用於對該晶粒的功率輸送，且進一步允許額外的I/O或控制信號連接性。伴隨著上述實施例，亦可完全避免TSV。
現請參閱圖式，第1A、1B、及1C圖係依據本發明各式各樣實施例之多晶片封裝100的平面視圖，以及第2圖係在依據本發明實施例之多晶片封裝100的第1C圖中之線2-2處所取得的橫剖面視圖(第1A及1B圖之對應橫剖面的視圖將非常相似或相等於第2圖中所描繪的橫剖面)。如第1A至1C圖以及第2圖中所描繪地，多晶片封裝100包含基板110，基板110具有側面111、相對側面112、及自側面111延伸至側面112之側面213。多晶片封裝100進一步包含晶粒120及晶粒130以及橋接器140，該等晶粒均被附著至基板110的側面111，且橋接器140係毗鄰基板110的側面213以及被附著至晶粒120及至晶粒130。如所描繪地，且如在下文將進一步解說地，基板110並不具有在橋接器140之下面的部分，使得針對橋接器140存在有穿過或沿著基板110之不受阻礙的路徑至晶粒120及130。橋接器140藉由匹配通過橋接器140之電性及/或光學導通走線與在晶粒上之接墊或其他互連結構，以產生連接(例如，電性或光學連接或其類似者)於晶粒120與晶粒130之間。
在某些實施例中，如上述地，橋接器140包含矽。使用矽橋接器係因為矽處理技術相當進步之緣故，且使用現有的矽處理技術可獲得的互連間距和線寬會比例如使用目前用於聚合物層中之銅線的可用技術之者更大大地小。因此，當使用矽橋接器時，晶粒至晶粒互連可以以比當製造該等互連於典型的有機基板材料內時之更大的密度來製造。大致而言，本發明之實施例使用具有高密度焊料凸塊和細線的矽橋接器，而高密度細線係使用傳統的矽處理所製成。
在一些實施例中，橋接器140可為被動組件，其中除了提供高速度、高密度的發信號通路於晶粒120及130間之外，其不具有功能性。在其他實施例中，橋接器140包含主動晶粒，該主動晶粒具有除了橋接功能外之其特有的功能性，而建構多晶片封裝100的第三晶粒(晶粒120及晶粒130係最初之二者)。在該等實施例中，橋接器140可具有針對混合總成所致能的設計，例如，具有製備於主動晶粒的相同側(表面)之用於覆晶互連的凸塊和用於線焊連接的接墊二者。而且，該等實施例可降低製造費用。例如，除了與另一處理單元晶粒的連接性之外，需要封裝上外部記憶體的處理單元晶粒可由具有快速局部記憶體功能性之單一橋接器晶粒所提供，藉以排除另一額外組件的需求，而此一橋接器將提供該兩功能。
例如，主動晶粒可為主動矽晶粒，或主動晶粒可包含諸如砷化鎵(GaAs)、鍺化矽(SiGe)、或任何其他適合的半導體材料之其他半導體材料，或半導體材料的組合。雖然此說明將時常提及〝主動矽晶粒〞，但應瞭解的是，亦可思及任何適合的半導體材料或材料之組合的主動晶粒。而且，應瞭解的是，此處所謂之主動晶粒，不論其係由何種材料所製成，除了其扮演橋接器以及提供其他晶粒間的連接之能力外，其具有其特有的功能性。
在所描繪的實施例中，側面111與側面213的交叉產生邊緣117。在第1A圖之中，邊緣117係內部基板邊緣，因為其沿著基板110的內周邊而伸展。對照地，在第1B及1C圖中之邊緣117係外部基板邊緣，因為其沿著基板110的外周邊而伸展。在後者之實施例(第1B及1C圖)中，側面213建構基板110的外周邊的一部分，亦即，立界限整個基板110的周邊；而在前者之實施例(第1A圖)中，側面213建構基板110的內周邊的一部分，亦即，立界限基板110之內部特徵的周邊，諸如孔徑119，但並未立界限整個基板110。
如描繪地，晶粒120及130係配置使得其突出基板110的內部或外部邊緣：晶粒120的一部分221突出邊緣117，且同樣地，晶粒130的一部分231突出邊緣117。如上述，突出於內部基板邊緣的晶粒意指基板110具有諸如孔徑119的孔徑。在至少一些實施例中，此孔徑係稍大於橋接器140。在其中若多重橋接器係所欲的情況中，則可設置多重孔徑，或可根據設計需求而將更小的孔徑結合於更大的孔徑之內，以容納多重橋接器。如上述且如第1B圖中所描繪地，突出於外部基板邊緣意指的是，晶粒120及130係安裝於靠近封裝基板周邊。然而，在某些情況中，突出數量可能比所欲的更大，而負面地影響到I/O選路、電力輸送、熱管理、及其類似者。該等問題可藉由使用諸如第1C圖中所示之開槽封裝基板以克服。
在第2圖中可看到的是，突出邊緣117(且連接至橋接器140)之晶粒120及130的部分，亦即，部分221及231，分別包含具有比晶粒120及130的非突出部分之互連結構更小間距的互連結構。此係符合上文關於可在橋接器140之內及外部二者獲得的間距之已描述的。在一實施例中，細間距介面(亦即，包含於部分221及231中之該等間距介面)係與晶粒120及130的非突出部分之粗間距介面分離地形成。關於該等互連結構，應提及的是，在此敘述成為具有〝細間距〞之該等互連結構無需一定要均具有與其他〝細間距〞互連結構之各者相同的間距，且所有〝粗間距〞互連結構亦無需一定要具有與其他〝粗間距〞互連結構之各者相同的(粗)間距。而是，大致地，各個〝細間距〞互連結構具有比任何〝粗間距〞互連結構更細的間距，但個別的間距變化可存在於個別的互連結構。用於矽橋接器之密集晶粒至晶粒互連的電性發信號分析已顯示出的是，在相關密度以及在所需的長度上(例如，直至2毫米)之不具有重發器的發信號係可行的。此外，在至少一實施例中，若干或所有的該等互連結構可包含覆晶或控制之崩塌晶片連接(C4)之連接(在此，〝覆晶〞及〝C4〞係可互換地使用)。因為該等連接係熟知於本項技藝中，所以除了述及製造係明顯於所使用的何種特定技術(是否回流，熱壓縮接合，或某些其他的處理)以製造之外，其結構及製造的細節將不予以解說。
針對下文所解說之理由，在某些實施例中(例如，諸如其中橋接器140係主動矽晶粒)，橋接器140係使用線焊241而附著至基板110(為了增加圖式之明晰，已將該等線焊自第1A至1C圖省略)。在第2圖中僅顯示一部分的線焊241，因為該圖很難以描繪出線焊的全部範圍。然而，應瞭解的是，為了要產生電性連接於橋接器140與基板110之間，線焊241係以不斷裂的路徑自橋接器140延續至基板110。
如上述地，無需TSV於橋接器140之中或用於此處所敘述之其他的橋接器/衛星晶粒。衛星晶粒係使用覆晶(面對面)連接而連接至處理單元晶粒，以便允許處理單元與衛星晶粒之I/O介面以及提供介面(其中在該處所欲者)以供晶粒至晶粒橋接功能之用。在某些實施例中，衛星晶粒之所有或一些的其他(較緩慢)I/O以及其之電力及接地的連接係由線焊所供應。此顯示可能的成本節省。使用線焊法以供應I/O以及電力及接地的連接而非透過連接之處理單元晶粒以供應該等連接的優點在於，處理單元晶粒將無需基礎架構來提供並非該處理單元晶粒本身所需之電力及額外的I/O，而額外的基礎架構以及相關聯的系統開銷將可能增大處理單元晶粒面積，且會大大地增加處理單元成本。而且，若不具有衛星晶粒而使用時，則此附加的基礎架構將係浪費的。
第3圖係流程圖，描繪依據本發明實施例之提供多晶片封裝中之晶粒至晶粒互連的方法。例如，方法300可顯示一部分之製程，而造成與如第1A、1B、1C、及2圖中所示之多晶片封裝100相似的多晶片封裝之形成。雖然該等圖式描繪連接二晶粒之單一橋接器，但本發明之其他實施例可包含多於二晶粒及/或超過單一橋接器。
方法300之步驟310係提供具有第一側、相對的第二側、及第三側之基板，該第三側自第一側延伸至第二側。例如，基板可與基板110相似，以及第一側、第二側、及第三側可分別與基板110的側面111、側面112、及側面213相似。側面111及112係首先顯示於第1A圖中，以及側面213係顯示於第2圖中。在一實施例中，步驟310包含形成孔徑穿過基板，使得第三側建構基板之內周邊的一部分。例如，此實施例可產生諸如第1A圖中所示之MCP。在另一實施例中，步驟310包含形成開槽於基板中，使得第三側建構基板之外周邊的一部分。例如，此實施例可產生諸如第1C圖中所示之MCP。該等實施例之任一者之特徵在於：比嵌入於基板空穴中之如本文的其他處所述之橋接器所需的成本更低。確實地，在其中將使用無核心基板或其他薄的基板之情況中，該等實施例可為唯一可行的選項。例如，諸如上述之該等孔徑或開槽可由機械或雷射鑽孔、銑削、選路、衝壓、穿孔、蝕刻、或其類似方法所形成。
方法300之步驟320係附著第一晶粒至基板的第一側，使得第一晶粒的一部分延伸越過基板之第一側的邊緣。例如，第一晶粒可與第1A圖中所先顯示之晶粒120相似。做為另一實例，基板之第一側的邊緣可與邊緣117相似，且延伸越過邊緣之第一晶粒的部分可與第2圖中所先顯示之晶粒120的部分221相似。
方法300之步驟330係附著第二晶粒至基板的第一側，使得第二晶粒的一部分延伸越過基板之第一側的邊緣。例如，第二晶粒可與第1A圖中所先顯示之晶粒130相似。做為另一實例，延伸越過邊緣之第二晶粒的部分可與第2圖中所先顯示之晶粒130的部分231相似。在一實施例中，步驟320及330可結合成為單一步驟。在相同或另一實施例中，步驟330及320(或結合該二步驟的單一步驟)的晶粒附著包含藉由焊料自行對齊(Solder self-alignment)所促進的對齊功能。注意的是，在實施例中，該焊料自行對齊發生於粗間距MCP晶粒附著步驟之期間，且晶粒可藉基板之第一側上的單一微影界定之焊料遮罩圖案而彼此相對地精確定位。
方法300之步驟340係提供包含複數個導電及/或光學導通特徵的橋接器。例如，橋接器可與第1A圖中所先顯示之橋接器140相似。因而，在若干實施例中，橋接器可為主動矽晶粒。做為另一實例，導電特徵可為例如在本項技藝中所熟知之金屬走線或其類似物，而適用以傳導電力於MCP之一區域與另一區域、或一組件與另一組件之間；且同時，光學導通特徵可為例如諸如氮化矽波導、肋背波導、及其類似物之光學波導，或諸如光柵、微反射鏡、及透鏡之光學耦合元件。
方法300之步驟350係定位橋接器以毗鄰基板之第三側，使得基板不具有在橋接器之下面的部分。此配置允許具有在熱膨脹係數(CTE)中之大的失配之材料的橋接器和基板之機械退耦。再者，非約束之橋接器可提供封裝應力好處，因為其可無產生折彎負荷於細間距接合處之上而移動。因此，方法300可無需使用底部填充劑或密封材料來充填孔徑或開槽中之橋接器周圍的空間或其類似者。例如，步驟350可使用取放機以完成，如本項技藝中所熟知地。
方法300之步驟360係附著橋接器至第一晶粒且至第二晶粒，藉以產生電性或光學連接於第一晶粒與第二晶粒之間。因而，步驟360可自封裝的背面來建構附著，亦即，方法300可建構〝橋接器持續〞處理流程。應注意的是，因為基板並不具有在橋接器之下面的部分，所以此〝橋接器持續〞處理流程可允許使用全厚度橋接器(除非熱機械考量指出橋接器薄化將有利於細間距互連的可靠性，或除非需要薄化以形成因子或機械淨空)，而其中，在其他的處理流程中將需要使用變薄的橋接器。而且，〝橋接器持續〞處理流程可致能具有不同高度之晶粒或晶粒堆疊之MCP的建立，而無需任何修正於所述的總成流程；且同時，亦可提供可縮放之解決而以給定的MCP組態來致能可給予之多重橋接器的總成。
在一實施例中，步驟360可使用熱壓縮接合處理以完成。在另一實施例中，步驟360包含使用焊料回流處理。如本項技藝中所熟知地，在熱壓縮接合中，溫度及壓力可被控制，而在焊料回流法中只能控制溫度。而且，如所知地，焊料回流係高產出量的批處理。熱壓縮接合係典型地順序之處理；然而，〝成群的〞接合器可一次處理若干單元。因為熱壓縮接合之處理彈性及其處理參數之較佳控制，所以在若干實施例中，需要熱壓縮接合以達成細間距互連。
方法300之步驟370係使用線焊以附著橋接器至基板。例如，線焊可與第2圖中所示之線焊241相似。步驟370可執行於例如其中橋接器係主動晶粒的實施例中。然而，應瞭解的是，步驟370無需一定要執行於方法300的每個實施例之中。
第4圖係流程圖，描繪依據本發明另一實施例之提供多晶片封裝中之晶粒至晶粒互連的方法400。方法400係組合處理，其在附著橋接器及晶粒至封裝基板之前，先致能橋接器對MCP晶粒的精確對齊。此橋接器及晶粒至封裝基板之隨後的附著可以以橋接器對晶粒之先行處理而變得更容易，因為該先行處理會排除受到混合之凸塊、細間距所典型造成的若干問題。例如，方法400亦可使用於當無法提供具有切除部分之基板時，以及當外部基板邊緣上之突出由於設計考量而非選項時。方法400以及與該方法相關連之多晶片封裝500係進一步描繪於第5至8圖中，第5至8圖係依據本發明實施例之多晶片封裝500在其製程中之各式各樣特定點處的橫剖面視圖。
如下文將進一步詳述地，方法400大致地包含晶粒至載體之附著，一或更多個橋接器至晶粒之細間距組合，載體、晶粒、及橋接器至封裝基板之粗間距組合，以及載體之退接合(隨意地)。此方法凌越本文中所敘述之一或更多個其他方法或實施例的潛在優點在於，此方法在混合式凸塊間距之組合流程中排除封裝基板做為機械參考，且此方法以分離步驟形成細間距及粗間距互連。再者，方法400允許在三維中之準確的橋接器對齊。如上述地，為了要產生全面之良好界定的凸塊場以供隨後晶粒附著之用，準確的橋接器對齊係重要的。高的互連密度強調此需求。
方法400之步驟410係附著第一晶粒及第二晶粒至載體。當設置該等晶粒時，可使用在先前所設置之晶粒上或在諸如載體之副組合的其他組件上之合適的基準者以做為參考。例如，第一晶粒及第二晶粒可分別與第1A圖中所最初顯示之晶粒120及晶粒130相似。做為另一實例，第一晶粒及第二晶粒可分別與第5圖中所顯示之晶粒520及晶粒530相似。附著至晶粒520的係細間距互連結構521及粗間距互連結構522。附著至晶粒530的係細間距互連結構531及粗間距互連結構532。更特定地，且如第5圖及隨後之圖式中所描繪地，晶粒520具有包含互連結構521之部分526，及包含互連結構522之部分527。同樣地，晶粒530具有包含互連結構531之部分536，及包含互連結構532之部分537。如上述地，互連結構521及531具有第一(細)間距，以及互連結構522及532具有與第一間距不同的第二(粗)間距。如本文中之其他處已敘述地，可明白的是，部分526及536係附著至橋接器(藉細間距互連結構521及531)。注意的是，互連結構521及531將典型地為矽至矽結構而非矽至有機結構。例如，此可協助搶先阻止典型地與二材料間之熱膨脹係數(CTE)中之失配所相關聯的問題。
載體可與第5圖中所示之載體505相似。在一實施例中，載體包含整合之散熱器(IHS)。例如，該散熱器可由銅或其類似物所製成。由於銅(或其類似物)IHS之高的熱傳導性，所以可熱強化封裝。在第5圖的實施例中，晶粒520及530係使用黏著劑材料507而附著至載體505，該黏著劑材料507可包含熱介面材料(TIM)或其類似物。
方法400之步驟420係附著橋接器至第一晶粒及第二晶粒。注意的是，在此步驟中僅附著細間距互連結構。小的凸塊間距需要高度準確的取放器裝備。再者，在晶粒上之基準者可有用於達成成功的接合。例如，橋接器可與第1A圖中所顯示之橋接器140相似。而做為另一實例，橋接器可與第5圖中所示之橋接器540相以，亦即，如橋接器140似地，可由矽所製成，且進一步地，可為主動矽晶粒。在一實施例中，步驟420包含使用熱壓縮接合法，以彼此相互地接合橋接器及晶粒。在其他實施例中，步驟420包含使用如本項技藝中所熟知之焊料回流法或另外的附著程序。
方法400之步驟430係提供基板。例如，基板可與第1A圖中所最先顯示之基板110相似。做為另一實例，基板可與第6圖中所示之基板610相似。在所描繪的實施例中，基板610包含空穴615，該空穴615包含由諸如密封材料、底部填充材料、環氧、或其類似物之保護材料612所包圍的橋接器540。為了要機械地退耦橋接器540及基板610，材料612可為順性的或撓性的，且其之存在可致能晶粒520及530之無擾動的底部充填。
做為仍一實例，基板可與第7圖中所示之基板710相似。在第7圖的實施例中，晶粒520及530係形成於或設置於多晶片封裝500的晶粒層750之中。基板710不具有空穴；其係比橋接器540更大大地薄之橋接器740，且位於基板710的表面上，或係設置於基板710與晶粒520及530之間，換言之，橋接器740係座落於晶粒層750與基板的表面之間(在其他方面，橋接器740可與橋接器540及140相似，且因此，在某些實施例中，可為主動晶粒)。而且，在第7圖的實施例中，為了要適應降低厚度之橋接器740，必須修正一或更多個互連結構521、522、531、及532。例如，互連結構521及531可能必須縮短，且同時，互連結構522及532可能必須加長，以便適應不同的封裝幾何。如本文中所述之其他實施例一樣地，一或更多個互連結構521、522、531、及532可包含覆晶連接。應注意的是，橋接器740可薄至需要其自身的載體，以便例如在方法400的步驟420之前和之期間促進操縱。
方法400之步驟440係附著第一晶粒及第二晶粒至基板。在此步驟中，僅附著具有大的間距之晶粒凸塊(在橋接器區域之外面)。因為凸塊間距大，所以可典型地使用較不昂貴的取放器裝備。在步驟440之後的多晶片封裝500之產生係描繪於使用基板610之實施例的第6圖中，以及使用基板710之實施例的第7圖中。
在一些實施例中，步驟440之後係去除載體。例如，此可藉由剝離、切除、蝕掉、或溶化黏著物材料，或自晶粒退接合載體而完成。第8圖顯示去除載體505之後的多晶片封裝500。在第7圖中之載體505亦被去除(未描繪)。在其他實施例中，諸如當載體係散熱器時，並不執行步驟440，且載體係永久地留在適當的位置。
在又一實施例中(未描繪)，為了要適應不同厚度的晶粒，混合之單晶粒及晶粒堆疊，或不同高度之晶粒堆疊，可使載體或IHS成步階，以致在橋接器至晶粒附著之前，將由個別之橋接器所互連的凸塊係共平面的。合適的步階或空穴可藉機械加工該載體或IHS而產生。
方法400之步驟450係使用線焊以附著橋接器至基板。例如，線焊可與第2圖中所示的線焊241或與第8圖中所示的線焊841相似(第7圖之實施例亦可包含線焊，或換言之，在某些實施例中，橋接器740亦可使用線焊以連接至基板710。然而，該等線焊並未被描繪於第7圖之中，因為其中載體505的圖與該圖之橫剖面性質所結合的存在使得難以清楚地繪示該等線焊，或因為該等線焊係在載體505的去除之後才被添加之故)。僅一部分的線焊841顯示於第8圖之中，因為該圖之透視圖難以描繪該等線焊的全部範圍。然而，應瞭解的是，線焊841連續以未斷裂之路徑自橋接器540至基板610，以便產生電性連接於橋接器540與基板610之間。例如，在其中橋接器在該處係主動晶粒的實施例中，可執行步驟450。然而，應瞭解的是，步驟450無需一定要被執行於方法400的每個實施例中。
第9圖係依據本發明實施例之多晶片封裝900的橫剖面視圖。如第9圖中所描繪地，多晶片封裝900包含：基板910，該基板910包含空穴915，該空穴915具有複數個接墊918於其中；晶粒920及晶粒930，係附著至基板910；橋接器940，具有側面941及相對的側面942；以及複數個接合處960，在橋接器940的側面942。例如，接墊918及接合處960可為無電性功能的。接墊918可在傳統建造處理之期間予以預製造，且然後，在空穴形成之期間，例如藉由雷射銑削法或其類似方法以暴露。
密封材料945至少部分地包圍所描繪之實施例中的空穴915中之橋接器940。例如，基板910、晶粒920、晶粒930、及橋接器940均可分別與第1A圖中所最初顯示之基板110、晶粒120、晶粒130、及橋接器140相似。因而，在若干實施例中，橋接器940可為主動晶粒。例如，可從圖式中看到的是，晶粒920及晶粒930係附著至橋接器940的側面941；至少一部分的橋接器940係設置於空穴915之內，使得複數個接合處960與接墊918對齊；以及橋接器940產生電性或光學連接於晶粒920與晶粒930之間。
晶粒920具有包含複數個互連結構921之部分926，以及包含複數個互連結構922之部分927。同樣地，晶粒930具有包含複數個互連結構931之部分936，以及包含複數個互連結構932之部分937。互連結構921及931具有第一(細)間距，以及互連結構922及932具有與第一間距不同的第二(粗)間距。部分926及936係附著至橋接器(藉細間距互連結構921及931)。
如本文中之其他處已解說地，在若干實施例中，諸如，例如當其中在該處橋接器940係主動晶粒時，橋接器940係使用線焊以附著至基板910。該等線焊並未描繪於第9圖中，因為該圖的性質使該描繪變得困難。然而，應瞭解的是，以本文中所描述之其他圖式中所顯示的相似方式，該等線焊係以未斷裂之路徑自橋接器940連續至基板910，以便產生電性連接於橋接器940與基板910之間。
第10圖係流程圖，描繪依據本發明實施例之提供多晶片封裝中之晶粒至晶粒互連的方法1000。例如，方法1000可顯示一部分之製程，其產生與例如第9圖中所示的多晶片封裝900相似之多晶片封裝的形成。
如下文將進一步詳述地，方法1000大致地包含提供封裝基板，機器加工或形成用於矽或其他橋接器之空穴，分配助熔劑至空穴底部接墊之上，取放具有背面焊料凸塊之橋接器，橋接器之焊料自行對齊的焊料回流，去助熔劑(除非使用無需清除之助熔劑或無助熔劑之附著處理)，橋接器的密封，以及主動晶粒之組合。此處理之潛在優點在於，其對於封裝上之多重橋接器及面板上之許多基板可立即縮放。
方法1000之步驟1010係提供具有複數個嵌入式接墊的基板。例如，基板和接墊可分別與第9圖中所示的基板910和接墊918相似。
方法1000之步驟1020係形成空穴於基板中，使得接墊暴露於空穴的底部。例如，空穴可與第9圖中所示的空穴915相似。在一實施例中，步驟1020可使用雷射銑削處理，電漿蝕刻/反應性離子蝕刻(RIE)處理，或其類似處理以完成。當形成空穴915時，可暴露空穴底部之非電性功能的(虛擬的)或其他的接墊918。在一實施例中，這些係由先前在傳統基板建造處理期間所製造的，且由一或更多個電介質建造層所埋置的。接墊918可由銅所製成，且可存在諸如非電解鎳之合適的表面光蝕劑，對軟焊導熱之插入金(ENIG)。當使用雷射銑削法於空穴形成而以雷射操作停止於接墊層時，約10微米(μm)之最小接墊厚度可為所欲的。配對接墊可設置於橋接器940的背面，且橋接器可使用標準金屬化及隆起技術而預先地，大概在晶圓層次隆起。阻焊劑層亦可被添加至橋接器940的背面。
方法1000之步驟1030提供具有對應於接墊之凸塊於其上的橋接器。(凸塊與接墊間之此對應可以意指，但無需一定要意指凸塊的數目與接墊的數目係彼此相等；更確切的說，該對應係使得該等凸塊與接墊匹配至可靠的機械接合係可行的程度)。例如，橋接器可與第9圖中所示的橋接器940相似，且因而，在某些實施例中，可為主動晶粒，以及所形成之接合處亦可與第9圖中所示的接合處960相似。
方法1000之步驟1040係設置橋接器於空穴中，且彼此相互地對齊凸塊與接墊。步驟1040附著橋接器至基板。在一實施例中，凸塊與接墊彼此相互的對齊係在回流及接合處形成期間使用焊料的自行對齊以完成。其中液體焊料之表面張力係驅動力之電子組件的焊料自行對齊係熟知於本項技藝中。焊料接合處陣列的仔細設計可以以位置公差在1微米(下文中稱為〝μm〞)之大小來提供自行對齊於x及y維中。在z維(高度)中之準確對齊可藉由焊料體積的控制以達成。接著，可將精確對齊的橋接器密封，藉以鎖定該橋接器於其之精確界定的位置。然後，可將所生成之混合封裝基板供應至晶粒附著模組。
方法1000之步驟1050提供第一晶粒及第二晶粒。例如，第一晶粒及第二晶粒可分別與第9圖中所示之晶粒920及晶粒930二者相似。
方法1000之步驟1060係附著第一晶粒及第二晶粒至橋接器及基板。在一實施例中，步驟1060包含助熔劑分配步驟、晶粒取放步驟、及回流步驟。
如本文中之其他處所述地，在非常高的I/O密度及非常細微的橋接器互連間距處，為了要促進MCP的成功組合(晶粒附著)，準確對齊將變得重要。因此，在若干實施例中，且如第9圖中所示地，位於橋接器940背面(亦即，側面942)之接合處960被使用來達成橋接器940相對於其他的封裝基板凸塊之精確對齊。熟知地，焊料自行對齊可以以位置公差在1微米之大小來致能x及y維中之最終的組件設置。做為焊料的選擇例，亦可使用能根據下方表面張力原理(在接合期間之附著能量的最小化)來提供自行對齊之合適的非導電材料。
方法1000之步驟1070係使用線焊以附著橋接器至基板。例如，線焊可與第2圖中所示的線焊241或與第8圖中所示的線焊841相似。例如，步驟1070可執行於其中在該處橋接器係主動晶粒的實施例。然而，應瞭解的是，步驟1070無需一定要執行於方法1000的每個實施例之中。
第11A圖係依據本發明實施例之多晶片封裝1100的平面視圖。各取第11A圖中之線B-C的多晶片封裝1100之二不同實施例的橫剖面視圖係顯示於第11B及11C圖之中。如第11A至11C圖中所描繪地，多晶片封裝1100包含：基板1110；主動晶粒1120，係使用覆晶連接1121以附著至基板1110(在第11A圖中，覆晶連接1121係可見於描繪為透明(用於描繪性之目的)之主動晶粒1120的一部分1125中)；以及主動晶粒1130，其係使用覆晶連接1131以附著至主動晶粒1120，且其係使用線焊1141以附著至基板1110。
如在圖式中可看到地，多晶片封裝1100係其中以混合方式所組合的衛星晶粒係附著至單一封裝上(處理單元)晶粒之實施例的實例。此一配置允許高密度、高速度的覆晶連接性於處理單元與衛星晶粒之間，且進一步允許處理單元晶粒使用衛星晶粒的功能。其中在並不需要高密度之互連的情況中(例如，因為衛星晶粒的功能)，覆晶互連可具有相對粗的間距。由衛星晶粒所需之諸如，但未受限於電力及接地連接的額外連接可由位於不會受到處理單元晶粒所遮蔽之衛星晶粒側面的線焊所提供。
在若干實施例中，基板1110包含空穴，其中至少部分地設置主動晶粒1130。此一空穴係可在第11B圖中見到，且實例亦可在第6、8、及9圖中看到。在其他實施例中(請參閱第11C圖)，基板1110具有第一側、相對的第二側、及自第一側延伸至第二側的第三側(並未以參考符號識別於第11C圖中，但諸如可如上述地形成孔徑或開槽)，主動晶粒1120係使用覆晶連接1121以附著至基板1110的第一側，主動晶粒1130係使用線焊1141以附著至基板1110，以及基板1110並不具有在主動晶粒1130之下面的部分。該等實施例係與結合第1A至1C圖及第2圖所敘述之該等實施例相似。在該等情況之各情況中，收容該等衛星晶粒之該等空穴、孔徑、開槽、及其類似物可與處理單元晶粒的凸塊場部分地重疊，以便如在此所述地致能覆晶、高速度、高密度的連接於衛星晶粒與處理單元晶粒之間。
主動晶粒1130具有區域1138及區域1139，其中區域1138係位於主動晶粒1130(在下面)與主動晶粒1120(在上面)之一部分間的重疊區域。如圖示地，重疊區域可為主動晶粒1120及1130之部分重疊，以致下方晶粒並不會完全在上方晶粒的下面。重疊區域可為彼此相互電性或光學連接該等主動晶粒之一或更多個面對面覆晶連接的位置。再請參閱所描繪之實施例，覆晶連接1131係設置於區域1138之中，而線焊1141則附著至區域1139中之主動晶粒1130。
在所描繪的實施例中，主動晶粒1130係使用線焊1141以附著至基板1110。注意的是，主動晶粒1130的一邊緣係顯示為具有雙列的線焊。在一些(未描繪的)實施例中，可製造三或更多列線焊。然而，該多重列無法獲得與以單一列可達成之相同的細間距，亦即，小至35微米之接墊間距(對應於每毫米晶粒邊緣大約29個接合)。針對電力和接地連接，無需一定要最小的間距線焊能力，且小間距之粗的接合導線係可接受或甚至適當的。應瞭解的是，此處所引用之圖式並不打算成為限制，且未被描繪的實施例可使用更多或更少個雙重線焊列(包含不具有該等列之實施例)，具有超過二線焊列之一或更多個部分，具有更多或更少個線焊之更長或更短的列，僅沿著主動晶粒之某些側邊而非所有側邊的線焊，或任何其他有效之線焊組態。
在一實施例中，主動晶粒1120係諸如中央處理單元(CPU)、繪圖處理單元(GPU)、或其類似者之處理單元晶粒，而主動晶粒1130係具有諸如記憶體(包含諸如快速DRAM、外部SRAM、eDRAM、及其類似者之揮發性記憶體，以及諸如快閃記憶體及其類似者之非揮發性記憶體)、繪圖處理、電力輸送之電壓調整、射頻(RF)、或其類似者、包含其有效組合之功能的衛星晶粒。依據各式各樣實施例之衛星晶粒甚至可為微電機機械系統(MEMS)晶片，使用於系統在封裝上(SoP)之中的感測器晶片、或具有光電子功能之光電子晶片。在此，主動晶粒1130係偶爾稱為衛星晶粒，因為其係連接主動晶粒1120，且可與主動晶粒1120分享主動功能。在某些實施例中，除了主動晶粒1120之外，主動晶粒1130亦可連接至一或更多個其他的晶粒(並未描繪於第11A至11C圖中)，且與該等晶粒分享主動功能。其中在衛星晶粒係連接至超過一個的主動晶粒之情況中，衛星晶粒可或不必相互電性或光學連接該等晶粒於彼此，或換言之，可或不必以在本文中其他處所解說之方式來扮演該等主動晶粒之間的橋接器。
第12圖係依據本發明實施例之主動晶粒1130的平面視圖。在第12圖中之主動晶粒1130的大小係比其在第11A至11C圖中稍大。如第12圖中所描繪地，主動晶粒1130的區域1138具有部分1201及部分1202。部分1201包含具有第一密度的複數個覆晶連接1231，以及部分1202包含具有比第一密度更小之第二密度的複數個覆晶連接1131(在第11A圖中已先行介紹)。更高密度和更低密度的連接可根據主動晶粒1130的功能而視需要地使用。
在所描繪的實施例中，區域1138進一步包含部分1203，部分1203包含具有第三密度的複數個覆晶連接1233，第三密度亦比第一密度更小，且在一實施例中，可與第二密度相同或實質地相似。在部分1201、1202、及1203之任一或更多者中的該等連接可致能主動晶粒1120存取主動晶粒1130的功能，且反之亦然。雖然在第12圖的實施例中，部分1201係設置於部分1202與部分1203之間，但例如將呈立即明顯於熟習本項技藝之一般人士的是，其他組態亦係確實可行。例如，主動晶粒1130可具有僅單一(高)密度、僅單一(標準或低)密度、一部分高密度及另一部分低密度，而以任一合適組態來配置該等密度的覆晶連接。且，此處應注意的是，在其中橋接器係主動晶粒的實施例中，任一或更多個橋接器140、540、740、及940可具有上述用於主動晶粒1130之特性、組態、功能、等等。同樣地，任一或更多個晶粒120、130、520、530、920、及930可與主動晶粒1120相似。
如已敘述的是，主動晶粒1130可連接至除了主動晶粒1120外之一或更多個主動晶粒。在若干實施例中，亦如上述地，主動晶粒1130扮演主動晶粒1120與該等額外的主動晶粒之間的橋接器。此之實例係描繪於第1A至1C圖、第2圖、及第6至9圖中，若假定該等圖式中之橋接器係主動晶粒時。第13圖進一步描繪依據本發明實施例之用於主動橋接器或衛星晶粒1330之可能的組態。
如第13圖中所描繪地，主動晶粒1330包含區域1338，區域1338係與區域1138相似。例如，在所描繪的實施例中，與區域1138相似地，區域1138包含區段1201、1202、及1203，各個區段包含上述之特性和組件。延伸於區域1138的區段1201與區域1338的對應區段之間的電性及/或光學傳導之橋接器走線1370提供電性或光學連接於藉由主動晶粒1330所橋接的晶粒之間。該等晶粒並未顯示於第13圖之中，但將例如利用覆晶連接1131、1231、及1233而以與用於主動晶粒1120之上述方式相似的方式附著至主動晶粒1330。
第14圖係流程圖，描繪依據本發明實施例之提供多晶片封裝中之晶粒至晶粒互連的方法1400。例如，方法1400可產生諸如第11C圖中所示之MCP(諸如第11B圖中所示之MCP可使用與方法400或方法1000相似而省略第二晶粒的方法以形成)。
方法1400之步驟1410係提供基板。例如，基板可與例如在第11C圖中顯示的基板1110相似。
方法1400之步驟1420係使用第一覆晶連接以附著第一主動晶粒至基板。例如，第一主動晶粒及第一覆晶連接可分別與第11A至11C圖中顯示之主動晶粒1120及覆晶連接1121二者相似。
方法1400之步驟1430係使用第二覆晶連接以附著第二主動晶粒至第一主動晶粒。例如，第二主動晶粒及第二覆晶連接可分別與首先在第11A圖中顯示之主動晶粒1130及覆晶連接1131二者相似。
方法1400之步驟1440係附著第二主動晶粒至基板。在一實施例中，第二主動晶粒係使用諸如首先在第11A圖中顯示之線焊1141的線焊而附著至基板。
第15圖係依據本發明實施例之多晶片封裝1500的平面視圖。如第15圖中所描繪地，多晶片封裝1500包含：基板1510；主動晶粒1520，係使用覆晶連接1521以附著至基板1510；主動晶粒1530，係使用覆晶連接1531以附著至主動晶粒1520及使用線焊1541以附著至基板1510；以及主動晶粒1550，係使用覆晶連接1551以附著至基板1510及使用覆晶連接1552以附著至主動晶粒1530。主動晶粒1520係經由設置於主動晶粒1530中之電性及/或光學傳導之橋接器走線1570，以電性及/或光學連接至主動晶粒1550。因此，主動晶粒1530扮演連接主動晶粒1520及1550的橋接器的角色。
在所描繪的實施例中，主動晶粒1520及1550具有與上文結合主動晶粒1120所敘述的及在第11A至11C圖中所顯示的該等區域和部分相同或相似的區域及部分，且設置於該等區域及部分中的特性，及該等特性的特徵亦係相似的。
在若干實施例中，基板1510包含其中至少部分地設置主動晶粒1530之空穴。此空穴無法在第15圖中見到，但可在第6、8、及9圖中看到實例。在其他實施例中，基板1510具有第一側、相對的第二側、及自第一側延伸至第二側的第三側(諸如可如上述地形成孔徑或開槽)，主動晶粒1520及1550係附著至基板1510的第一側，以及基板1510並沒有在主動晶粒1530之下面的部分。該等實施例並未明白地描繪於第15圖之中，但係與結合第1A至1C圖及第2圖所述之實施例相似。在該等情況之各情況中，收容衛星晶粒之該等空穴、孔徑、開槽、及其類似物可與處理單元晶粒的凸塊場部分地重疊，以便如在此所述地致能覆晶、高速度、高密度的連接於衛星晶粒與處理單元晶粒之間。顯示該等部分重疊之MCP封裝幾何形狀的一些實例係顯示於第16圖之中，其中，橋接器/衛星晶粒係有斜影線的，以及處理單元晶粒係顯示無斜影線(封裝基板並未顯示於第16圖中)。將瞭解的是，所描繪的實例僅顯示許多可行之組態的小部分。
第17圖係流程圖，描繪依據本發明實施例之提供多晶片封裝中之晶粒至晶粒互連的方法1700。例如，方法1700可產生諸如第15圖中所示之MCP。下文所敘述係與方法300所述之〝橋接器持續〞處理流程相似的處理流程。第15圖結構亦可以以與第8或9圖所示的基板相似之具有空穴的基板來予以製造。適用以製造該等結構的處理流程可沿著方法400及1000之線進行，而以如下文所述之第三主動晶粒的參與以供該等方法的橋接器之用。
方法1700之步驟1710係提供基板。例如，基板可與第15圖中顯示之基板1510相似。
方法1700之步驟1720係使用第一覆晶連接以附著第一主動晶粒至基板。例如，第一主動晶粒及第一覆晶連接可分別與第15圖中顯示之主動晶粒1520及覆晶連接1521二者相似。
方法1700之步驟1730係使用第二覆晶連接以附著第二主動晶粒至基板。例如，第二主動晶粒可與主動晶粒1550相似，且第二覆晶連接可與覆晶連接1551相似，主動晶粒1550及覆晶連接1551二者均顯示於第15圖之中。
方法1700之步驟1740係使用第三覆晶連接以附著第三主動晶粒至第一主動晶粒。例如，第三覆晶連接可與第15圖中顯示之覆晶連接1531相似。
方法1700之步驟1750係使用第四覆晶連接以附著第三主動晶粒至第二主動晶粒。例如，第四覆晶連接可與第15圖中顯示之覆晶連接1552相似。隨著附著至第一及第二主動晶粒二者之第三主動晶粒，且因第三主動晶粒包含如上述及第15圖中所示之電性及/或光學傳導之橋接器走線，所以方法1700固有地產生彼此相互電性及/或光學連接之第一及第二主動晶粒。選擇性地，方法1700可包含造成此電性或光學連接之附加步驟。
方法1700之步驟1760係附著第三主動晶粒至基板。在一實施例中，步驟1760包含使用線焊以附著第三主動晶粒至基板。
雖然本發明已參照特定的實施例來加以敘述，但熟習本項技藝之該等人士將瞭解的是，各式各樣的改變可予以作成而不會背離本發明之精神或範疇。因此，本發明之實施例的揭示係打算描繪且非意圖限制本發明之範疇。所打算的是，本發明之範疇應僅由附錄申請專利範圍所需的範圍來予以限制。例如，對熟習本項技藝之一般人士將立即呈明顯的是，在本文中所說明之多晶片封裝以及相關之結構及方法可以以許許多多的實施例來加以實施，且若干該等實施例之上述說明無需顯示所有可行之實施例的全部說明。
此外，已就特定的實施例來敘述好處、其他優點、及對問題的解決；然而，該等好處、優點、對問題的解決、以及可使任何好處、優點、或解決發生或變得更為明顯之任何元件不應被解讀成為任何或所有申請專利範圍之關鍵的、所需的、或主要的特性或元件。
而且，若實施例及/或限制：(1)並未被明確地主張於申請專利範圍中；或(2)在均等論之下係潛在地等效於申請專利範圍中之明確的元件及/或限制時，則在專用的學理之下，在本文中所揭示的該等實施例及限制並未賦予公眾。
100，500，1500，900，1100‧‧‧多晶片封裝
110，610，1110，1510，710，910‧‧‧基板
111，213，941‧‧‧側面
112，942‧‧‧相對側面
120，130，920，930，520，530‧‧‧晶粒
140，540，740，940‧‧‧橋接器
117‧‧‧邊緣
119‧‧‧孔徑
221，231，526，527，536，537，926，927，936，937，1125‧‧‧部分
241，841，1141，1541‧‧‧線焊
300，400，1000，1400，1700‧‧‧方法
310~370，410~450，1010~1070，1410~1440，1710~1760‧‧‧步驟
521，531‧‧‧細間距互連結構
522，532‧‧‧粗間距互連結構
505‧‧‧載體
507‧‧‧黏著劑材料
612‧‧‧保護材料
750‧‧‧晶粒層
915‧‧‧空穴
918‧‧‧接墊
960‧‧‧接合處
921，922，931，932‧‧‧互連結構
1120，1130，1520，1530‧‧‧主動晶粒
1121，1131，1231，1233，1521，1531，1551，1552‧‧‧覆晶連接
1138，1139‧‧‧區域
1201，1202，1203‧‧‧區段
1570‧‧‧橋接器走線
揭示的實施例自結合圖式中之附圖所獲得的詳細說明之讀取而呈現更佳的瞭解，其中：
第1A，1B，及1C圖係依據本發明各式各樣實施例之多晶片封裝的平面視圖；
第2圖係依據本發明實施例的第1C圖之多晶片封裝的橫剖面視圖；
第3及4圖係流程圖，描繪依據本發明實施例之提供多晶片封裝中之晶粒至晶粒互連的方法；
第5至8圖係依據本發明實施例之在製程中的各式各樣特定點處之多晶片封裝的橫剖面視圖；
第9圖係依據本發明另一實施例之多晶片封裝的橫剖面視圖；
第10圖係流程圖，描繪依據本發明另一實施例之提供多晶片封裝中之晶粒至晶粒互連的方法；第11A圖係依據本發明其他實施例之多晶片封裝的平面視圖，且第11B及11C圖係其之橫剖面視圖；第12圖係依據本發明實施例的第11A至11C圖之多晶片封裝中的主動晶粒之其中一者的平面視圖；第13圖係依據本發明實施例之主動晶粒的平面視圖；第14圖係流程圖，描繪依據本發明另一實施例之提供多晶片封裝中之晶粒至晶粒互連的方法；第15圖係依據本發明另一實施例之多晶片封裝的平面視圖；第16圖描繪依據本發明各式各樣實施例之多晶片封裝幾何形狀的若干實例；第17圖係流程圖，描繪依據本發明另一實施例之提供多晶片封裝中之晶粒至晶粒互連的方法。
100．．．多晶片封裝
110．．．基板
111．．．側面
112．．．相對側面
117．．．邊緣
120．．．晶粒
130．．．晶粒
140．．．橋接器
213．．．側面
221．．．部分
231．．．部分
241．．．線焊

Claims (48)

  1. 一種多晶片封裝，包含：基板，其具有第一側、相對的第二側、及第三側，該第三側自該第一側延伸至該第二側，其中該第三側建構該基板之外周邊的一部分；第一晶粒，係附著至該基板之該第一側，及第二晶粒，係附著至該基板之該第一側；以及橋接器，係毗鄰該基板之該第三側且附著至該第一晶粒及至該第二晶粒，其中該基板不具有在該橋接器之下面的部分，且其中該橋接器產生連接於該第一晶粒與該第二晶粒之間。
  2. 如申請專利範圍第1項之多晶片封裝，其中：該橋接器包含矽。
  3. 如申請專利範圍第1項之多晶片封裝，其中：該橋接器係使用覆晶連接而附著至該第一晶粒及至該第二晶粒；以及該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒。
  4. 如申請專利範圍第3項之多晶片封裝，其中該橋接器係使用線焊而附著至該基板。
  5. 一種提供多晶片封裝中之晶粒至晶粒互連之方法，該方法包含：提供基板，該基板具有第一側、相對的第二側、及第三側，該第三側自該第一側延伸至該第二側，其中該第三 側建構該基板之外周邊的一部分；附著第一晶粒至該基板之該第一側，使得該第一晶粒的一部分延伸越過該基板之該第一側的邊緣；附著第二晶粒至該基板之該第一側，使得該第二晶粒的一部分延伸越過該基板之該第一側的該邊緣；提供橋接器，該橋接器包含複數個電性或光學傳導特性；定位該橋接器毗鄰該基板之該第三側，使得該基板不具有在該橋接器之下面的部分；以及附著該橋接器至該第一晶粒及至該第二晶粒，藉以產生連接於該第一晶粒與該第二晶粒之間。
  6. 如申請專利範圍第5項之方法，其中：該橋接器包含矽。
  7. 如申請專利範圍第6項之方法，其中：該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒；以及該橋接器係使用覆晶連接而附著至該第一晶粒及至該第二晶粒。
  8. 如申請專利範圍第7項之方法，進一步包含：使用線焊以附著該橋接器至該基板。
  9. 如申請專利範圍第6項之方法，其中：附著該橋接器包含使用熱壓縮接合處理。
  10. 如申請專利範圍第6項之方法，其中：附著該橋接器包含使用焊料回流處理。
  11. 如申請專利範圍第6項之方法，其中：提供該基板包含形成溝槽於該基板之中於該第三側。
  12. 一種提供多晶片封裝中之晶粒至晶粒互連之方法，該方法包含：附著第一晶粒及第二晶粒至載體；附著橋接器至第一晶粒及至第二晶粒；提供基板；附著該第一晶粒及該第二晶粒至該基板，其中該基板具有空穴於該基板的外周邊的一部分；以及附著該第一晶粒及該第二晶粒至該基板包含設置該橋接器於該空穴之內。
  13. 如申請專利範圍第12項之方法，進一步包含：去除該載體。
  14. 如申請專利範圍第12項之方法，其中：該載體包含散熱器。
  15. 如申請專利範圍第12項之方法，其中：附著該橋接器包含使用熱壓縮接合處理。
  16. 如申請專利範圍第12項之方法，其中：該橋接器包含矽。
  17. 如申請專利範圍第16項之方法，其中：該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒；該橋接器係使用覆晶連接而附著至該第一晶粒及至該 第二晶粒；以及該方法進一步包含使用線焊以附著該橋接器至該基板。
  18. 一種多晶片封裝，包含：基板，該基板具有表面及側面，該側面於該基板之該表面之間，其中該側面建構該基板之外周邊的一部分；第一晶粒，係附著至該基板之該表面，及第二晶粒，係附著至該基板之該表面，該第一晶粒及該第二晶粒形成該多晶片封裝的晶粒層；以及橋接器，係附著至該第一晶粒及至該第二晶粒，且設置於該晶粒層與該基板之該表面之間且毗鄰該側面。
  19. 如申請專利範圍第18項之多晶片封裝，其中：該橋接器包含矽。
  20. 如申請專利範圍第19項之多晶片封裝，其中：該橋接器係使用覆晶連接而附著至該第一晶粒及至該第二晶粒；該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒；以及該橋接器係使用線焊而附著至該基板。
  21. 如申請專利範圍第19項之多晶片封裝，其中：該第一晶粒具有第一部分及第二部分，該第一部分包含第一複數個互連結構，及該第二部分包含第二複數個互連結構；該第二晶粒具有第三部分及第四部分，該第三部分包 含第三複數個互連結構，及該第四部分包含第四複數個互連結構；該第一複數個互連結構與該第三複數個互連結構具有第一間距；該第二複數個互連結構與該第四複數個互連結構具有第二間距，該第二間距係與該第一間距不同；以及該第一部分及該第三部分係附著至該橋接器。
  22. 一種多晶片封裝，包含：基板，其包含於該基板的外周邊的一部分的空穴，該空穴具有複數個接墊於其中；第一晶粒，係附著至該基板，及第二晶粒，係附著至該基板；橋接器，具有第一側及相對的第二側；以及複數個接合處，在該橋接器之該第二側，其中：該第一晶粒及該第二晶粒係附著至該橋接器之該第一側；該橋接器的至少一部分係設置於該空穴之內，使得該複數個接合處係與該複數個接墊對齊；以及該橋接器產生連接於該第一晶粒與該第二晶粒之間。
  23. 如申請專利範圍第22項之多晶片封裝，其中：該橋接器包含矽。
  24. 如申請專利範圍第23項之多晶片封裝，其中： 該橋接器係使用覆晶連接而附著至該第一晶粒及至該第二晶粒；該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒；以及該橋接器係使用線焊而附著至該基板。
  25. 如申請專利範圍第23項之多晶片封裝，其中：該第一晶粒具有第一部分及第二部分，該第一部分包含第一複數個互連結構，及該第二部分包含第二複數個互連結構；該第二晶粒具有第三部分及第四部分，該第三部分包含第三複數個互連結構，及該第四部分包含第四複數個互連結構；該第一複數個互連結構與該第三複數個互連結構具有第一間距；該第二複數個互連結構與該第四複數個互連結構具有第二間距，該第二間距係與該第一間距不同；以及該第一部分及該第三部分係附著至該橋接器。
  26. 一種提供多晶片封裝中之晶粒至晶粒互連之方法，該方法包含：提供基板，該基板具有複數個嵌入式接墊；形成空穴於該基板的外周邊的一部分，以致使該等接墊暴露於該空穴之底部；提供橋接器，該橋接器具有對應於該等接墊的凸塊於其上； 配置該橋接器於該空穴，且使該等凸塊與該等接墊彼此相互對齊；提供第一晶粒及第二晶粒；以及附著該第一晶粒及該第二晶粒至該橋接器及該基板。
  27. 如申請專利範圍第26項之方法，其中：該橋接器包含矽。
  28. 如申請專利範圍第27項之方法，其中：該橋接器包含主動晶粒，該主動晶粒建構該多晶片封裝的第三晶粒；該橋接器係使用覆晶連接而附著至該第一晶粒及至該第二晶粒；以及該方法進一步包含使用線焊以附著該橋接器至該基板。
  29. 如申請專利範圍第27項之方法，其中：形成該空穴包含使用雷射銑削法及電漿蝕刻處理的其中一者。
  30. 一種多晶片封裝，包含：基板；第一主動晶粒，係使用第一覆晶連接而附著至該基板；以及第二主動晶粒，其中該第二主動晶粒係使用第二覆晶於該基板的外周邊的一部分連接而附著至該第一主動晶粒，且其中該第二主動晶粒亦係附著至該基板。
  31. 如申請專利範圍第30項之多晶片封裝，其中： 該第二主動晶粒係使用線焊而附著至該基板。
  32. 如申請專利範圍第31項之多晶片封裝，其中：該第二主動晶粒具有第一區域及第二區域；該第一區域係重疊區域，位於該基板與該第一主動晶粒的一部分之間；以及該第二覆晶連接係設置於該第二主動晶粒的該第一區域之中，且該線焊係在該第二區域中被附著至該第二主動晶粒。
  33. 如申請專利範圍第32項之多晶片封裝，其中：該第二主動晶粒的該第一區域具有第一區段及第二區段；以及該第一區段包含具有第一密度之第一複數個覆晶連接，及該第二區段包含具有第二密度之第二複數個覆晶連接，該第二密度係小於該第一密度。
  34. 如申請專利範圍第33項之多晶片封裝，其中：該第一區域進一步包含第三區段，該第三區段包含具有第三密度之第三複數個覆晶連接，該第三密度係小於該第一密度；以及該第一區段係位於該第二區段與該第三區段之間。
  35. 如申請專利範圍第30項之多晶片封裝，其中：該基板包含空穴；以及該第二主動晶粒係至少部分地設置於該空穴之中。
  36. 如申請專利範圍第30項之多晶片封裝，其中：該基板具有第一側、相對的第二側、及第三側，該第 三側自該第一側延伸至該第二側；該第一主動晶粒係附著至該基板之該第一側；以及該基板不具有在該第二主動晶粒之下面的部分。
  37. 如申請專利範圍第30項之多晶片封裝，進一步包含：第三主動晶粒，係使用第三覆晶連接而附著至該基板，其中該第二主動晶粒連接該第一主動晶粒至該第三主動晶粒。
  38. 一種提供多晶片封裝中之晶粒至晶粒互連之方法，該方法包含：提供基板；使用第一覆晶連接以附著第一主動晶粒至該基板；使用第二覆晶於該基板的外周邊的一部分連接以附著第二主動晶粒至該第一主動晶粒；以及附著該第二主動晶粒至該基板。
  39. 如申請專利範圍第38項之方法，其中：該第二主動晶粒係使用線焊而附著至該基板。
  40. 一種多晶片封裝，包含：基板；第一主動晶粒，係使用第一覆晶連接而附著至該基板；第二主動晶粒，其中該第二主動晶粒係使用第二覆晶於該基板的外周邊的一部分處連接而附著至該第一主動晶粒，且其中該第二主動晶粒亦係附著至該基板；以及 第三主動晶粒，係使用第三覆晶連接而附著至該基板，且使用第四覆晶於該基板的外周邊的一部分處連接而附著至該第二主動晶粒，其中該第二主動晶粒連接該第一主動晶粒至該第三主動晶粒。
  41. 如申請專利範圍第40項之多晶片封裝，其中：該第二主動晶粒係使用線焊而附著至該基板。
  42. 如申請專利範圍第41項之多晶片封裝，其中：該第二主動晶粒具有第一區域，第二區域，及第三區域；該第一區域係第一重疊區域，位於該基板與該第一主動晶粒的一部分之間；該第三區域係第二重疊區域，位於該基板與該第三主動晶粒的一部分之間；該第二覆晶連接係設置於該第二主動晶粒的該第一區域之中，且該線焊係在該第二區域中被附著至該第二主動晶粒；以及該第四覆晶連接係設置於該第二主動晶粒的該第三區域之中。
  43. 如申請專利範圍第42項之多晶片封裝，其中：該第二晶粒的該第一區域具有第一區段及第二區段；該第二晶粒的該第三區域具有第三區段及第四區段；該第一區段包含具有第一密度之第一複數個覆晶連接，及該第二區段包含具有第二密度之第二複數個覆晶連接 ，該第二密度係小於該第一密度；以及該第三區段包含具有第三密度之第三複數個覆晶連接，及該第四區段包含具有第四密度之第四複數個覆晶連接，該第四密度係小於該第三密度。
  44. 如申請專利範圍第43項之多晶片封裝，其中：該第二主動晶粒包含電性或光學傳導走線，延伸於該第一區段與該第三區段之間；以及該等電性或光學傳導走線連接該第一主動晶粒至該第三主動晶粒。
  45. 如申請專利範圍第40項之多晶片封裝，其中：該基板包含空穴；以及該第二主動晶粒係至少部分地設置於該空穴之中。
  46. 如申請專利範圍第40項之多晶片封裝，其中：該基板具有第一側、相對的第二側、及第三側，該第三側自該第一側延伸至該第二側；該第一主動晶粒及該第二主動晶粒係附著至該基板之該第一側；以及該基板不具有在該第二主動晶粒之下面的部分。
  47. 一種提供多晶片封裝中之晶粒至晶粒互連之方法，該方法包含：提供基板；使用第一覆晶連接以附著第一主動晶粒至該基板：使用第二覆晶連接以附著第二主動晶粒至該基板；使用第三覆晶於該基板的外周邊的一部分處連接以附 著第三主動晶粒至該第一主動晶粒；使用第四覆晶於該基板的外周邊的一部分處連接以附著該第三主動晶粒至該第二主動晶粒；以及附著該第三主動晶粒至該基板。
  48. 如申請專利範圍第47項之方法，其中：該第三主動晶粒係使用線焊而附著至該基板。
TW099109406A 2009-06-24 2010-03-29 多晶片封裝及提供多晶片封裝中之晶粒至晶粒互連之方法 TWI455279B (zh)

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