JP5947387B2 - 3d集積回路積層体の層間通信 - Google Patents
3d集積回路積層体の層間通信 Download PDFInfo
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- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
Description
本実施形態の例を下記の各項目として示す。
[項目1]
同じ方向に向くアクティブ表面を有する2つ以上の積層ダイ層と、
前記2つ以上の積層ダイ層を貫通し、関連するキャパシタンスを有する少なくとも1つのインターコネクトと、
前記2つ以上の積層ダイ層のうちの少なくとも1つの上の少なくとも1つの受信機及び前記2つ以上の積層ダイ層のうちの少なくとも1つの上の少なくとも1つの送信機と、を備え、前記少なくとも1つの送信機は、結合キャパシタを通して前記少なくとも1つのインターコネクトに接続され、前記少なくとも1つの送信機及び前記少なくとも1つの受信機は、AC結合によって前記少なくとも1つのインターコネクトを通して互いに結合される、装置。
[項目2]
前記少なくとも1つの受信機は、フィードバックキーパー回路要素を備える、項目1に記載の装置。
[項目3]
前記少なくとも1つの受信機は差動受信機である、項目2に記載の装置。
[項目4]
前記少なくとも1つのインターコネクトは貫通シリコンビアを含む、項目1から3の何れか1項に記載の装置。
[項目5]
前記少なくとも1つのインターコネクトは部分接続式貫通シリコンビアを含む、項目1から3の何れか1項に記載の装置。
[項目6]
前記結合キャパシタは、前記少なくとも1つのインターコネクトの回りに同軸的に配設された導電性ピースから形成される、項目1から5の何れか1項に記載の装置。
[項目7]
TX結合キャパシタは、前記関連するインターコネクトキャパシタンスより小さいキャパシタンスを有する、項目1から6の何れか1項に記載の装置。
[項目8]
結合キャパシタを使用することなく、前記少なくとも1つのインターコネクトに直接結合された少なくとも1つの受信機を備える、項目1から7の何れか1項に記載の装置。
[項目9]
前記少なくとも1つのインターコネクトに直接結合された少なくとも1つの送信機を備える、項目1から8の何れか1項に記載の装置。
[項目10]
前記2つ以上の積層ダイ層は、結合キャパシタによって互いから絶縁された異なるDCバイアス印加レベルを必要とするコアロジック層及び1つ又は複数のメモリ層を備える、項目1から9の何れか1項に記載の装置。
[項目11]
異なる技術のコアロジック層及び1つ又は複数のメモリ層を含む少なくとも2つの集積回路(IC)層と、
前記少なくとも2つの層を互いに通信可能にリンクするバスと、を備え、前記バスは、前記少なくとも3つの層を貫通して接続された1つ又は複数のインターコネクトを含み、各層は、結合キャパシタを通して前記1つ又は複数のインターコネクトに結合された少なくとも1つのバスインタフェースを含む、装置。
[項目12]
少なくとも2つの層用のバスインタフェースは異なるDCレベルにバイアスされる、項目11に記載の装置。
[項目13]
前記バスインタフェースは、前記結合キャパシタを通して前記1つ又は複数のインターコネクトに結合された送信機及び受信機を備える、項目11または12に記載の装置。
[項目14]
前記結合キャパシタは、前記1つ又は複数のインターコネクトのキャパシタンスより小さいキャパシタンスを有し、受信機によって見られるAC信号スイングは、関連する送信機によって送信されるスイングレベルから分圧される、項目11から13の何れか1項に記載の装置。
[項目15]
前記結合キャパシタはオンダイ金属キャパシタンスによって実装される、項目11から14の何れか1項に記載の装置。
[項目16]
前記結合キャパシタはMIMキャパシタによって実装される、項目11から14の何れか1項に記載の装置。
[項目17]
前記結合キャパシタは、2つの隣接するTSVを使用して実装されたキャパシタによって実装される、項目11から14の何れか1項に記載の装置。
[項目18]
前記結合キャパシタは、再分配層内で実装されたキャパシタによって実装される、項目11から14の何れか1項に記載の装置。
[項目19]
前記結合キャパシタは、TSVと同軸的に配設された電極によって実装される、項目11から14の何れか1項に記載の装置。
[項目20]
前記結合キャパシタは、ダイ間キャパシタとして実装される、項目11から14の何れか1項に記載の装置。
[項目21]
同じ方向に向くアクティブ表面を有する2つ以上の積層ダイ層と、
前記2つ以上の積層ダイ層を貫通し、関連するキャパシタンスを有する少なくとも1つのインターコネクトと、
前記2つ以上の積層ダイ層上の受信機及び送信機と、を備え、前記受信機の少なくとも1つは結合キャパシタを通して前記少なくとも1つのインターコネクトに接続され、前記送信機及び前記受信機は、AC結合によって前記少なくとも1つのインターコネクトを通して互いに結合される、装置。
[項目22]
前記少なくとも1つの受信機は、フィードバックキーパー回路要素を備える、項目21に記載の装置。
[項目23]
送信機結合キャパシタは、前記関連するインターコネクトキャパシタンスより小さいキャパシタンスを有する、項目21または22に記載の装置。
[項目24]
前記送信機の少なくとも1つは、結合キャパシタを通して前記少なくとも1つのインターコネクトに接続される、項目21から23の何れか1項に記載の装置。
Claims (16)
- 同じ方向に向くアクティブ表面を有し、コアロジック層及び1つ又は複数のメモリ層を備える2つ以上の積層ダイ層と、
前記2つ以上の積層ダイ層を貫通し、関連するキャパシタンスを有する少なくとも1つのインターコネクトと、
前記1つ又は複数のメモリ層上の受信機及び送信機と、
前記コアロジック層上の受信機及び送信機と、を備え、
前記1つ又は複数のメモリ層の前記受信機及び前記送信機は、結合キャパシタを通して前記少なくとも1つのインターコネクトに接続され、前記1つ又は複数のメモリ層の前記送信機及び前記受信機は、AC結合によって前記少なくとも1つのインターコネクトを通して互いに結合され、
前記コアロジック層の前記送信機は、結合キャパシタを通して前記少なくとも1つのインターコネクトに接続され、前記コアロジック層の前記受信機は、前記少なくとも1つのインターコネクトに直接結合される、
装置。 - 前記受信機は、フィードバックキーパー回路要素を備える、請求項1に記載の装置。
- 前記受信機は差動受信機である、請求項2に記載の装置。
- 前記少なくとも1つのインターコネクトは貫通シリコンビアを含む、請求項1から3の何れか1項に記載の装置。
- 前記少なくとも1つのインターコネクトは部分接続式貫通シリコンビアを含む、請求項1から3の何れか1項に記載の装置。
- 前記結合キャパシタは、前記少なくとも1つのインターコネクトの回りに同軸的に配設された導電性プレートから形成される、請求項1から5の何れか1項に記載の装置。
- 前記結合キャパシタは、前記関連するインターコネクトキャパシタンスより小さいキャパシタンスを有する、請求項1から6の何れか1項に記載の装置。
- コアロジック層及び1つ又は複数のメモリ層を含む少なくとも2つの集積回路(IC)層と、
前記少なくとも2つの層を互いに通信可能にリンクするバスと、を備え、
前記バスは、前記少なくとも3つの層を貫通して接続された1つ又は複数のインターコネクトを含み、各層は、前記1つ又は複数のインターコネクトに結合された送信機及び受信機を備えた、少なくとも1つのバスインタフェースを含み、
前記1つ又は複数のメモリ層の前記送信機及び前記受信機は、結合キャパシタを通して前記1つ又は複数のインターコネクトに結合され、
前記コアロジック層の前記送信機は、結合キャパシタを通して前記1つ又は複数のインターコネクトに接続され、前記コアロジック層の前記受信機は、前記1つ又は複数のインターコネクトに直接結合される、
装置。 - 少なくとも2つの層用のバスインタフェースは異なるDCレベルにバイアスされる、請求項8に記載の装置。
- 前記結合キャパシタは、前記1つ又は複数のインターコネクトのキャパシタンスより小さいキャパシタンスを有し、受信機によって見られるAC信号スイングは、関連する送信機によって送信されるスイングレベルから分圧される、請求項8または9に記載の装置。
- 前記結合キャパシタはオンダイ金属キャパシタンスによって実装される、請求項8から10の何れか1項に記載の装置。
- 前記結合キャパシタはMIMキャパシタによって実装される、請求項8から10の何れか1項に記載の装置。
- 前記結合キャパシタは、2つの隣接するTSVを使用して実装されたキャパシタによって実装される、請求項8から10の何れか1項に記載の装置。
- 前記結合キャパシタは、再分配層内で実装されたキャパシタによって実装される、請求項8から10の何れか1項に記載の装置。
- 前記結合キャパシタは、TSVと同軸的に配設された電極によって実装される、請求項8から10の何れか1項に記載の装置。
- 前記結合キャパシタは、ダイ間キャパシタとして実装される、請求項8から10の何れか1項に記載の装置。
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PCT/US2011/054440 WO2013048501A1 (en) | 2011-09-30 | 2011-09-30 | Interlayer communications for 3d integrated circuit stack |
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JP5947387B2 true JP5947387B2 (ja) | 2016-07-06 |
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US (2) | US9000577B2 (ja) |
EP (1) | EP2761655B1 (ja) |
JP (1) | JP5947387B2 (ja) |
KR (1) | KR101589843B1 (ja) |
CN (1) | CN103828046B (ja) |
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WO (1) | WO2013048501A1 (ja) |
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EP2509075B1 (en) * | 2006-12-14 | 2019-05-15 | Rambus Inc. | Multi-die memory device |
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US9000577B2 (en) | 2015-04-07 |
TWI476863B (zh) | 2015-03-11 |
KR101589843B1 (ko) | 2016-01-28 |
EP2761655A1 (en) | 2014-08-06 |
WO2013048501A1 (en) | 2013-04-04 |
EP2761655A4 (en) | 2015-04-15 |
CN103828046A (zh) | 2014-05-28 |
EP2761655B1 (en) | 2021-10-20 |
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US20150130534A1 (en) | 2015-05-14 |
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