WO2011007507A1 - 半導体パッケージ用基板および半導体パッケージ用基板の製造方法 - Google Patents
半導体パッケージ用基板および半導体パッケージ用基板の製造方法 Download PDFInfo
- Publication number
- WO2011007507A1 WO2011007507A1 PCT/JP2010/004239 JP2010004239W WO2011007507A1 WO 2011007507 A1 WO2011007507 A1 WO 2011007507A1 JP 2010004239 W JP2010004239 W JP 2010004239W WO 2011007507 A1 WO2011007507 A1 WO 2011007507A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- mounting
- semiconductor element
- substrate
- ground electrode
- semiconductor package
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 226
- 239000000758 substrate Substances 0.000 title claims abstract description 168
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000012212 insulator Substances 0.000 claims abstract description 65
- 239000004020 conductor Substances 0.000 claims description 48
- 229920005989 resin Polymers 0.000 claims description 47
- 239000011347 resin Substances 0.000 claims description 47
- 230000002093 peripheral effect Effects 0.000 claims description 42
- 238000007639 printing Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 230000005855 radiation Effects 0.000 description 27
- 239000000463 material Substances 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 12
- 239000010931 gold Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000002131 composite material Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920001955 polyphenylene ether Polymers 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007649 pad printing Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
Definitions
- the present invention relates to a semiconductor package substrate, a semiconductor package, a method for manufacturing a semiconductor package substrate, and a method for manufacturing a semiconductor package.
- semiconductor packages suitable for high-frequency signal propagation (a structure in which one semiconductor element is mounted on a package substrate) and composite modules (a structure in which a plurality of semiconductor elements are mounted on a module substrate)
- a semiconductor package in which a semiconductor element is connected to a mounting substrate by wire bonding is mainly used.
- high-frequency characteristics cannot be sufficiently obtained due to the inductance component of the wire, and that the performance of the semiconductor package varies due to manufacturing variations in wire length.
- the active surface of the wire-bonded semiconductor element faces upward (face-up mounting), and there is a problem that radiation noise is large. Therefore, in a semiconductor package in which a high-frequency semiconductor element is mounted face-up, a method of covering the semiconductor element with a metal cap for electromagnetic shielding is adopted.
- JP 2002-26178 A Japanese Patent Laid-Open No. 10-92981
- FIG. 18 is a schematic diagram showing a schematic configuration of the semiconductor package 100 shown in Patent Document 1.
- the conductor 103 needs to be connected to the ground electrode on the surface of the mounting substrate 101 (the surface facing the semiconductor element 102).
- An electrode other than the ground electrode such as a signal line cannot be provided.
- the mounting substrate 101 in the semiconductor package 100 has a laminated structure of a plurality of layers in which via holes are formed so as to route signal lines to the outside (the back surface of the mounting substrate 101).
- FIG. 19 is a schematic diagram showing a schematic configuration of the semiconductor package 200 shown in Patent Document 2.
- the semiconductor package 200 has a structure in which the conductor 204 covers the side surface of the underfill resin 203 and the side surface of the semiconductor element 202.
- the conductor 204 covers the side surface of the underfill resin 203 and the side surface of the semiconductor element 202.
- the present invention has been made in view of such circumstances, and a semiconductor package substrate, a semiconductor package, and a semiconductor package capable of suppressing leakage of radiation noise from a gap between a semiconductor element and a mounting substrate.
- An object of the present invention is to provide a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor package.
- a substrate for a semiconductor package according to the present invention includes a signal electrode flip-chip connected to the semiconductor element via a bump on a mounting substrate on which the semiconductor element is mounted, and both sides of the signal electrode.
- a coplanar line having a ground electrode provided at a distance from each other, and the ground electrode in the outer peripheral portion of the mounting region of the semiconductor element has a distance between the top surface of the mounting substrate and the top surface of the ground electrode.
- a stepped portion that is larger in the outer peripheral portion of the mounting region than in the mounting region is formed, and an insulator is formed to cover the signal electrode in the outer peripheral portion of the mounting region.
- the step portion is formed on the ground electrode in the outer peripheral portion of the mounting region of the semiconductor element on the mounting substrate, and the insulator is formed to cover the signal electrode in the outer peripheral portion of the mounting region.
- a ground electrode and an insulator can be used as a base so as not to contact the signal electrode. Further, the conductor can be formed on the ground electrode and the insulator without any gap. Therefore, when the semiconductor element is mounted on the mounting substrate, it is possible to suppress leakage of radiation noise from the gap between the semiconductor element and the mounting substrate.
- FIG. 2 is a cross-sectional view taken along line X1-X1 ′ of FIG.
- FIG. 2 is a cross-sectional view taken along line X2-X2 ′ of FIG.
- FIG. 2 is a cross-sectional view taken along line Y1-Y1 ′ of FIG.
- FIG. 2 is a cross-sectional view taken along line Y2-Y2 ′ of FIG.
- FIG. 7 is a cross-sectional view taken along line X3-X3 ′ of FIG.
- FIG. 7 is a cross-sectional view taken along line X4-X4 ′ of FIG.
- FIG. 7 is a cross-sectional view taken along line Y3-Y3 ′ of FIG. It is process drawing which shows the manufacturing process of the semiconductor package of this invention.
- FIG. 11 is a process diagram following FIG. 10.
- FIG. 12 is a process diagram following FIG. 11. It is a schematic diagram which shows the cross-sectional structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows the cross-sectional structure of the semiconductor device which concerns on Embodiment 3 of this invention.
- FIG. 16 is a process drawing following FIG. 15.
- FIG. 17 is a cross-sectional view taken along line X5-X5 ′ of FIG. It is a figure which shows the cross-sectional structure of the semiconductor package which concerns on patent document 1.
- FIG. It is a figure which shows the cross-sectional structure of the semiconductor package which concerns on patent document 2.
- FIG. 11 is a process diagram following
- FIG. 1 is a plan view showing a semiconductor package substrate 20.
- 2 is a cross-sectional view taken along line X1-X1 ′ of FIG. 3 is a cross-sectional view taken along line X2-X2 ′ of FIG. 4 is a cross-sectional view taken along line Y1-Y1 ′ of FIG.
- FIG. 5 is a sectional view taken along line Y2-Y2 ′ of FIG.
- the semiconductor package substrate 20 of the present embodiment has a rectangular shape in plan view, and the signal electrode 3 and the ground electrode 2 are formed on the mounting substrate 6.
- the ground electrode 2 is provided on both sides of the signal electrode 3 so as to be spaced from the signal electrode 3, and the signal electrode 3 and the ground electrode 2 form a coplanar line (CPW; coplanar waveguide).
- CPW coplanar line
- the central part on the mounting substrate 6 there is a mounting region S where a semiconductor element 7 (see FIG. 6) described later is mounted.
- a blanking pattern P (opening region) having a rectangular shape in plan view is formed in the mounting region S of the coplanar line on the mounting substrate 6.
- the outer peripheral portion of the extraction pattern P in the mounting region S is a connection region where the semiconductor element 7 is connected to electrodes (the signal electrode 3 and the ground electrode) via bumps 9 (see FIG. 7) described later. Further, a step portion 4 is formed on the ground electrode 2 in the outer peripheral portion of the mounting region S on the mounting substrate 6.
- the ground electrode 2 and the signal electrode 3 are shown as coplanar lines on the mounting substrate 6, but other electrodes such as a power supply electrode may be provided.
- a high-frequency signal can be propagated while suppressing transmission loss.
- the signal electrode 3 and the ground electrode 2 are concentrated on the element formation surface of the mounting substrate 6 (the surface on which the semiconductor element 7 is mounted), the surface opposite to the element formation surface is formed. An electrode becomes unnecessary. As a result, it is not necessary to provide via holes for electrically connecting the ground electrode 2 and the signal electrode 3 to the mounting substrate 6. Therefore, high-frequency signals can be propagated without via holes, and transmission loss can be reduced.
- the substrate used for the mounting substrate 6 is not particularly limited.
- a printed substrate, an organic substrate, or a ceramic substrate can be used, but a printed substrate mainly composed of polyphenylene ether (PPE), which is a material having a low dielectric loss at high frequencies.
- PPE polyphenylene ether
- LCP liquid crystal polymer
- LTCC low temperature co-fired ceramic
- the material for forming the electrode is not particularly limited.
- copper (Cu) is preferable for an organic substrate
- silver-palladium (Ag—Pd) alloy is preferable for an LTCC substrate.
- the surface treatment of the electrode is not particularly limited.
- a gold (Au) plating process suitable for flip chip connection of the semiconductor element 7 is applied to the base via a nickel (Ni) plating barrier.
- the stepped portion 4 is located in the mounting region S more than the thickness T1 of the ground electrode 2 on the mounting region S side (the distance between the upper surface of the mounting substrate 6 and the upper surface of the ground electrode 2 in the mounting region S).
- the thickness T2 (the distance between the upper surface of the mounting substrate 6 and the upper surface of the ground electrode 2 at the outer peripheral portion of the mounting region S) of the ground electrode 2 on the opposite side of the side is formed to be larger (T1 ⁇ T2).
- the semiconductor element 7 when the semiconductor element 7 is mounted on the mounting substrate 6, it is possible to suppress leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6. Specifically, radiated noise generated from the active surface of the semiconductor element 7 is shielded by the step portion 4 serving as an electromagnetic shield wall formed in the outer peripheral portion of the mounting region S on the mounting substrate 6. That is, since the surface of the mounting substrate 6 is not flat, it is possible to suppress radiation noise from propagating along the surface of the mounting substrate 6.
- the height (T2-T1) of the stepped portion 4 is not particularly limited. However, when the underfill resin 10 (see FIG. 7) is formed, the height (dam) is sufficient to prevent the underfill resin 10 from flowing out. Is required). In the present embodiment, the height (T2-T1) of the stepped portion 4 is set within a range of 10 ⁇ m to 30 ⁇ m.
- the thickness T3 of the signal electrode 3 (the distance between the upper surface of the mounting substrate 6 and the upper surface of the signal electrode 3) is the ground electrode 2 on the mounting region S side over the entire area of the mounting substrate 6.
- the thickness is substantially the same as the thickness T1.
- an insulator 5 is formed so as to cover the signal electrode 3.
- the conductor 8 see FIG. 6 as an electromagnetic shield covering the semiconductor element 7
- the ground electrode 2 and the insulator 5 can be used as a base so as not to contact the signal electrode 3.
- the conductor 8 when the conductor 8 is formed after the semiconductor element 7 is mounted, it can be formed on the ground electrode 2 and the insulator 5 without a gap.
- the upper surface of the insulator 5 and the upper surface of the ground electrode 2 become flat, so that when the conductor 8 is formed after the semiconductor element 7 is mounted, the insulator 5 and the ground electrode 2 can be provided without any unevenness on the ground. .
- the thickness T4 of the insulator 5 (distance between the top surface of the mounting substrate 6 and the top surface of the insulator 5) is not particularly limited, but the height of the dam is the same as the height of the step portion 4 (T2-T1). is required. In the present embodiment, the thickness T4 of the insulator 5 is set within a range of 10 ⁇ m to 30 ⁇ m.
- a material for forming the insulator 5 is not particularly limited. For example, a solder resist material is suitable for an organic substrate, and a substrate material can be used for an LTCC substrate.
- the side surface portion of the insulator 5 on the side facing the mounting region S and the step portion 4 are connected.
- the surface on the mounting region S side becomes flat as a whole of the insulator 5 and the stepped portion 4, and therefore, when the underfill resin 10 is formed after mounting the semiconductor element 7, the outflow from the dam is surely prevented. be able to.
- the insulator 5 is formed so as to fill a gap between the signal electrode 3 and the ground electrode 2 on the mounting substrate 6 in the outer peripheral portion of the mounting region S. As a result, the insulator 5 covering the signal electrode 3 and the ground electrode 2 are formed without a gap. Therefore, when the conductor 8 is formed after the semiconductor element 7 is mounted, the conductor 8 flows through the gap and the signal electrode 3 is formed. Can be prevented from touching. Further, the conductor 8 can be reliably formed on the insulator 5 and the ground electrode 2 without a gap.
- FIG. 6 to 9 are schematic views showing the semiconductor package 1 according to the first embodiment of the present invention.
- FIG. 6 is a plan view showing the semiconductor package 1.
- FIG. 7 is a cross-sectional view taken along line X3-X3 ′ of FIG.
- FIG. 8 is a cross-sectional view taken along line X4-X4 ′ of FIG.
- FIG. 9 is a cross-sectional view taken along line Y3-Y3 ′ of FIG.
- the semiconductor package 1 of the present embodiment is fixed on the above-described semiconductor package substrate 20 with bumps 9 with the circuit formation surface (active surface) of the semiconductor element 7 facing down.
- the material for forming the bumps 9 is not particularly limited, but gold (Au) stud bumps and solder bumps are preferably used. Further, the type and size of the semiconductor element 7 and the size and pitch of the bumps 9 are not particularly limited.
- a step portion 4 is formed on the ground electrode 2 and an insulator 5 is formed so as to cover the signal electrode 3 in the outer peripheral portion of the mounting region S in the semiconductor package substrate 20 described above. For this reason, radiation noise generated from the active surface of the semiconductor element 7 is shielded by the stepped portion 4 serving as an electromagnetic shield wall formed in the outer peripheral portion of the mounting region S on the mounting substrate 6.
- the semiconductor package 1 is fixed by filling the underfill resin 10 between the semiconductor element 7 and the mounting substrate 6.
- the underfill resin 10 is formed up to a position reaching the stepped portion 4 of the ground electrode 2 and the side surface of the insulator 5 (the surface on the mounting region S side), and a gap between the semiconductor element 7 and the mounting substrate 6 is formed. It is blocking.
- the contraction force of the underfill resin 10 strengthens the connection state of the bumps 9 and reduces the thickness of the bumps 9 (the distance between the upper surface of the electrode and the circuit formation surface of the semiconductor element 7). For this reason, the transmission loss of a high frequency signal can be reduced.
- the material for forming the underfill resin 10 is not particularly limited, but a smaller thermal expansion difference from the semiconductor element 7 is preferable, and a material made of a composite of an inorganic filler and an organic resin is preferable.
- the underfill resin 10 needs to be sufficiently filled without generating voids even when the input / output terminal pitch of the semiconductor element 7 is miniaturized to 150 ⁇ m or less and the distance between the bumps 9 is small. Further, when the underfill resin 10 is filled, it is necessary to prevent the semiconductor element 7 and the mounting substrate 6 from being damaged.
- a material composed of a composite of an inorganic filler (maximum particle size of 5 ⁇ m or less, 40-60 wt%) and an organic resin is suitable as a material for forming the underfill resin 10. .
- the conductor 8 is formed in a closed ring shape in plan view and is electrically connected to the ground electrode 2. Specifically, the conductor 8 is formed so as to cover the entire exposed portion of the underfill resin 10 across the semiconductor element 7 and the mounting substrate 6 (the step portion 4 and the insulator 5). Thereby, it is possible to suppress radiation noise from leaking from a minute gap inside the underfill resin 10 or an interface between the active surface of the semiconductor element 7 and the underfill resin 10.
- the material for forming the conductor 8 is not particularly limited.
- a silver paste that is a composite of a silver (Ag) filler and an epoxy resin may be used.
- FIGS. 10 to 12 are process diagrams sequentially showing the manufacturing process of the semiconductor package substrate 20.
- FIG. 10 is an enlarged view when the step portion 4 is formed in the ground electrode 2.
- 11 and 12 are cross-sectional views corresponding to FIG. 8 (cross-sectional views taken along the line X4-X4 ′ in FIG. 6).
- the signal electrode 3 and the ground electrode 2 are formed by patterning the electrode formed on the upper surface of the mounting substrate 6. Specifically, on the upper surface of the mounting substrate 6, the ground electrode 2 is formed on both sides of the signal electrode 3 at a distance from the signal electrode 3, thereby forming a coplanar line with the signal electrode 3 and the ground electrode 2.
- a mask is formed on the ground electrode 2 in the outer peripheral portion of the mounting region S (the portion where the thickness of the ground electrode 2 is to be increased).
- the step portion 4 is formed by etching the ground electrode 2 where the surface where the mask is not formed is exposed.
- the step portion 4 is formed such that the thickness T2 of the ground electrode 2 on the side opposite to the mounting region S side is larger than the thickness T1 of the ground electrode 2 on the mounting region S side (T1 ⁇ T2). .
- the height (T2-T1) of the stepped portion 4 is high enough to prevent the underfill resin 10 from flowing out when the underfill resin 10 is formed after the semiconductor element 7 is mounted (the height of the dam).
- the thickness T3 of the signal electrode 3 is set to be substantially the same as the thickness T1 of the ground electrode 2 on the mounting region S side over the entire area of the mounting substrate 6.
- a nickel (Ni) plating barrier is applied as a base on the upper surfaces of the ground electrode 2 and the signal electrode 3, and further gold (Au) plating is applied thereon.
- the insulator 5 is formed so as to cover the signal electrode 3 in the outer peripheral portion of the mounting region S on the mounting substrate 6.
- the insulator 5 is formed such that the surface on the mounting region S side of the stepped portion 4 formed on the ground electrode 2 and the surface on the mounting region S side of the insulator 5 are in the same plane.
- the thickness T4 of the insulator 5 is required to be a dam height similar to the height (T2-T1) of the stepped portion 4, and is set within a range of 10 ⁇ m to 30 ⁇ m.
- the insulator 5 is formed so as to fill a gap between the signal electrode 3 and the ground electrode 2 on the mounting substrate 6 in the outer peripheral portion of the mounting region S.
- the semiconductor element 7 is flip-chip mounted on the semiconductor package substrate 20 manufactured by the above-described process via the bumps 9 (see FIG. 11).
- the underfill resin 10 is filled between the semiconductor element 7 and the mounting substrate 6 using a dispenser. At this time, the underfill resin 10 can be prevented from flowing out due to the function as a dam of the stepped portion 4 and the insulator 5 in the outer peripheral portion of the mounting region S on the mounting substrate 6.
- the conductor 8 is formed so as to cover the entire exposed portion of the underfill resin 10 across the semiconductor element 7 and the mounting substrate 6 (the stepped portion 4 and the insulator 5). Thereby, it is possible to suppress radiation noise from leaking from a minute gap inside the underfill resin 10 or an interface between the active surface of the semiconductor element 7 and the underfill resin 10.
- the conductor 8 may be formed by printing the above-described conductive paste using a printing method such as a screen printing method or a pad printing method. Since the upper surface of the stepped portion 4 and the upper surface of the insulator 5 in the outer peripheral portion of the mounting region S on the mounting substrate 6 are flat, it is possible to print the conductive paste suitably. Further, by using a simple printing method, the conductor 8 can be formed with a high yield, and the manufacturing cost of the semiconductor package 1 can be reduced.
- a printing method such as a screen printing method or a pad printing method. Since the upper surface of the stepped portion 4 and the upper surface of the insulator 5 in the outer peripheral portion of the mounting region S on the mounting substrate 6 are flat, it is possible to print the conductive paste suitably. Further, by using a simple printing method, the conductor 8 can be formed with a high yield, and the manufacturing cost of the semiconductor package 1 can be reduced.
- the ground electrode 2 is formed on the outer peripheral portion of the mounting region S on the mounting substrate 6.
- a step portion 4 is formed, and an insulator 5 is formed to cover the signal electrode 3 in the outer peripheral portion of the mounting region S.
- the conductor 8 when the conductor 8 is formed as an electromagnetic shield covering the semiconductor element 7, the ground electrode 2 and the insulator 5 can be used as a base so as not to contact the signal electrode 3. Further, the conductor 8 can be formed on the insulator 5 and the ground electrode 2 without a gap. Therefore, when the semiconductor element 7 is mounted on the mounting substrate 6, it is possible to suppress the leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6.
- the surface on the mounting region S side becomes flat as the insulator 5 and the step portion 4 as a whole.
- the conductor 8 can be formed on the underfill resin 10 without a gap. Therefore, when the semiconductor element 7 is mounted on the mounting substrate 6, it is possible to reliably suppress leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6.
- the insulator 5 is formed so as to fill the gap between the signal electrode 3 on the mounting substrate 6 and the ground electrode 2 in the outer peripheral portion of the mounting region S, the insulator 5 covering the signal electrode 3 and the ground The electrode 2 is formed without a gap. For this reason, when the conductor 8 is formed after the semiconductor element 7 is mounted, it is possible to prevent the conductor 8 from flowing through the gap and coming into contact with the signal electrode 3. Further, the conductor 8 can be reliably formed on the insulator 5 and the ground electrode 2 without a gap. Therefore, when the semiconductor element 7 is mounted on the mounting substrate 6, it is possible to reliably suppress leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6.
- an underfill resin 10 is formed between the semiconductor element 7 and the mounting substrate 6. For this reason, the connection state of the bumps 9 is strengthened by the contraction force of the underfill resin 10, and the thickness of the bumps 9 can be reduced. Therefore, the semiconductor package 1 that can reduce the transmission loss of the high-frequency signal can be provided.
- the stepped portion 4 and the insulator 5 are formed on the outer peripheral portion of the mounting region S on the mounting substrate 6.
- the conductor 8 can be formed on the underfill resin 10 without a gap, and the leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6 can be reliably suppressed.
- the conductor 8 can be formed with a high yield, and the manufacturing cost of the semiconductor package 1 can be reduced.
- a semiconductor package using a semiconductor package substrate (a structure in which one semiconductor element is mounted on the package substrate) has been described as an example, but the present invention is not limited to this.
- the present invention can also be applied to a composite module (a structure in which a plurality of semiconductor elements are mounted on a module substrate).
- FIG. 13 is a diagram showing an internal structure of the semiconductor package 1A according to the second embodiment of the present invention.
- FIG. 13 is a cross-sectional view showing a schematic configuration of semiconductor package 1A in the second embodiment corresponding to FIG.
- the conductor 8A is formed so as to cover the entire exposed portion of the semiconductor element 7 on the mounting substrate 6, and thus the first embodiment described above. This is different from the semiconductor package 1 described above. Since the other points are the same as in the first embodiment, the same elements as those in FIG.
- the semiconductor package 1 ⁇ / b> A of the present embodiment is formed so that the conductor 8 ⁇ / b> A that shields radiation noise covers the entire exposed portion of the semiconductor element 7 and the underfill resin 10 on the mounting substrate 6. ing.
- the semiconductor package 1A of the present embodiment has a rectangular shape in plan view, whereas the conductor 8 in the first embodiment has a closed annular shape in plan view.
- the semiconductor package 1 ⁇ / b> A of the present embodiment radiation noise leaks from a minute gap inside the underfill resin 10, an interface between the active surface of the semiconductor element 7 and the underfill resin 10, and an upper surface of the semiconductor element 7. Can be suppressed. Therefore, leakage of radiation noise from the gap between the semiconductor element 7 and the mounting substrate 6 can be reliably suppressed.
- FIG. 14 is a diagram showing an internal structure of the semiconductor package 1B according to the third embodiment of the present invention.
- FIG. 14 is a cross-sectional view showing a schematic configuration of semiconductor package 1B in the third embodiment corresponding to FIG.
- the semiconductor package 1 ⁇ / b> B of the present embodiment has the semiconductor package 1 described in the above-described first embodiment in that a gap 11 is formed between the semiconductor element 7 and the mounting substrate 6. Is different. Since the other points are the same as in the first embodiment, the same elements as those in FIG.
- the semiconductor package 1 ⁇ / b> B of the present embodiment has a hollow structure in which a gap 11 is formed between the semiconductor element 7 and the mounting substrate 6.
- the underfill resin 10 ⁇ / b> B is formed in the connection region of the bump 9 between the semiconductor element 7 and the mounting substrate 6.
- the semiconductor package 1B of the present embodiment has a closed ring shape in plan view, whereas the underfill resin 10B of the first embodiment has a rectangular shape in plan view.
- the dielectric constant of air in the air gap 11 is the dielectric of the underfill resin 10 in the first embodiment. Smaller than the rate.
- the dielectric constant between the semiconductor element 7 and the mounting substrate 6 even when the passivation of the semiconductor element 7 is thin, the high-frequency characteristics are not deteriorated and the reliability of the connection of the semiconductor element 7 is ensured. It is also possible to suppress the leakage of radiation noise from the gap between the mounting board 6 and the mounting board 6.
- the inventor of the present application conducted an experiment to verify the effect of the substrate for a semiconductor package of the present invention. Specifically, by the method for manufacturing a substrate for a semiconductor package of the present invention, an electromagnetic shield wall is formed by forming a stepped portion on the ground electrode and forming an interval covering both sides of the signal electrode and an insulator covering the signal electrode. This proves that leakage of radiation noise can be suppressed.
- the experimental results will be described.
- the substrate for a semiconductor package of this example is a stepped portion (height) formed on a ground electrode by a manufacturing method as described above based on a printed circuit board having a thickness of 35 ⁇ m as a mounting substrate and a coplanar line mainly composed of PPE with copper foil. 22 ⁇ m) pattern was formed.
- the surface of the electrode was subjected to surface treatment in the order of nickel (thickness 3 ⁇ m) and gold (thickness 0.5 ⁇ m).
- a solder resist material (thickness: 20 ⁇ m) was used as a gap between both sides of the signal electrode and an insulator covering the signal electrode.
- As the semiconductor element an element having a size of 4 mm ⁇ 2 mm ⁇ 200 ⁇ m was used.
- the area of the electromagnetic shield wall in the stepped portion and the insulator on the mounting substrate was 4.5 mm ⁇ 2.5 mm.
- a semiconductor package was manufactured by the above-described semiconductor package manufacturing method as follows.
- a gold bump (diameter 80 ⁇ m) was used.
- Flip chip connection between the mounting substrate and the semiconductor element was performed by Au—Au connection with a gold bump pitch of 150 ⁇ m.
- An underfill resin was formed between the mounting substrate and the semiconductor element by filling the underfill resin forming material with a dispenser and curing at a temperature of 150 ° C. for 30 minutes.
- the material for forming the underfill resin is a composite of a filler (maximum particle size 3 ⁇ m, concentration 50 wt%) and an epoxy resin.
- a silver paste was formed as a conductor using a printing method.
- the semiconductor package of the comparative example was flip-chip connected between the mounting substrate and the semiconductor element based on the same mounting substrate as in the above example.
- the difference from the semiconductor package of the above embodiment is that the pattern of the stepped portion is not formed on the ground electrode, the interval on both sides of the signal electrode, and the insulator covering the signal electrode It is a point that is not formed.
- the radiation noise in the semiconductor package of an Example was measured on the basis of the comparative example. As a result, it has been found that leakage of radiation noise from between the semiconductor element which is the largest radiation noise source in the semiconductor package and the mounting substrate (side of the bump) can be suppressed.
- the formation state of the underfill resin in the semiconductor device of the example was confirmed based on the comparative example.
- the underfill resin spread into an indefinite shape as shown in FIG.
- the underfill resin could be formed without protruding from the outer peripheral portion of the mounting region due to the effect of the dam formed by the step portion and the insulator.
- the formation state of the conductor in the semiconductor package of the example was confirmed based on the comparative example.
- the conductor spreads over a wide range.
- the conductor could be formed in a closed annular shape in plan view without protruding to the outer peripheral portion of the mounting region.
- the underfill resin and the conductor are formed so as to spread over a wide range, so that impedance mismatch occurs in the coplanar line, resulting in a large signal transmission loss.
- the underfill resin and the conductor are formed without protruding from the outer peripheral portion of the mounting region, so that the signal transmission loss can be reduced without causing impedance mismatch in the coplanar line. It was.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
(実施の形態1)
図1~5は本発明の実施の形態1に係る半導体パッケージ用基板20を示す模式図である。図1は、半導体パッケージ用基板20を示す平面図である。図2は、図1のX1-X1'線に沿った断面図である。図3は、図1のX2-X2'線に沿った断面図である。図4は、図1のY1-Y1'線に沿った断面図である。図5は、図1のY2-Y2'線に沿った断面図である。
図6~9は本発明の実施の形態1に係る半導体パッケージ1を示す模式図である。図6は、半導体パッケージ1を示す平面図である。図7は、図6のX3-X3'線に沿った断面図である。図8は、図6のX4-X4'線に沿った断面図である。図9は、図6のY3-Y3'線に沿った断面図である。
次に、本実施の形態に係る半導体パッケージ1における半導体パッケージ用基板20の製造方法を図10~12及び図8を用いて説明する。図10~12は、半導体パッケージ用基板20の製造工程を順を追って示す工程図である。なお、図10は、接地電極2に段差部4を形成したときの拡大図である。また、図11及び図12は、図8に対応した断面図(図6のX4-X4'線に沿った断面図)である。
次に、上述の工程により製造された半導体パッケージ用基板20上にバンプ9を介して半導体素子7をフリップチップ実装する(図11参照)。
図13は、本発明の実施の形態2に係る半導体パッケージ1Aの内部構造を示す図である。図13は、図7に対応した、実施の形態2における半導体パッケージ1Aの概略構成を示した断面図である。図13に示すように、本実施の形態の半導体パッケージ1Aは、実装基板6上の半導体素子7の露出する部位全体を覆って導電体8Aが形成されている点で、上述の実施の形態1で説明した半導体パッケージ1と異なっている。その他の点は実施の形態1と同様であるので、図7と同様の要素には同一の符号を付し、詳細な説明は省略する。
図14は、本発明の実施の形態3に係る半導体パッケージ1B内部構造を示す図である。図14は、図7に対応した、実施の形態3における半導体パッケージ1Bの概略構成を示した断面図である。図14に示すように、本実施の形態の半導体パッケージ1Bは、半導体素子7と実装基板6との間に空隙11が形成されている点で、上述の実施の形態1で説明した半導体パッケージ1と異なっている。その他の点は実施の形態1と同様であるので、図7と同様の要素には同一の符号を付し、詳細な説明は省略する。
本実施例の半導体パッケージ用基板は、実装基板として厚さ35μm、銅箔付きのPPEを主成分とするコプレーナ線路を有するプリント基板をベースとして、上述の製造方法によって接地電極に段差部(高さ22μm)のパターンを形成した。電極の表面には、ニッケル(厚さ3μm)、金(厚さ0.5μm)の順で表面処理を施した。信号電極の両側の間隔及び信号電極を覆う絶縁体としてはソルダーレジスト材(厚さ20μm)を用いた。半導体素子としては、サイズ4mm×2mm×200μmの素子を用いた。実装基板上の段差部と絶縁体とにおける電磁シールド壁のエリアは、4.5mm×2.5mmとした。
2:接地電極
3:信号電極
4:段差部
5:絶縁体
6:実装基板
7:半導体素子
8:導電体
9:バンプ
10:アンダーフィル樹脂
11:空隙
20:半導体パッケージ用基板
S:実装領域
T1:実装領域の外周部における接地電極の厚さ(実装領域の外周部における実装基板上面と接地電極上面との間の距離)
T2:実装領域における接地電極の厚さ(実装領域における実装基板上面と接地電極上面との間の距離)
T4:絶縁体の厚さ(実装基板上面と絶縁体上面との間の距離)
Claims (15)
- 半導体素子が実装される実装基板上に、該半導体素子にバンプを介してフリップチップ接続される信号電極と、該信号電極の両側に間隔をあけて設けられた接地電極と、を有するコプレーナ線路を有し、
前記半導体素子の実装領域の外周部における前記接地電極には前記実装基板上面と前記接地電極上面との間の距離が前記実装領域よりも前記実装領域の外周部において大きくなる段差部が形成され、かつ、前記実装領域の外周部における前記信号電極を覆って絶縁体が形成されていることを特徴とする半導体パッケージ用基板。 - 前記実装基板上面と前記絶縁体上面との間の距離が、前記実装領域の外周部における前記実装基板上面と前記接地電極上面との間の距離と同じになっていることを特徴とする請求項1に記載の半導体パッケージ用基板。
- 前記実装領域に面する側の前記絶縁体の側面部と前記段差部とが連接していることを特徴とする請求項1または2に記載の半導体パッケージ用基板。
- 前記絶縁体が前記実装領域の外周部における前記信号電極と前記接地電極との間隔を埋めるように形成されていることを特徴とする1~3のいずれか1項に記載の半導体パッケージ用基板。
- 半導体素子が実装された実装基板と、
前記実装基板上に設けられ、前記半導体素子にバンプを介してフリップチップ接続された信号電極と、該信号電極の両側に間隔をあけて設けられた接地電極と、を有するコプレーナ線路と、を有し、
前記半導体素子の実装領域の外周部における前記接地電極には前記実装基板上面と前記接地電極上面との間の距離が前記実装領域よりも前記実装領域の外周部において大きくなる段差部が形成され、かつ、前記実装領域の外周部における前記信号電極を覆って絶縁体が形成され、
前記信号電極と接触しないように前記接地電極と前記絶縁体とを下地にして前記半導体素子と前記実装基板との間の隙間を塞ぐ導電体が形成されていることを特徴とする半導体パッケージ。 - 前記実装基板上面と前記絶縁体上面との間の距離が、前記実装領域の外周部における前記実装基板上面と前記接地電極上面との間の距離と同じになっていることを特徴とする請求項5に記載の半導体パッケージ。
- 前記実装領域に面する側の前記絶縁体の側面部と前記段差部とが連接していることを特徴とする請求項5または6に記載の半導体パッケージ。
- 前記絶縁体が前記実装領域の外周部における前記信号電極と前記接地電極との間隔を埋めるように形成されていることを特徴とする5~7のいずれか1項に記載の半導体パッケージ。
- 前記半導体素子と前記実装基板との間における少なくとも前記バンプの接続領域にはアンダーフィル樹脂が形成されていることを特徴とする請求項5~8のいずれか1項に記載の半導体パッケージ。
- 前記実装基板上の前記半導体素子の露出する部位全体を覆って導電体が形成されていることを特徴とする請求項5~9のいずれか1項に記載の半導体パッケージ。
- 前記半導体素子と前記実装基板との間には空隙が形成されていることを特徴とする請求項5~10のいずれか1項に記載の半導体パッケージ。
- 半導体素子が実装される実装基板上に形成された電極をパターニングすることにより、信号電極と、該信号電極の両側に間隔をあけて設けられた接地電極と、を有するコプレーナ線路を形成する工程と、
前記半導体素子の実装領域の外周部における前記接地電極上にマスクを形成し、該マスクが形成されていない領域の前記接地電極をエッチングすることにより前記実装基板上面と前記接地電極上面との間の距離が前記実装領域よりも前記実装領域の外周部において大きくなる段差部を形成する工程と、
前記実装領域の外周部における前記信号電極を覆って絶縁体を形成する工程と、
を有することを特徴とする半導体パッケージ用基板の製造方法。 - 半導体素子が実装される実装基板上に形成された電極をパターニングすることにより、信号電極と、該信号電極の両側に間隔をあけて設けられた接地電極と、を有するコプレーナ線路を形成する工程と、
前記半導体素子の実装領域の外周部における前記接地電極上にマスクを形成し、該マスクが形成されていない領域の前記接地電極をエッチングすることにより前記実装基板上面と前記接地電極上面との間の距離が前記実装領域よりも前記実装領域の外周部において大きくなる段差部を形成する工程と、
前記実装領域の外周部における前記信号電極を覆って絶縁体を形成する工程と、
前記半導体素子を前記実装基板上にバンプを介してフリップチップ接続することにより実装する半導体素子実装工程と、
前記信号電極と接触しないように前記接地電極と前記絶縁体とを下地にして前記半導体素子と前記実装基板との間の隙間を塞ぐ導電体を形成する導電体形成工程と、
を有することを特徴とする半導体パッケージの製造方法。 - 前記半導体素子実装工程と前記導電体形成工程との間に、前記半導体素子と前記実装基板との間にアンダーフィル樹脂を充填する工程を有することを特徴とする請求項13に記載の半導体パッケージの製造方法。
- 前記導電体形成工程において、前記導電体を導電ペーストを用いて印刷法により形成することを特徴とする請求項13または14に記載の半導体パッケージの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/383,895 US8531023B2 (en) | 2009-07-17 | 2010-06-25 | Substrate for semiconductor package and method of manufacturing thereof |
JP2011522699A JPWO2011007507A1 (ja) | 2009-07-17 | 2010-06-25 | 半導体パッケージ用基板および半導体パッケージ用基板の製造方法 |
US13/958,989 US8802496B2 (en) | 2009-07-17 | 2013-08-05 | Substrate for semiconductor package and method of manufacturing thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009168831 | 2009-07-17 | ||
JP2009-168831 | 2009-07-17 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/383,895 A-371-Of-International US8531023B2 (en) | 2009-07-17 | 2010-06-25 | Substrate for semiconductor package and method of manufacturing thereof |
US13/958,989 Division US8802496B2 (en) | 2009-07-17 | 2013-08-05 | Substrate for semiconductor package and method of manufacturing thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011007507A1 true WO2011007507A1 (ja) | 2011-01-20 |
Family
ID=43449119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/004239 WO2011007507A1 (ja) | 2009-07-17 | 2010-06-25 | 半導体パッケージ用基板および半導体パッケージ用基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8531023B2 (ja) |
JP (1) | JPWO2011007507A1 (ja) |
WO (1) | WO2011007507A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019046878A (ja) * | 2017-08-30 | 2019-03-22 | 富士通株式会社 | 電子装置、及び、電子装置の製造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102884619B (zh) * | 2010-07-30 | 2016-08-17 | 京瓷株式会社 | 电子部件收纳用部件、电子模块及电子装置 |
US9627346B2 (en) * | 2013-12-11 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill pattern with gap |
US9485671B2 (en) * | 2014-02-27 | 2016-11-01 | Azurewave Technologies, Inc. | Inter-stage test structure for wireless communication apparatus |
US10586716B2 (en) | 2017-06-09 | 2020-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
US11342277B2 (en) * | 2020-06-10 | 2022-05-24 | Micron Technology, Inc. | Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07254661A (ja) * | 1994-03-15 | 1995-10-03 | Toshiba Corp | マイクロ波集積回路 |
JP2000031708A (ja) * | 1998-07-16 | 2000-01-28 | Toshiba Corp | モノリシックマイクロ波集積回路 |
JP2000357763A (ja) * | 1999-04-13 | 2000-12-26 | Nec Corp | 高周波回路基板 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1092981A (ja) | 1996-09-17 | 1998-04-10 | Toshiba Corp | 半導体装置の導電性モールドパッケージ |
JPH11214580A (ja) * | 1998-01-21 | 1999-08-06 | Kyocera Corp | 高周波素子収納用パッケージ |
JP3410673B2 (ja) * | 1999-03-15 | 2003-05-26 | 日本無線株式会社 | 半導体装置及び半導体チップの実装方法 |
JP3282608B2 (ja) * | 1999-03-23 | 2002-05-20 | 日本電気株式会社 | 多層基板 |
JP3346752B2 (ja) * | 1999-11-15 | 2002-11-18 | 日本電気株式会社 | 高周波パッケージ |
JP2002026178A (ja) | 2000-07-04 | 2002-01-25 | Hitachi Ltd | 半導体装置及びその製造方法並びに電子装置 |
US6787919B2 (en) * | 2001-12-27 | 2004-09-07 | Intel Corporation | Flip-chip opto-electronic circuit |
JP2004095923A (ja) * | 2002-09-02 | 2004-03-25 | Murata Mfg Co Ltd | 実装基板およびこの実装基板を用いた電子デバイス |
TWI360912B (en) * | 2008-04-25 | 2012-03-21 | Univ Nat Chiao Tung | Vertical transition structure |
EP2333828B1 (en) * | 2008-09-05 | 2019-11-20 | Mitsubishi Electric Corporation | High-frequency circuit package, and sensor module |
KR101077011B1 (ko) * | 2009-06-09 | 2011-10-26 | 서울대학교산학협력단 | 미세가공 공동 공진기와 그 제조 방법 및 이를 이용한 대역통과 필터와 발진기 |
US8227904B2 (en) * | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US8383949B2 (en) * | 2009-12-29 | 2013-02-26 | Intel Corporation | Method to form lateral pad on edge of wafer |
-
2010
- 2010-06-25 US US13/383,895 patent/US8531023B2/en active Active
- 2010-06-25 WO PCT/JP2010/004239 patent/WO2011007507A1/ja active Application Filing
- 2010-06-25 JP JP2011522699A patent/JPWO2011007507A1/ja not_active Ceased
-
2013
- 2013-08-05 US US13/958,989 patent/US8802496B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07254661A (ja) * | 1994-03-15 | 1995-10-03 | Toshiba Corp | マイクロ波集積回路 |
JP2000031708A (ja) * | 1998-07-16 | 2000-01-28 | Toshiba Corp | モノリシックマイクロ波集積回路 |
JP2000357763A (ja) * | 1999-04-13 | 2000-12-26 | Nec Corp | 高周波回路基板 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019046878A (ja) * | 2017-08-30 | 2019-03-22 | 富士通株式会社 | 電子装置、及び、電子装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8802496B2 (en) | 2014-08-12 |
JPWO2011007507A1 (ja) | 2012-12-20 |
US8531023B2 (en) | 2013-09-10 |
US20120112344A1 (en) | 2012-05-10 |
US20130316495A1 (en) | 2013-11-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9679864B2 (en) | Printed interconnects for semiconductor packages | |
US8729680B2 (en) | Semiconductor device | |
US8592959B2 (en) | Semiconductor device mounted on a wiring board having a cap | |
TWI393239B (zh) | 具有內屏蔽體之封裝結構及其製造方法 | |
JP2010103574A (ja) | 半導体チップ及び半導体チップパッケージ | |
WO2011007507A1 (ja) | 半導体パッケージ用基板および半導体パッケージ用基板の製造方法 | |
JP5729186B2 (ja) | 半導体装置及びその製造方法 | |
JP6054188B2 (ja) | 半導体パッケージおよびその製造方法 | |
JP2009010327A (ja) | 半導体装置およびその製造方法 | |
JP4190111B2 (ja) | 高周波モジュール | |
JP2006344672A (ja) | 半導体チップとそれを用いた半導体装置 | |
JP7167933B2 (ja) | 電子部品内蔵構造体 | |
JP5153364B2 (ja) | 積層型半導体パッケージおよび電子装置 | |
US10763200B2 (en) | Mounting structure and module | |
KR101011888B1 (ko) | 반도체 패키지 | |
TWI811764B (zh) | 半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法 | |
JP2013004754A (ja) | 半導体パッケージ及びその製造方法 | |
JP3761538B2 (ja) | 高周波半導体装置 | |
JP3502769B2 (ja) | 半導体素子の実装構造 | |
JP2006278780A (ja) | 半導体装置 | |
JP2016143782A (ja) | 電子装置 | |
JP3879475B2 (ja) | 配線基板及びそれを用いた半導体装置並びに配線基板の製造方法 | |
JP6557481B2 (ja) | 電子装置 | |
JP2014160697A (ja) | 素子収納用パッケージ、並びに実装構造体 | |
JPH1131696A (ja) | 半導体素子、半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10799571 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011522699 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13383895 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 10799571 Country of ref document: EP Kind code of ref document: A1 |