TWI811764B - 半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法 - Google Patents

半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法 Download PDF

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TWI811764B
TWI811764B TW110130084A TW110130084A TWI811764B TW I811764 B TWI811764 B TW I811764B TW 110130084 A TW110130084 A TW 110130084A TW 110130084 A TW110130084 A TW 110130084A TW I811764 B TWI811764 B TW I811764B
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layer
packaging
component
support component
semiconductor
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TW110130084A
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TW202310723A (zh
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周鄂東
邱柏翰
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恆勁科技股份有限公司
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Priority to TW110130084A priority Critical patent/TWI811764B/zh
Priority to US17/858,286 priority patent/US20230048468A1/en
Priority to CN202210793376.7A priority patent/CN115706092A/zh
Publication of TW202310723A publication Critical patent/TW202310723A/zh
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  • Liquid Crystal (AREA)

Abstract

本發明揭露一種半導體封裝結構，其包括一封裝載板、一電子元件、一封裝層、一支撐組件以及一屏蔽層。電子元件係設置於封裝載板之一第一表面上。封裝層設置於封裝載板之第一表面且包覆電子元件。支撐組件嵌埋於封裝層內並且至少框圍住電子元件。支撐組件之一側端面係電性連接於封裝載板之一增層線路並且電性接地。屏蔽層之一圖案化金屬層電性連接支撐組件，且圖案化金屬層之遮蔽範圍至少涵蓋電子元件。支撐組件與屏蔽層共同框圍形成一包覆電子元件之屏蔽空間。另外，本發明還揭露一種半導體電磁干擾屏蔽元件以及半導體封裝結構的製造方法。

Description

半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法
本發明係關於一種封裝結構及其製造方法，特別關於一種具有電磁干擾屏蔽功能的半導體封裝結構及其製造方法。
電磁干擾(Electromagnetic Interference,EMI)可能以電流的形式沿載流導體(例如電源線和電纜)傳播，或以電磁波的形式通過空間傳播。因此，根據電磁干擾的耦合通路的不同，電磁干擾可以分為傳導電磁干擾和輻射電磁干擾兩種。通過載流導體傳播的電磁干擾稱為傳導型電磁干擾，通過空間傳播的電磁干擾稱為輻射型電磁干擾。
一般而言，對於輻射型電磁干擾通常係採取空間上屏蔽或隔離的方式做為改善對策，其大致分為利用金屬蓋或打線(wire bonding)包覆的方式來屏蔽電磁干擾，其將分述如下。
請參照第1圖所示，習知的一種封裝結構10包括一電路板11、一晶片12、一封裝層13。晶片12係電性連接於電路板11之一表面上，且封裝層13係包覆晶片12。電路板11可以係為多層電路板，其具有複數層疊的電路層111，並包覆於一介電層112中。其中，層疊的電路層111係透過導電通孔或導電盲孔形成電性連接，並且，電路層111的其中之一係設計為一接地層(grounding layer)111a。
為了避免晶片12受到輻射型電磁干擾的影響，第一種電磁干擾屏蔽手段係採用一金屬外蓋14罩設於封裝結構10的外側，以隔絕外來的電磁干擾。其中金屬外蓋14具有一頂蓋141及一 側壁142，頂蓋141係覆蓋於晶片12之上，而側壁142係電性連接於封裝結構10側緣之接地層111a，以令金屬外蓋14接地，並據此達到電磁干擾屏蔽之目的。
請參照第2圖所示，習知的一種電子裝置20係包括一電路板21、複數個晶片22以及複數個被動元件23。晶片22以及被動元件23係焊接於電路板21之表面上。
為了避免晶片22受到輻射型電磁干擾的影響，第二種電磁干擾屏蔽手段係採用打線包覆晶片22，以隔絕外來的電磁干擾。打線包覆係利用銅線(Cu wire)24包覆晶片22，其中銅線24的兩端係電性連接於電路板21之接地銲墊(ground pad)，而接地銲墊係與電路板21之接地層導通之外露電性連接墊，以形成局部或全區的電磁干擾屏蔽。
上述第一種電磁干擾屏蔽手段必須先形成單顆的封裝結構10後，再對其逐一組裝金屬外蓋14，因此製程手續相當繁瑣；而上述第二種電磁干擾屏蔽手段必須針對需要電磁干擾屏蔽的晶片進行局部打線或是全區打線，可想而知其所需的製程步驟將更加繁複。
因應於習知技術存在之上述技術問題，提供一種封裝結構及其電磁干擾屏蔽元件及具有電磁干擾屏蔽功能的封裝結構製造方法，使封裝結構具有電磁干擾屏蔽效果，同時能夠簡化製程手續，實屬當前重要課題之一。
有鑑於上述，本發明之一目的是提供一種半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法，其具有製程手續簡便之優點。
為達上述目的，本發明提供一種半導體封裝結構，其包括一封裝載板、至少一電子元件、一封裝層、一支撐組件以及一屏蔽層。封裝載板具有相對之第一表面與第二表面，且包括有一增層線路及一包覆該增層線路之一第一介電層。電子元件係設置於封裝載板之第一表面，並與增層線路電性連接。封裝層係 設置於封裝載板之第一表面，且包覆電子元件。支撐組件係嵌埋於封裝層內並且至少框圍住電子元件。其中支撐組件之一側端面係暴露於封裝層之一表面，而支撐組件之另一側端面係電性連接於封裝載板之增層線路並且電性接地。屏蔽層係設置於封裝層與支撐組件上，且包括有一圖案化金屬層及一包覆圖案化金屬層之第二介電層。圖案化金屬層電性連接支撐組件，且圖案化金屬層之遮蔽範圍至少涵蓋電子元件及支撐組件。支撐組件與該屏蔽層共同框圍形成一包覆電子元件之屏蔽空間。
於一實施例中，其中圖案化金屬層設置有複數貫穿圖案化金屬層之穿孔。
於一實施例中，其中圖案化金屬層之上表面係暴露於第二介電層之上表面。
於一實施例中，支撐組件包含有呈柵欄式排列之複數導電柱、或呈圍牆狀之連續側壁、或複數導電柱與連續側壁之組合。
於一實施例中，半導體封裝結構更包含複數導電黏合膠，藉以將支撐組件結合於封裝載板之第一表面，且與該增層線路電性連接為電性接地，其中該等導電黏合膠之間具有空隙。
另外，為達上述目的，本發明提供一種半導體電磁干擾屏蔽元件，其可結合於一封裝載板上。半導體電磁干擾屏蔽元件包括一第二介電層、一圖案化金屬層以及一支撐組件。圖案化金屬層係嵌設於該第二介電層內。支撐組件係由導電金屬所構成，且支撐組件之其中一側端面係與圖案化金屬層結合並且電性連接，而支撐組件之另一側端面係可結合並且電性連接於封裝載板。圖案化金屬層與支撐組件共同框圍形成一屏蔽空間。
又，為達上述目的，本發明提供一種半導體封裝結構之製造方法，其包括下列步驟：步驟一係提供一封裝載板，其具有相對之第一表面與第二表面，且包含一增層線路，以及一包覆增層線路之一第一介電層。步驟二係於封裝載板之一第一表面上設置至少一電子元件，且電子元件與增層線路電性連接。步驟 三係提供一如上所述之半導體電磁干擾屏蔽元件，且使其結合於封裝載板之第一表面，並且至少罩蓋住電子元件，其中半導體電磁干擾屏蔽元件與封裝載板之增層線路電性連接且電性接地。步驟四係形成一封裝層於封裝載板之第一表面上與半導體電磁干擾屏蔽元件間之腔體，並包覆電子元件與半導體電磁干擾屏蔽元件之支撐組件。
於一實施例中，其中將半導體電磁干擾屏蔽元件結合於封裝載板之第一表面之步驟之前，更包含於封裝載板之第一表面形成複數非連續之導電黏合膠，且該些導電黏合膠與該增層線路電性連接並電性接地，供半導體電磁干擾屏蔽元件以支撐組件之一側端面來黏接結合於封裝載板，且該些導電黏合膠之間具有空隙，以作為填充封裝材料之填充通道。
再者，為達上述目的，本發明提供另一種半導體封裝結構之製造方法，其包括下列步驟：步驟一係提供一封裝載板，其具有相對之一第一表面與一第二表面，且包含有一增層線路，以及一包覆增層線路之第一介電層。步驟二係於封裝載板之第一表面上設置至少一電子元件，且電性連接增層線路。步驟三係形成一支撐組件及一封裝層於封裝載板之第一表面，其中支撐組件電性連接增層線路以接地並框圍住電子元件，而封裝層包覆電子元件及支撐組件。步驟四係於封裝層上以曝光顯影方法電鍍形成一圖案化金屬層，且圖案化金屬層電性連接支撐組件，其中圖案化金屬層之遮蔽範圍至少涵蓋電子元件及支撐組件。步驟五係形成一第二介電層於封裝層及圖案化金屬層上，以包覆圖案化金屬層。
於一實施例中，形成支撐組件及封裝層之方法還至少包括下列兩個步驟。首先，係以一感光型介電材形成封裝層於封裝載板之第一表面上，以包覆電子元件。接著，於封裝層以圖案化曝光顯影形成複數開孔，且於開孔內電鍍形成支撐組件以框圍住電子元件，其中支撐組件與增層線路電性連接並且接地。
於另一實施例中，於一實施例中，形成支撐組件及 封裝層之方法還至少包括下列兩個步驟。首先，於封裝載板之第一表面上以圖案化曝光顯影電鍍形成支撐組件，以框圍住電子元件，其中支撐組件與增層線路電性連接並且接地。接著，形成一封裝層於封裝載板之第一表面上，以包覆電子元件及支撐組件，並且露出支撐組件之一端面。
於一實施例中，其中形成圖案化金屬層之步驟之前，更包含於封裝層上對應於支撐組件露出之一側端面上，以曝光顯影方法電鍍形成與支撐組件相連接之一導電金屬；以及形成一第一子介電層於封裝層上，以包覆導電金屬，並且露出導電金屬之一側端面。
於一實施例中，其中形成圖案化金屬層之步驟之前，更包含形成一第一子介電層於封裝層上，並且於第一子介電層形成複數開孔以對應露出支撐組件之一側端面；以及於複數開孔內電鍍形成與支撐組件相連接之導電金屬，且導電金屬之一側端面露出於第一子介電層之一表面。
於一實施例中，圖案化金屬層之上表面係露出於第二介電層之上表面。
承上所述，本發明揭露之一種封裝結構及其半導體電磁干擾屏蔽元件及封裝結構的製造方法係利用半導體製程來製作電磁干擾屏蔽元件，其可以與封裝結構的製程整合，於封裝時同步形成電磁干擾屏蔽結構，而可以簡化具有電磁干擾屏蔽功能的封裝結構的製程。
11,21:電路板
111:電路層
111a:接地層
112:介電層
12,22:晶片
13:封裝層
14:金屬外蓋
141:頂蓋
142:側壁
20:電子裝置
23:被動元件
24:銅線
10,30:半導體封裝結構
31:封裝載板
311:第一表面
312:第二表面
313:增層線路
3131,3133,3135:圖案化導電層
3132,3134:導電柱層
314:第一介電層
321,322,323:電子元件
33:封裝層
331:第三表面
332:第四表面
34:支撐組件
341:第一側端面
342:第二側端面
343a:導電柱
343b:連續側壁
35:屏蔽層
351:圖案化金屬層
3511:第一子導電金屬
3512:第二子導電金屬
352:第二介電層
3521:第五表面
3522:第六表面
3523:第一子介電層
3524:第二子介電層
36:銲球
AM1:半導體電磁干擾屏蔽元件
O1:第一開孔
O2:第一子開孔
O3:第二子開孔
Z01:圍設區域
Z11:第一圍設區域
Z12:第二圍設區域
〔第1圖〕係顯示一種習知電磁干擾屏蔽方法的結構示意圖。
〔第2圖〕係顯示另一種習知電磁干擾屏蔽方法的結構示意圖。
〔第3圖〕係顯示依據本發明較佳實施例之一種封裝結構的剖面示意圖。
〔第4A圖〕係顯示依據本發明較佳實施例之封裝結構的半導 體電磁干擾屏蔽元件的俯視示意圖。
〔第4B圖〕係顯示依據本發明較佳實施例之封裝結構的半導體電磁干擾屏蔽元件的側視示意圖。
〔第5A至5D圖〕係顯示依據本發明較佳實施例之封裝結構，其中不同實施態樣的半導體電磁干擾屏蔽元件的支撐組件的仰視示意圖。
〔第6A至6C圖〕係顯示本發明較佳實施例之第一種封裝結構的製造方法流程示意圖。
〔第7A至7F圖〕係顯示本發明較佳實施例之第二種封裝結構的製造方法流程示意圖。
為了使所屬技術領域中具有通常知識者能瞭解本發明的內容，並可據以實現本發明的內容，茲配合適當實施例及圖式說明如下。
第3圖係依據本發明較佳實施例之一種封裝結構的剖面示意圖。半導體封裝結構30包括一封裝載板31、三個電子元件321~323、一封裝層33、一支撐組件34、一屏蔽層35以及複數個銲球36。
封裝載板31具有相對之一第一表面311與一第二表面312，並具有一增層線路313與一第一介電層314。其中，增層線路313係嵌埋於第一介電層314中，並且包括堆疊設置之圖案化導電層3131、3133、3135以及導電柱層3132、3134，其材質例如為銅，藉以形成導電路徑。在本實施例中，部分的圖案化導電層3131、3135係可作為電性連接墊(或稱銲墊)。例如，部分的圖案化導電層3131係與銲球36電性連接。
電子元件321~323係可透過銲球(conductive bump)或導電黏合膠等具有導電黏合的元件而分別設置於封裝載板31之第一表面311上，並且電性連接於增層線路313。在本實施例中，電子元件321例如係為打線封裝式的晶片、電子元件322例如係為覆晶封裝式的晶片、而電子元件323例如係為電容器。換言之，電 子元件可以是主動元件(active component)或被動元件(passive component)，其並未限定。
封裝層33具有相對之一第三表面331與一第四表面332。封裝層33係包覆封裝載板31之第一表面311與電子元件321~323。在本實施例中，封裝層33之第四表面332與封裝載板31之第一表面311係為共平面。
支撐組件34係由導電金屬所構成，並且具有相對之一第一側端面341以及一第二側端面342。支撐組件34係嵌埋於封裝層33內並且框圍該些電子元件321~323。支撐組件34之第一側端面341係暴露於封裝層33之第三表面331，而第二側端面342係電性連接於封裝載板之增層線路313並且電性接地。
屏蔽層35設置於封裝層33之第三表面331以及支撐組件34上，並且屏蔽層35包括一圖案化金屬層351以及一第二介電層352。第二介電層352係包覆圖案化金屬層351，並具有相對之一第五表面3521及一第六表面3522，其中，第六表面3522與封裝層33之第三表面331為共平面。部分的圖案化金屬層351係分別暴露於第二介電層352之第五表面3521及第六表面3522，其中，暴露於第六表面3522之部分的圖案化金屬層351係電性連接於支撐組件34之第一側端面341。
另外，值得一提的是，上述的支撐組件34與屏蔽層35係可組成一半導體電磁干擾屏蔽元件AM1，並且支撐組件34與屏蔽層35係共同框圍形成一包覆電子元件321~323之屏蔽空間。請同時參照第3圖及第4A圖所示，其中第4A圖係半導體電磁干擾屏蔽元件AM1的俯視示意圖。由第3圖及第4A圖可知，圖案化金屬層351之遮蔽範圍係至少涵蓋電子元件321~323以及支撐組件34。再由第4A圖可知，部分之圖案化金屬層351之一側表面係暴露於第二介電層352之第五表面3521，由俯視圖觀察，半導體電磁干擾屏蔽元件AM1可利用類似網狀的結構來達到電磁干擾屏蔽效果。在其他實施例中，半導體電磁干擾屏蔽元件AM1亦可利用完整的金屬面或利用其他圖案化金屬層來達到電磁干擾屏蔽效果， 於此並未加以限制。
請再同時參照第3圖及第4B圖所示，其中第4B圖係半導體電磁干擾屏蔽元件AM1的側視示意圖。由第4B圖可知，在本實施例中，支撐組件34具有複數個導電柱343a，其係呈柵欄式排列，並且各導電柱343a可以藉由導電黏合膠或銲球而連接於封裝載板31上(圖中未示出)。
另外，半導體電磁干擾屏蔽元件AM1的支撐組件34可以具有多種的變化態樣以擴展其應用範圍，以下係以第5A圖至5D圖之仰視示意圖簡單說明半導體電磁干擾屏蔽元件AM1的支撐組件34的變化態樣。
如第5A圖所示，支撐組件34具有複數個導電柱343a，其係間隔排列，並且構成一圍設區域Z01。前述之電子元件321~323係位於圍設區域Z01中，而被導電柱343a框圍。如第5B圖所示，藉由支撐組件34之導電柱343a還可分別構成一第一圍設區域Z11及一第二圍設區域Z12，其可形成範圍不一之圍設區域，以針對局部的電子元件做電磁干擾屏蔽，例如前述之電子元件321、322係位於一第一圍設區域Z11之範圍內，而電子元件323係位於第二圍設區域Z12之範圍內。上述之圍設區域之敘述僅為舉例性，其圍設區域之形狀大小係可依據實際需求所設計。
另外，如第5C圖所示，支撐組件34除上述具有導電柱的態樣之外，還可呈圍牆狀之連續側壁343b的態樣，或是如第5D圖所示，係由連續側壁343b以及導電柱343a組合之態樣。支撐組件34的實現亦可由第5A~5D圖的態樣依據實際需求而搭配使用，於此並未限定。
針對上述具有電磁干擾屏蔽功能的封裝結構，以下將列舉二個實施例，以說明具有電磁干擾屏蔽功能的封裝結構的製造方法。
請參照第6A至6C圖所示，本發明之第一種半導體封裝結構之製造方法，其係包括步驟S01~S05。
如第6A圖所示，步驟S01係提供一封裝載板31，其具 有相對之一第一表面311與一第二表面312，並且包括一增層線路313，以及一包覆增層線路313之第一介電層314。
步驟S02係於封裝載板31之第一表面311上設置三個電子元件321~323。其中，電子元件321~323可藉由打線製程、覆晶製程、迴銲製程或導電黏合膠黏合等製程而設置於封裝載板31上，並與增層線路313電性連接。
如第6B圖所示，步驟S03係將一半導體電磁干擾屏蔽元件AM1結合於封裝載板31之第一表面311，並罩蓋電子元件321~323。其中，半導體電磁干擾屏蔽元件AM1與封裝載板31之增層線路313電性連接且電性接地。在本實施例中，半導體電磁干擾屏蔽元件AM1具有一支撐組件34以及一屏蔽層35。支撐組件34可包括複數個呈柵欄式排列的導電柱343a，其係可透過導電黏合膠而設置或固定於封裝載板31之第一表面311，並電性連接於增層線路313。屏蔽層35包括一圖案化金屬層351以及一第二介電層352，並且部分的圖案化金屬層351係電性連接於導電柱343a。
如第6C圖所示，步驟S04係形成一封裝層33於封裝載板31之第一表面311與半導體電磁干擾屏蔽元件AM1間之腔體，並包覆電子元件321~323與支撐組件34。在本實施例中，由於半導體電磁干擾屏蔽元件AM1之支撐組件34包括有複數個呈柵欄式排列的導電柱343a，因此封裝層33能在流體的狀態下覆蓋封裝載板31，並且填充於半導體電磁干擾屏蔽元件AM1、封裝載板31以及電子元件321~323之間，之後再予以固化。
步驟S05係形成銲球36於封裝載板31之第二表面312。另外，在本實施例中，上述步驟所形成之封裝結構係可由大版面製程來完成，而在進行切單製程後，即可形成單一個具有電磁干擾屏蔽功能的封裝結構。
於此要特別說明的是，當半導體電磁干擾屏蔽元件AM1之支撐組件34係為連續側壁型式時，可透過間隔設置導電黏合膠於側壁之底端部與封裝載板31之第一表面之間，則封裝層33亦能在流體的狀態下通過間隔的導電黏合膠而填充至半導體電磁 干擾屏蔽元件AM1、封裝載板31以及電子元件321~323之間。
請再參照第7A至7F圖所示，本發明之第二種半導體封裝結構之製造方法，其係包括步驟S11~S22。
與前述實施例之第6A圖相同，步驟S11係提供封裝載板31。步驟S12係於封裝載板31之一表面上設置三個電子元件321~323。
如第7A圖所示，步驟S13係以一感光型介電材形成封裝層33於封裝載板31之第一表面311上，並且包覆電子元件321、322、323。步驟S14係以圖案化曝光顯影方式於封裝層33形成複數個第一開孔O1，以暴露出部分之封裝載板31之第一表面311及/或增層線路313。在本實施例中，該些第一開孔O1係呈柵欄式排列以框圍電子元件321、322、323，並且暴露部分的增層線路313。
如第7B圖所示，步驟S15係分別於各第一開孔O1中電鍍形成一導電柱343a，以使該些導電柱343a構成前述之支撐組件34。
於此，值得一提的是，在其他實施例中上述的步驟S13、步驟S14及步驟S15係可以替換如下。首先，係於封裝載板31之第一表面311上以圖案化曝光顯影電鍍形成導電柱343a(支撐組件34)，以框圍住電子元件321、322、323。接著，形成一封裝層33於封裝載板31之第一表面311上，以包覆電子元件321、322、323及支撐組件34，並且露出支撐組件34之一端面。其中，支撐組件34與增層線路313電性連接並且接地。須注意者，在這個例示中，封裝層33之材質則無選用感光型介電材之必要性，而有更多的封裝材料可供選擇之。
回到本實施例，如第7C圖所示，步驟S16係形成一第一子介電層3523於封裝層33及導電柱343a上，以覆蓋封裝層33。步驟S17係於第一子介電層3523形成複數個第一子開孔O2以暴露出各導電柱343a之上端面。
如第7D圖所示，步驟S18係形成一第一子導電金屬3511於該等第一子開孔O2中，並且電性連接該些導電柱343a。
如第7E圖所示，步驟S19係形成一第二子介電層3524於第一子介電層3523及第一子導電金屬3511上，以包覆第一子介電層3523。其中，第一子介電層3523與第二子介電層3524係共同組成第二介電層352。步驟S20係形成複數個第二子開孔O3以暴露出部分之第一子導電金屬3511及部分之第一子介電層3523。
如第7F圖所示，步驟S21係形成一第二子導電金屬3512於該等第二子開孔O3，以使第一子導電金屬3511及第二子導電金屬3512構成圖案化金屬層351。最後，步驟S22係形成銲球36於封裝載板31之第二表面312。
與前述實施例之第一種製造方法相似的是，上述步驟S11~S22所形成之半導體封裝結構係可由大版面製程來完成，而在進行切單製程後，即可形成單一個具有電磁干擾屏蔽功能的半導體封裝結構。
綜上所述，本發明揭露之一種半導體電磁干擾屏蔽元件、半導體封裝結構及其製造方法係利用半導體製程來製作電磁干擾屏蔽元件，其可以與封裝結構的製程整合同步，而可以簡化具有電磁干擾屏蔽功能的封裝結構的製程。相較於先前技術，本發明至少具有下列優點：
01.本發明可以在封裝載板尚未進行切單製程之前即可與半導體電磁干擾屏蔽元件組合，並在組合之後再進行切單製程。
02.本發明對於僅需局部電磁干擾屏蔽的封裝結構具有可作業性高且生產週期短的優點。
03.本發明的電磁干擾屏蔽元件係以半導體製程完成，而能夠與同為半導體製程的封裝結構利用相似的製程技術同步完成，而可簡化製程。
本發明符合發明專利之要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士，爰依本案發明精神所作之等效修飾或變化，皆應包含於以下之申請專利範圍內。
30:半導體封裝結構
31:封裝載板
311:第一表面
312:第二表面
313:增層線路
3131,3133,3135:圖案化導電層
3132,3134:導電柱層
314:第一介電層
321,322,323:電子元件
33:封裝層
331:第三表面
332:第四表面
34:支撐組件
341:第一側端面
342:第二側端面
35:屏蔽層
351:圖案化金屬層
352:第二介電層
3521:第五表面
3522:第六表面
36:銲球
AM1:半導體電磁干擾屏蔽元件

Claims (19)

  1. 一種半導體封裝結構，包含：一封裝載板，係具有相對之一第一表面與一第二表面，且包含有一增層線路及一包覆該增層線路之第一介電層；至少一電子元件，係設置於該封裝載板之該第一表面，並與該封裝載板之該增層線路電性連接；一封裝層，係設於該封裝載板之該第一表面上，且包覆該電子元件；一支撐組件，係嵌埋於該封裝層內並且至少框圍住該電子元件，其中該支撐組件之一側端面係暴露於該封裝層之一表面，而該支撐組件之另一側端面係電性連接於該封裝載板之該增層線路並且電性接地，其中該支撐組件具有呈柵欄式排列之複數導電柱；以及一屏蔽層，係設置於該封裝層與該支撐組件上，且包含有一圖案化金屬層及一包覆該圖案化金屬層之第二介電層，其中該圖案化金屬層電性連接該支撐組件，且該圖案化金屬層之遮蔽範圍至少涵蓋該電子元件及該支撐組件；其中，該支撐組件與該屏蔽層共同框圍形成一包覆該電子元件之屏蔽空間。
  2. 如請求項1所述之半導體封裝結構，其中該圖案化金屬層係設有複數貫穿該圖案化金屬層之穿孔。
  3. 如請求項1所述之半導體封裝結構，其中該圖案化金屬層之一側表面係暴露出於該第二介電層之一表面。
  4. 如請求項1所述之半導體封裝結構，其中該支撐組件包含有該些導電柱與連續側壁之組合。
  5. 如請求項4所述之半導體封裝結構，更包含複數導電黏合膠，藉以將該支撐組件結合於該封裝載板之該第一表面，且與該增層線路電性連接為電性接地，其中該等導電黏合膠之間具有空隙。
  6. 一種半導體電磁干擾屏蔽元件，係可結合於一封裝載 板上，其主要係包含：一第二介電層；一圖案化金屬層，係嵌設於該第二介電層內；以及一支撐組件，係由導電金屬所構成，且該支撐組件之其中一側端面係與該圖案化金屬層結合並且電性連接，而該支撐組件之另一側端面係可結合並且電性連接於該封裝載板，其中該支撐組件具有呈柵欄式排列之複數導電柱；其中，該圖案化金屬層與該支撐組件共同框圍形成一屏蔽空間。
  7. 如請求項6所述之半導體電磁干擾屏蔽元件，其中該圖案化金屬層係設有複數貫穿該圖案化金屬層之穿孔。
  8. 如請求項6所述之半導體電磁干擾屏蔽元件，其中該圖案化金屬層之一側表面係暴露出於該第二介電層之一表面。
  9. 如請求項6所述之半導體電磁干擾屏蔽元件，其中該支撐組件包含該些導電柱與連續側壁之組合。
  10. 一種半導體封裝結構之製造方法，包含：提供一封裝載板，其係具有相對之一第一表面與一第二表面，且包含一增層線路，以及一包覆該增層線路之第一介電層；於該封裝載板之該第一表面上設置至少一電子元件，且該電子元件與該增層線路電性連接；提供一如請求項6~9所述之半導體電磁干擾屏蔽元件，且結合於該封裝載板之該第一表面，並且至少罩蓋住該電子元件，其中該半導體電磁干擾屏蔽元件與該封裝載板之該增層線路電性連接且電性接地；以及形成一封裝層於該封裝載板之該第一表面與該半導體電磁干擾屏蔽元件間之腔體，並包覆該電子元件與該半導體電磁干擾屏蔽元件之該支撐組件。
  11. 如請求項10所述之半導體封裝結構之製造方法，其中將該半導體電磁干擾屏蔽元件結合於該封裝載板之該第一表面之步驟前，更包含：於該封裝載板之該第一表面形成複數非連續之導電黏合膠，且該 些導電黏合膠與該增層線路電性連接並電性接地，供該半導體電磁干擾屏蔽元件以該支撐組件之一側端面來黏接結合於該封裝載板，且該些導電黏合膠之間具有空隙，以作為填充封裝材料之填充通道。
  12. 一種半導體封裝結構之製造方法，包含：提供一封裝載板，其係具有相對之一第一表面與一第二表面，且包含有一增層線路，以及一包覆該增層線路之第一介電層；於該封裝載板之該第一表面上設置至少一電子元件，且電性連接該增層線路；形成一支撐組件及一封裝層於該封裝載板之該第一表面，其中該支撐組件電性連接該增層線路以接地並框圍住該電子元件，而該封裝層包覆該電子元件及該支撐組件，其中該支撐組件具有呈柵欄式排列之複數導電柱；於該封裝層上以曝光顯影方法電鍍形成一圖案化金屬層，且該圖案化金屬層電性連接該支撐組件，其中該圖案化金屬層之遮蔽範圍至少涵蓋該電子元件及該支撐組件；以及形成一第二介電層於該封裝層及該圖案化金屬層上，以包覆該圖案化金屬層。
  13. 如請求項12所述之半導體封裝結構之製造方法，其中形成該支撐組件及該封裝層之方法包括：以一感光型介電材形成該封裝層於該封裝載板之該第一表面上，以包覆該電子元件；以及於該封裝層以圖案化曝光顯影形成複數開孔，且分別於該些開孔內電鍍形成該支撐組件以框圍住該電子元件，其中該支撐組件與該增層線路電性連接並且接地。
  14. 如請求項12所述之半導體封裝結構之製造方法，其中形成該支撐組件及該封裝層之方法包括：於該封裝載板之該第一表面上以圖案化曝光顯影電鍍形成該支撐組件，以框圍住該電子元件，其中該支撐組件與該增層線路電性連接並且接地；以及 形成一封裝層於該封裝載板之該第一表面上，以包覆該電子元件及該支撐組件，並且露出該支撐組件之一端面。
  15. 如請求項12所述之半導體封裝結構之製造方法，其中該支撐組件包含有該些導電柱與連續側壁之組合。
  16. 如請求項12所述之半導體封裝結構之製造方法，其中形成該圖案化金屬層之步驟前，更包含：於該封裝層上對應於該支撐組件露出之一側端面上，以曝光顯影方法電鍍形成與該支撐組件相連接之一導電金屬；以及形成一第一子介電層於該封裝層上，以包覆該導電金屬，並且露出該導電金屬之一側端面。
  17. 如請求項12所述之半導體封裝結構之製造方法，其中形成該圖案化金屬層之步驟前，更包含：形成一第一子介電層於該封裝層上，並且於該第一子介電層形成複數開孔以對應露出該支撐組件之一側端面；以及於該複數開孔內電鍍形成與該支撐組件相連接之一導電金屬，且該導電金屬之一側端面露出於該第一子介電層之一表面。
  18. 如請求項12所述之半導體封裝結構之製造方法，其中該圖案化金屬層具有複數貫穿該圖案化金屬層之穿孔。
  19. 如請求項12所述之半導體封裝結構之製造方法，其中更包含：於形成該第二介電層後，再執行整平作業，以令該圖案化金屬層之上表面露出於該第二介電層之上表面。
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TW201407745A (zh) * 2012-08-01 2014-02-16 Advanced Semiconductor Eng 半導體封裝件及其製造方法
TW201715691A (zh) * 2015-10-22 2017-05-01 力成科技股份有限公司 半導體封裝體及其製作方法
CN109256371A (zh) * 2017-07-13 2019-01-22 联发科技股份有限公司 半导体封装结构及其形成方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201407745A (zh) * 2012-08-01 2014-02-16 Advanced Semiconductor Eng 半導體封裝件及其製造方法
TW201715691A (zh) * 2015-10-22 2017-05-01 力成科技股份有限公司 半導體封裝體及其製作方法
CN109256371A (zh) * 2017-07-13 2019-01-22 联发科技股份有限公司 半导体封装结构及其形成方法

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