TWI508245B - 嵌埋晶片之封裝件及其製法 - Google Patents

嵌埋晶片之封裝件及其製法 Download PDF

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TWI508245B
TWI508245B TW099133962A TW99133962A TWI508245B TW I508245 B TWI508245 B TW I508245B TW 099133962 A TW099133962 A TW 099133962A TW 99133962 A TW99133962 A TW 99133962A TW I508245 B TWI508245 B TW I508245B
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Taiwan
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wafer
layer
package
dielectric layer
conductive
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TW099133962A
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TW201216426A (en
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張江城
廖信一
邱世冠
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矽品精密工業股份有限公司
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Priority to TW099133962A priority Critical patent/TWI508245B/zh
Priority to US12/965,215 priority patent/US20120086117A1/en
Publication of TW201216426A publication Critical patent/TW201216426A/zh
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Publication of TWI508245B publication Critical patent/TWI508245B/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

嵌埋晶片之封裝件及其製法
本發明係有關於一種封裝件及其製法，尤指一種嵌埋晶片之封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為追求半導體封裝件之輕薄短小，因而發展出一種晶片尺寸封裝件(chip scale package,CSP)，其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。
美國專利第5,892,179、6,103,552、6,287,893、6,350,668及6,433,427號案即揭露一種傳統之CSP結構，係直接於晶片上形成增層而無需使用如基板或導線架等晶片承載件，且利用重佈線(redistribution layer,RDL)技術重配晶片上的電極墊至所欲位置。
然而上述CSP結構之缺點在於重佈線技術之施用或佈設於晶片上的導電跡線往往受限於晶片之尺寸或其作用面之面積大小，尤其當晶片之積集度提昇且晶片尺寸日趨縮小的情況下，晶片甚至無法提供足夠表面以安置更多數量的銲球來與外界電性連接。
鑑此，美國專利第6,271,469號案揭露一種晶圓級晶片尺寸封裝件WLCSP(Wafer Level CSP)之製法，係於晶片上形成增層的封裝件，得提供較為充足的表面區域以承載較多的輸入/輸出端或銲球。
如第1A圖所示，準備一膠膜11，並將複數晶片12以作用面121黏貼於該膠膜11上，該膠膜11例如為熱感應膠膜；如第1B圖所示，進行封裝模壓製程，利用一如環氧樹脂之封裝膠體13包覆住晶片12之非作用面122及側面，再加熱移除該膠膜11，以外露出該晶片作用面121；如第1C圖所示，然後利用重佈線(RDL)技術，敷設一介電層14於晶片12之作用面121及封裝膠體13的表面上，並開設複數貫穿介電層14之開口以露出晶片上的電極墊120，接著於該介電層14上形成線路層15，並使線路層15電性連接至電極墊120，再於線路層15上敷設拒銲層16及線路層15預定位置植設銲球17，之後進行切割作業。
透過前述製程，因包覆該晶片12之封裝膠體13的表面得提供較該晶片12作用面121大之表面區域而能安置較多銲球17以有效達成與外界之電性連接。
然，上揭製程之缺點在於將該晶片12以其作用面121黏貼於該膠膜11上而固定之方式’常因該膠膜11於製程中受熱而發生伸縮問題，造成黏置於該膠膜11上之晶片12位置發生偏移，甚至於封裝模壓時因該膠膜11受熱軟化而造成該晶片12位移，如此導致後續在重佈線製程時，該線路層15無法連接到該晶片12電極墊120上，因而造成電性不良。
請參閱第2圖，於另一封裝模壓中，因膠膜11’遇熱軟化，該封裝膠體13易發生溢膠130至該晶片12之作用面121，甚或污染該電極墊120，造成後續重佈線製程之 線路層與晶片電極墊接觸不良，而導致廢品問題。
請參閱第3A圖，前述封裝模壓製程僅透過該膠膜11支撐複數晶片12，該膠膜11及封裝膠體13易發生嚴重翹曲(warpage)110問題，尤其是當該封裝膠體13之厚度很薄時，翹曲問題將更為嚴重，從而導致後續重佈線製程時，在該晶片12上塗佈該介電層14時會有厚度不均問題；如此即須額外再提供一硬質載具18(如第3B圖所示)，以將該封裝膠體13透過一黏膠19固定在該硬質載具18來進行整平，但當完成重佈線製程而移除該載具18時，易於該封裝膠體13上殘留黏膠190(如第3C圖所示)。其它相關習知技術的揭露如美國專利第6,498,387、6,586,822、7,019,406及7,238,602號。
再者，如第3D圖所示，若該封裝件欲進行堆疊時，需先貫穿該封裝膠體13，爾後進行封裝膠體13貫孔製程(TMV,Through Mold Via)，以形成複數貫穿之通孔，之後再以電鍍或化鍍製成以於該通孔中填充導電材料100，俾形成複數導電通孔10，再於該導電通孔10上形成銲球17’，以供接置如另一封裝件之電子裝置1。惟，貫穿該封裝膠體13之製程困難，且形成該導電通孔10時需填充該導電材料100，以致於製程時間增加，且成本提高。
因此，如何提供一種晶片尺寸封裝件及製法，能避免前述習知技術之缺失，進而確保線路層與電極墊間之電性連接品質，並提昇產品的可靠度，減少製程成本，實為一重要課題。
本發明提供一種嵌埋晶片之封裝件，係包括：介電層，具有相對之第一表面及第二表面；導電凸塊，係設於該介電層中並外露於該介電層之第二表面；晶片，係嵌設於該介電層中，該晶片具有相對之作用面及非作用面，該作用面上設有複數電極墊；線路層，係設於該介電層之第一表面上；導電盲孔，係設於該介電層中，以令該線路層透過該導電盲孔電性連接該電極墊及該導電凸塊；以及第一拒銲層，係設於該介電層之第一表面及該線路層上，且該第一拒銲層具有第一開孔，以令部分該線路層外露於該第一開孔中。
前述之封裝件中，形成該導電凸塊之材質係為銅。
前述之封裝件中，該晶片之非作用面外露於該介電層之第二表面。復包括第二拒銲層，係設於該介電層之第二表面、晶片之非作用面及該導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
前述之封裝件中，該晶片之非作用面上具有散熱片。復包括第二拒銲層，係設於該介電層之第二表面、散熱片及該導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
前述之封裝件復包括導電元件，係設於該第一開孔中之線路層上。
前述之封裝件復包括增層結構，係設於該介電層之第 一表面及該線路層上，且該第一拒銲層設於該增層結構之最外層上。
本發明復提供一種嵌埋晶片之封裝件之製法，係包括：提供一承載板，且於該承載板上具有相鄰之導電凸塊及置晶區；設置晶片於該承載板之置晶區上，該晶片具有相對之作用面及非作用面，且該作用面上設有複數電極墊，並以該非作用面接置於該承載板上；形成介電層於該承載板、導電凸塊及晶片上，以包覆該晶片，且該介電層具有外露之第一表面及結合至該承載板上之第二表面；形成線路層於該介電層之第一表面上，且於該介電層中形成導電盲孔，以令該線路層透過該導電盲孔電性連接該電極墊及該導電凸塊；形成第一拒銲層於該介電層之第一表面及該線路層上；移除該承載板，以露出該介電層之第二表面及該導電凸塊；以及於該第一拒銲層上形成複數第一開孔，以令該線路層之部分表面露出於該第一開孔中。
前述之製法中，形成該承載板及導電凸塊之材質係為銅。且係使用蝕刻法移除該承載板。
前述之製法復包括於該晶片之非作用面上塗佈黏著層，以令該晶片定位於該承載板上。當移除該承載板後，再移除該黏著層，以外露該晶片之非作用面。
前述之製法中，於移除全部該承載板後，該晶片之非作用面係外露於該介電層之第二表面。復包括形成第二拒銲層於該介電層之第二表面、該晶片之非作用面及該些導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導 電凸塊之部分表面外露於該第二開孔中。
前述之製法中，若僅移除該承載板之部分材料，該晶片之非作用面上之承載板部分係供作為散熱片。復包括形成第二拒銲層於該介電層之第二表面、該散熱片及該些導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
前述之製法復包括形成導電元件於該第一開孔中之線路層上。
由上可知，本發明嵌埋晶片之封裝件及其製法，主要先將晶片設於具有導電凸塊之承載板上，再將介電層包覆該晶片與導電凸塊，接著進行重佈線製程再移除該承載板，藉以避免習知將晶片直接黏置於膠膜上發生膠膜受熱軟化、封裝膠體溢膠及晶片偏移與污染問題，甚或造成重佈線製程之線路層與電極墊接觸不良，導致廢品之問題。
再者，藉由導電凸塊增加支撐力，故可避免習知製程中以膠膜為支撐件而發生翹曲問題，且可避免在介電層上殘留黏膠之問題。
又，藉由導電凸塊之設計，以於欲進行堆疊時，可直接外接其他電子裝置，不需如習知技術之貫穿封裝膠體形成導電通孔，故本發明有效簡化製程，且因無需填充導電材料，而有效減少製程時間，並降低成本。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解 本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第4A至4I圖，係為本發明揭露之一種嵌埋晶片之封裝件之製法。
如第4A圖所示，提供一承載板20，且於該承載板20上具有相鄰之複數導電凸塊200及一置晶區A，且形成該承載板20及導電凸塊200係可為銅之材質。於本實施例中，該導電凸塊200係一體成形於該承載板20上，但亦可為額外增設之凸部，並無特別限制。
如第4B圖所示，設置一晶片22於該承載板20之置晶區A上，該晶片22具有相對之作用面22a及非作用面22b，且該作用面22a上設有複數電極墊220，並於該非作用面22b上藉由黏著層21以令該晶片22定位於該承載板20上。
如第4C圖所示，形成一介電層23於該承載板20、該些導電凸塊200及該晶片22上，以包覆該晶片22，且該介電層23具有外露之第一表面23a及結合至該承載板20上之第二表面23b。
如第4D圖所示，於該介電層23之第一表面23a上形成外露出該些電極墊220及該些導電凸塊200之複數盲孔230。
如第4E圖所示，進行圖案化電鍍製程，形成導電盲孔240於該些盲孔230中，且形成線路層24於該導電盲孔240上及該介電層23之第一表面23a上，以令該線路層24透過該些導電盲孔240電性連接各該電極墊220及各該導電凸塊200。
如第4F圖所示，形成第一拒銲層25a於該介電層23之第一表面23a及該線路層24上。
如第4G圖所示，蝕刻移除全部之承載板20，以露出該介電層23之第二表面23b、該黏著層21及該些導電凸塊200；再以化學藥液移除該黏著層21，以外露該晶片22之非作用面22b。
如第4G’圖所示，於另一實施方式中，係蝕刻移除該承載板20之部分材料後，僅留下該晶片22之非作用面22b上之承載板20以供作為散熱片201，且露出該介電層23之第二表面23b及該些導電凸塊200。
如第4H圖所示，接續第4G圖之製程，於該第一拒銲層25a上形成複數第一開孔250a，以令該線路層24之部分表面露出於該第一開孔250a中；且形成第二拒銲層25b於該介電層23之第二表面23b、該晶片22之非作用面22b及該些導電凸塊200上，並於該第二拒銲層25b上形成複數第二開孔250b，以令該些導電凸塊200之部分表面外露於該些第二開孔250b中。
如第4I圖所示，於後續製程中，可形成如銲球或銲針之導電元件26於各該第一開孔250a中之線路層24上，以供外接其他電子裝置28，例如：半導體晶片、電路板或另一封裝件。亦可形成如銲球或銲針之導電元件27於各該第二開孔250b中之導電凸塊200上，以供外接其他電子裝置，例如：電路板、半導體晶片或另一封裝件。
如第4I’圖所示，若接續第4G’圖之製程，將於該第一拒銲層25a上形成該些外露該線路層24之第一開孔250a，且形成該些導電元件26於外露之線路層24上，以供外接其他電子裝置28。且亦形成第二拒銲層25b’於該介電層23之第二表面23b、該散熱片201及該些導電凸塊200上，且於該第二拒銲層25b’中形成複數第二開孔250b’，以令該些導電凸塊200之部分表面外露於該些第二開孔250b’中，俾供形成導電元件27於各該第二開孔250b’中之導電凸塊200上，以供外接其他電子裝置。
又如第4F’圖所示，亦可先形成增層結構29於該介電層23之第一表面23a及該線路層24上，再將該第一拒銲層25a’設於該增層結構29之最外層上，以令部分該增層結構29之最外層線路外露於該第一開孔250a’，俾供於後續製程中形成導電元件。又該增層結構29具有至少一介電層、設於該介電層上之線路、以及設於該介電層中且電性連接該線路層24與線路之導電盲孔。
另外，於其他實施例中，當移除該承載板20之後(如第4G或4G’圖)，亦可形成另一增層結構於該介電層23之第二表面23b上(未表示於圖式中)。
本發明藉由先將該晶片22設於該承載板20上，再以該介電層23包覆該晶片22，接著移除該承載板20，因無需使用如習知之膠膜，而得以避免習知技術所發生封裝膠體溢膠及晶片污染等問題。
再者，本發明將該晶片22以該非作用面22b設於該承載板20上，不會如習知技術中因膠膜受熱而發生伸縮問題，故該晶片22不會發生偏移，且於形成該介電層23時，該承載板20因不會受熱軟化，故該晶片22亦不會產生位移。因此，於重佈線製程時，該線路層24與晶片22之電極墊220不會接觸不良，有效避免廢品問題。
又，本發明藉由於該承載板20上形成該導電凸塊200，以增加支撐力，而使整體結構不會發生翹曲，有效避免如習知製程中以膠膜為支撐部而發生翹曲之問題，故該晶片22不會發生偏移。因此，於重佈線製程時，該線路層24與電極墊220不會接觸不良，有效避免廢品問題。
另外，本發明藉由該導電凸塊200之設計，當欲進行堆疊時，可透過如銲球之導電元件27直接外接其他電子裝置，不需如習知技術之貫穿封裝膠體以形成導電通孔，故本發明可簡化製程，且無需填充導電材料，有效減少製程時間，並降低成本。
本發明復提供一種嵌埋晶片之封裝件，係包括：具有相對之第一表面23a及第二表面23b之介電層23、設於該介電層23中並外露於該介電層23之第二表面23b之導電凸塊200、嵌設於該介電層23中之晶片22、係設於該介電層23之第一表面23a上之線路層24、係設於該介電層23中之導電盲孔240、以及設於該介電層23之第一表面23a及該線路層24上之第一拒銲層25a。
形成該導電凸塊200之材質係為銅。
所述之晶片22具有相對之作用面22a及非作用面22b，該作用面22a上設有複數電極墊220。
所述之線路層24透過該導電盲孔240電性連接該電極墊220及該導電凸塊200。
所述之第一拒銲層25a具有第一開孔250a，以令部分該線路層24外露於該第一開孔250a中。
所述之封裝件復包括導電元件26，係設於該第一開孔250a中之線路層24上。
所述之封裝件復包括增層結構29，係設於該介電層23之第一表面23a及該線路層24上，且該第一拒銲層25a設於該增層結構29之最外層上。
於一實施例中，該晶片22之非作用面22b外露於該介電層23之第二表面23b。且包括第二拒銲層25b，係設於該介電層23之第二表面23b、晶片22之非作用面22b及該導電凸塊200上，且該第二拒銲層25b具有複數第二開孔250b，以令該導電凸塊200之部分表面外露於該第二開孔250b中，俾供設置導電元件27。
於另一實施例中，該晶片22之非作用面22b上具有散熱片201。且包括第二拒銲層25b，係設於該介電層23之第二表面23b、散熱片201及該導電凸塊200上，且該第二拒銲層25b具有複數第二開孔250b，以令該導電凸塊200之部分表面外露於該第二開孔250b中，俾供設置導電元件27。
綜上所述，本發明嵌埋晶片之封裝件及其製法，係藉由導電凸塊之設計，當欲進行堆疊時，可透過銲球直接外接其他電子裝置，有效簡化製程，以減少製程時間且降低成本。再者，本發明使用承載板代替習知之膠膜，有效避免封裝膠體溢膠及晶片污染等問題。
又，藉由承載板設置晶片，且藉由導電凸塊增加整體結構之支撐力以避免結構發生翹曲，故該晶片不會發生偏移，因而於重佈線製程時，該線路層與晶片之電極墊不會接觸不良，有效避免廢品問題。另外，移除該承載板時，不會在介電層上殘留金屬材或黏膠。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1、28‧‧‧電子裝置
10‧‧‧導電通孔
100‧‧‧導電材料
11、11’‧‧‧膠膜
110‧‧‧翹曲
12、22‧‧‧晶片
120、220‧‧‧電極墊
121、22a‧‧‧作用面
122、22b‧‧‧非作用面
13‧‧‧封裝膠體
130‧‧‧溢膠
14、23‧‧‧介電層
15、24‧‧‧線路層
16‧‧‧拒銲層
17、17’‧‧‧銲球
18‧‧‧載具
19‧‧‧黏膠
190‧‧‧殘留黏膠
20‧‧‧承載板
200‧‧‧導電凸塊
201‧‧‧散熱片
21‧‧‧黏著層
23a．．．第一表面
23b．．．第二表面
230．．．盲孔
240．．．導電盲孔
25a、25a’．．．第一拒銲層
25b、25b’．．．第二拒銲層
250a、250a’．．．第一開孔
250b、250b’．．．第二開孔
26、27．．．導電元件
29．．．增層結構
A．．．置晶區
第1A至1C圖係為美國專利US6,271,469所揭露之晶圓級晶片尺寸封裝件之製法示意圖；第2圖係為美國專利US6,271,469所揭示之晶圓級晶片尺寸封裝件發生溢膠問題之示意圖；第3A至3D圖係為美國專利US6,271,469所揭示之晶圓級晶片尺寸封裝件發生封裝膠體翹曲、增設載具、封裝膠體表面殘膠及不易堆疊等問題之示意圖；以及第4A至4I圖係為本發明嵌埋晶片之封裝件之製法之示意圖其中，第4F’圖係為第4F圖之另一實施例，第4G’圖係為第4G圖之另一實施例，第4I’圖係為第4I圖之另一實施例。
200．．．導電凸塊
22．．．晶片
22a．．．作用面
22b．．．非作用面
220．．．電極墊
23．．．介電層
23a．．．第一表面
23b．．．第二表面
24．．．線路層
240．．．導電盲孔
25a．．．第一拒銲層
250a．．．第一開孔
25b．．．第二拒銲層
250b．．．第二開孔

Claims (18)

  1. 一種嵌埋晶片之封裝件，係包括：介電層，具有相對之第一表面及第二表面；導電凸塊，係設於該介電層中並外露於該介電層之第二表面；晶片，係嵌設於該介電層中，該晶片具有相對之作用面及非作用面，該作用面上設有複數電極墊；線路層，係設於該介電層之第一表面上；導電盲孔，係設於該介電層中，以令該線路層透過該導電盲孔電性連接該電極墊及該導電凸塊；以及第一拒銲層，係設於該介電層之第一表面及該線路層上，且該第一拒銲層具有第一開孔，以令部分該線路層外露於該第一開孔中。
  2. 如申請專利範圍第1項所述之嵌埋晶片之封裝件，其中，形成該導電凸塊之材質係為銅。
  3. 如申請專利範圍第1項所述之嵌埋晶片之封裝件，其中，該晶片之非作用面外露於該介電層之第二表面。
  4. 如申請專利範圍第3項所述之嵌埋晶片之封裝件，復包括第二拒銲層，係設於該介電層之第二表面、晶片之非作用面及該導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
  5. 如申請專利範圍第1項所述之嵌埋晶片之封裝件，其中，該晶片之非作用面上具有散熱片。
  6. 如申請專利範圍第5項所述之嵌埋晶片之封裝件，復包括第二拒銲層，係設於該介電層之第二表面、散熱片及該導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
  7. 如申請專利範圍第1項所述之嵌埋晶片之封裝件，復包括導電元件，係設於該第一開孔中之線路層上。
  8. 如申請專利範圍第1項所述之嵌埋晶片之封裝件，復包括增層結構，係設於該介電層之第一表面及該線路層上，且該第一拒銲層設於該增層結構之最外層上。
  9. 一種嵌埋晶片之封裝件之製法，係包括：提供一承載板，且於該承載板上具有相鄰之導電凸塊及置晶區；設置晶片於該承載板之置晶區上，該晶片具有相對之作用面及非作用面，且該作用面上設有複數電極墊，並以該非作用面接置於該承載板上；形成介電層於該承載板、導電凸塊及晶片上，以包覆該晶片，且該介電層具有外露之第一表面及結合至該承載板上之第二表面；形成線路層於該介電層之第一表面上，且於該介電層中形成導電盲孔，以令該線路層透過該導電盲孔電性連接該電極墊及該導電凸塊；形成第一拒銲層於該介電層之第一表面及該線路層上；移除該承載板，以露出該介電層之第二表面及該導電凸塊；以及於該第一拒銲層上形成複數第一開孔，以令該線路層之部分表面露出於該第一開孔中。
  10. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，其中，形成該承載板及導電凸塊之材質係為銅。
  11. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，復包括於該晶片之非作用面上塗佈黏著層，以令該晶片定位於該承載板上。
  12. 如申請專利範圍第11項所述之嵌埋晶片之封裝件之製法，復包括當移除該承載板後，再移除該黏著層，以外露該晶片之非作用面。
  13. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，其中，係使用蝕刻法移除該承載板。
  14. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，其中，於移除全部該承載板後，該晶片之非作用面係外露於該介電層之第二表面。
  15. 如申請專利範圍第14項所述之嵌埋晶片之封裝件之製法，復包括形成第二拒銲層於該介電層之第二表面、該晶片之非作用面及該些導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
  16. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，其中，僅移除該承載板之部分材料，俾該晶片之非作用面上之承載板部分供作為散熱片。
  17. 如申請專利範圍第16項所述之嵌埋晶片之封裝件之製法，復包括形成第二拒銲層於該介電層之第二表面、該散熱片及該些導電凸塊上，且該第二拒銲層具有複數第二開孔，以令該導電凸塊之部分表面外露於該第二開孔中。
  18. 如申請專利範圍第9項所述之嵌埋晶片之封裝件之製法，復包括形成導電元件於該第一開孔中之線路層上。
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