TWI469294B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

Info

Publication number
TWI469294B
TWI469294B TW101124878A TW101124878A TWI469294B TW I469294 B TWI469294 B TW I469294B TW 101124878 A TW101124878 A TW 101124878A TW 101124878 A TW101124878 A TW 101124878A TW I469294 B TWI469294 B TW I469294B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor
insulating layer
semiconductor package
active surface
Prior art date
Application number
TW101124878A
Other languages
English (en)
Other versions
TW201403774A (zh
Inventor
李孟宗
張江城
邱世冠
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101124878A priority Critical patent/TWI469294B/zh
Priority to CN201210256347.3A priority patent/CN103545277B/zh
Priority to US13/659,181 priority patent/US9041189B2/en
Publication of TW201403774A publication Critical patent/TW201403774A/zh
Application granted granted Critical
Publication of TWI469294B publication Critical patent/TWI469294B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2101—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種晶圓級之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
如第1A至1D圖，係為習知晶圓級半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之主動面12a與非主動面12b，各該主動面12a上均具有複數電極墊120，且各該主動面12a黏著於該熱化離型膠層11上。
如第1B圖所示，以模壓(molding)方式形成一封裝膠體15於該熱化離型膠層11上，以包覆該半導體元件12。
如第1C圖所示，進行烘烤製程以硬化該封裝膠體15，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之主動面12a。
如第1D圖所示，進行線路重佈層(Redistribution layer,RDL)製程，係形成一線路重佈結構16於該封裝膠體15與該半導體元件12之主動面12a上，令該線路重佈結構16電性連接該半導體元件12之電極墊120。
接著，形成一絕緣保護層17於該線路重佈結構16上，且該絕緣保護層17外露該線路重佈結構16之部分表面，以供結合銲球18。
惟，習知半導體封裝件1之製法中，該熱化離型膠層11於模壓製程中受熱時會膨脹，容易使黏附於該熱化離型膠層11上之半導體元件12產生偏移，如第1D’圖所示(亦即半導體元件12未置於置晶區B上)。故而，當該承載件10之尺寸越大時，各該半導體元件12間之位置公差亦隨之加大，致使該線路重佈結構16與該半導體元件12間之電性連接造成極大影響，因而造成良率過低。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：半導體元件，係具有相對之主動面與非主動面及相接該主動面與非主動面之側面，且該主動面上具有複數電極墊；絕緣層，係形成於該半導體元件之主動面與側面上，並令該些電極墊外露於該絕緣層，又該絕緣層之材質係為二氧化矽或氮化矽；以及線路層，係形成於該絕緣層上且電性連接該些電極墊。
前述之半導體封裝件中，該半導體元件之非主動面係 外露於該絕緣層。
前述之半導體封裝件中，該半導體元件之非主動面與該絕緣層之表面係不共平面。
本發明復提供一種半導體封裝件之製法，係包括：形成複數結合單元於一承載件上所定義之複數置晶區上，以令各該結合單元對應位於各該置晶區上；設置複數半導體元件於該結合單元上，以令各該半導體元件對應位於各該結合單元上，該半導體元件具有相對之主動面與非主動面及相接該主動面與非主動面之側面，該主動面上具有複數電極墊，且該非主動面係接至該結合單元上；形成絕緣層於該承載件與該些半導體元件之主動面與側面上，且令該些電極墊外露於該絕緣層；以及形成線路層於該絕緣層上，且該線路層電性連接該些電極墊。
前述之製法中，該結合單元係為膠材，且該結合單元係以網版印刷、點膠方式或圖案化方式形成。
前述之製法中，復包括移除該承載件與該結合單元。
前述之半導體封裝件及其製法中，復包括形成線路重佈結構於該絕緣層與該線路層上，且該線路重佈結構電性連接該線路層。
前述之半導體封裝件及其製法中，復包括形成介電層於該絕緣層與該線路層上，且該介電層具有複數外露該線路層之開孔，以於該開孔中形成凸塊底下金屬層。
前述之半導體封裝件及其製法中，形成介電層於該絕緣層與該線路層上，使該介電層係埋設該半導體元件、絕 緣層與該線路層，該介電層係具有相對之第一表面與第二表面，且該介電層之第二表面接觸該絕緣層。
另外，依上述，該絕緣層係由該半導體元件之主動面沿該半導體元件之側面延伸至該承載件上，且該線路層具有位於該承載件上之電性連接墊，使該電性連接墊之位置係低於該半導體元件之主動面。又該介電層之第一表面上係形成有開孔，以令該電性連接墊對應外露於該開孔。
由上可知，本發明之半導體封裝件及其製法，係藉由該結合單元僅對應形成於各該置晶區上，故於溫度變化時，該結合單元不會產生伸縮，而可避免該半導體元件產生偏移。因此，於進行後續製程時，該半導體元件之定位準確，該線路層與該半導體元件間之電性連接能有效對接，故能避免良率過低之問題。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如 “上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之半導體封裝件2之第一實施例之製法的剖面示意圖。
如第2A及2A’圖所示，提供一承載件20，該承載件20上定義有複數置晶區A。接著，形成複數結合單元21於該置晶區A上，以令各該結合單元21對應位於各該置晶區A上。
於本實施例中，該結合單元21係為膠材，且以網版印刷或點膠方式形成。該結合單元21亦可為感光膠材，並經圖案化方式形成。
如第2B圖所示，設置複數半導體元件22於該結合單元21上，以令各該半導體元件22對應位於各該結合單元21上，每一該半導體元件22具有相對之主動面22a與非主動面22b及相接該主動面22a與非主動面22b之側面22c，該主動面22a上具有複數電極墊220，且該非主動面22b係接至該結合單元21上。
如第2C圖所示，藉由化學氣相沉積(Chemical vapor deposition,CVD)製程，形成一絕緣層23於該承載件20與該些半導體元件22上，且令該些電極墊220外露於該絕緣層23。
於本實施例中，該些電極墊220係與該絕緣層23表 面齊平，以令該些電極墊220外露於該絕緣層23。
再者，該絕緣層23係為鈍化層(passivation layer)，其材質如二氧化矽(SiO2 )或氮化矽(silicon nitrate)。
如第2D圖所示，形成一線路層24於該絕緣層23上，且該線路層24水平電性連接該些電極墊220。
本發明之製法中，係藉由該結合單元21僅對應形成於各該置晶區A上，故於溫度變化時，該結合單元21不會產生伸縮，而可避免該半導體元件22產生偏移。因此，當該承載件20之尺寸越大時，各該半導體元件22間之位置公差不會隨之加大，故可精確控制該半導體元件22之精度，以於進行後續製程時，該半導體元件22之定位準確，該線路層24與該半導體元件22間之電性連接能有效對接，故能避免良率過低之問題。
如第2E圖所示，形成一介電層25於該絕緣層23與該線路層24上，且該介電層具有複數外露該線路層24之開孔，以於該開孔中及其周圍形成凸塊底下金屬層(Under Bump Metallurgy,UBM)280。
於本實施例中，該介電層25之材質係為聚亞醯胺(Polyimide,PI)或苯並環丁烯(Benezocy-clobutene,BCB)。
如第2F圖所示，形成如銲球28之導電元件於該凸塊底下金屬層280上，且移除該承載件20與該結合單元21，以外露該非主動面22b與該絕緣層23。
於本實施例中，該半導體元件22之非主動面22b與該絕緣層23之表面係不共平面。
於另一實施例中，如第2F’圖所示，亦可進行RDL製程，即形成一線路重佈結構26於該絕緣層23與該線路層24上。該線路重佈結構26可為多層線路結構，其包含複數重佈介電層260、及形成於該重佈介電層260上之線路261，以藉由該些線路261電性連接該線路層24。又可形成複數開孔260a於該最外層之重佈介電層260’上，以外露該線路261之部分表面，俾供形成凸塊底下金屬層(UBM)280以結合如銲球28之導電元件。
如第2G圖所示，進行切單製程，係沿如第2F圖所示之切割路徑S進行切割，以製作複數個半導體封裝件2。
第3A至3D圖係為本發明之半導體封裝件之第二實施例之製法的剖面示意圖。本實施例與第一實施例之差異僅在於線路層34之佈設，其它相同製程與結構不再贅述。
如第3A圖所示，係接續第2B圖之製程，將一絕緣層33由該半導體元件22之主動面22a沿該半導體元件22之側面22c延伸至該承載件20上。於本實施例中，該絕緣層33係具有複數開口330，以令該些電極墊220外露於該開口330。
接著，形成一線路層34於該絕緣層33上，且電性連接該開口330中之電極墊220。於本實施例中，該線路層34具有位於該承載件20上之電性連接墊340，使該電性連接墊340之位置係低於該半導體元件22之主動面22a。
如第3B圖所示，形成一介電層35於該絕緣層33與該線路層34上，使該介電層35係埋設該半導體元件22、絕緣層33與該線路層34，該介電層35係具有相對之第一表面35a與第二表面35b，且該介電層35之第二表面35b接觸該絕緣層33。又該介電層35之材質係為聚亞醯胺(Polyimide,PI)或苯並環丁烯(Benezocy-clobutene,BCB)。
接著，形成複數開孔350於該介電層35之第一表面35a上，以令該電性連接墊340外露於該開孔350。
如第3C圖所示，形成複數如銲球28之導電元件於該電性連接墊340上。
如第3D圖所示，移除該承載件20與該結合單元21之後，係外露該非主動面22b與該絕緣層33，且該半導體元件22之非主動面22b與該絕緣層33之表面係不共平面。再進行切單製程，以製作複數個半導體封裝件3。
於另一實施例中，如第3D’圖所示，可於該電性連接墊340上形成凸塊底下金屬層280，再於該凸塊底下金屬層280上形成該銲球28。
本發明復提供一種半導體封裝件2,3,3’，係包括：半導體元件22、絕緣層23,33以及線路層24,34。
所述之半導體元件22係具有相對之主動面22a與非主動面22b及相接該主動面22a與非主動面22b之側面22c，該主動面22a上具有複數電極墊220。
所述之絕緣層23,33係形成於該半導體元件22之主 動面22a與側面22c上，並令該些電極墊220外露於該絕緣層23,33，又該絕緣層23,33之材質係為二氧化矽或氮化矽。
所述之線路層24,34係形成於該絕緣層23,33上且電性連接該些電極墊220。
於一實施例中，所述之半導體封裝件2復包括介電層25，係形成於該絕緣層23與該線路層24上，且該介電層25具有複數外露該線路層24之開孔，以於該開孔中形成凸塊底下金屬層280。
於一實施例中，所述之半導體封裝件2復包括線路重佈結構26，其形成於該絕緣層23與該線路層24上，且電性連接該線路層24。
於一實施例中，所述之半導體封裝件3,3’復包括介電層35，係埋設該半導體元件22、絕緣層33與該線路層34，該介電層35具有相對之第一表面35a與第二表面35b，且該介電層35之第二表面35b係結合該絕緣層33。再者，該絕緣層33係由該半導體元件22之主動面22a沿該半導體元件22之側面22c延伸至該介電層35之第二表面35b上，且該線路層34具有位於該第二表面35b上之電性連接墊340，使該電性連接墊340之位置係低於該半導體元件22之主動面22a。又，該介電層35之第一表面35a上係形成有開孔350，以令該電性連接墊340對應外露於該開孔350，俾供結合如銲球28之導電元件。另外，該介電層35之材質係為聚亞醯胺(Polyimide,PI)或苯並環丁烯 (Benezocy-clobutene,BCB)。
於一實施例中，該半導體元件22之非主動面22b係外露於該絕緣層23,33，且該非主動面22b與該絕緣層23,33之表面係不共平面。
綜上所述，本發明之半導體封裝件及其製法，主要藉由該結合單元之形成方式，以避免該半導體元件產生偏移，進而提升產品之良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,3,3’‧‧‧半導體封裝件
10,20‧‧‧承載件
11‧‧‧熱化離型膠層
12,22‧‧‧半導體元件
12a,22a‧‧‧主動面
12b,22b‧‧‧非主動面
120,220‧‧‧電極墊
15‧‧‧封裝膠體
16,26‧‧‧線路重佈結構
17‧‧‧絕緣保護層
18,28‧‧‧銲球
21‧‧‧結合單元
22c‧‧‧側面
23,33‧‧‧絕緣層
24,34‧‧‧線路層
25,35‧‧‧介電層
260,260’‧‧‧重佈介電層
260a,350‧‧‧開孔
261‧‧‧線路
280‧‧‧凸塊底下金屬層
330‧‧‧開口
340‧‧‧電性連接墊
35a‧‧‧第一表面
35b‧‧‧第二表面
A,B‧‧‧置晶區
S‧‧‧切割路徑
第1A至1D圖係為習知半導體封裝件之製法的剖視示意圖；其中，第1D’圖係為第1C圖之上視圖；第2A至2G圖係為本發明之半導體封裝件之第一實施例之製法的剖視示意圖；其中，第2A’圖係為第2A圖之上視圖，第2F’圖係為第2F圖之另一實施例；以及第3A至3D圖係為本發明之半導體封裝件之第二實施例之製法的剖視示意圖；其中，第3D’圖係為第3D圖之另一實施例。
20‧‧‧承載件
21‧‧‧結合單元
22‧‧‧半導體元件
220‧‧‧電極墊
23‧‧‧絕緣層
24‧‧‧線路層

Claims (19)

  1. 一種半導體封裝件，係包括：半導體元件，係具有主動面、相對該主動面之非主動面及相接該主動面與非主動面之側面，且該主動面上具有複數電極墊；絕緣層，係形成於該半導體元件之主動面與側面上，並令該些電極墊外露於該絕緣層，又該絕緣層之材質係為二氧化矽或氮化矽；以及線路層，係形成於該絕緣層上且水平電性連接該些電極墊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之非主動面係外露於該絕緣層。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之非主動面與該絕緣層之表面係不共平面。
  4. 如申請專利範圍第1項所述之半導體封裝件，復包括線路重佈結構，係形成於該絕緣層與該線路層上，且電性連接該線路層。
  5. 如申請專利範圍第1項所述之半導體封裝件，復包括介電層，係形成於該絕緣層與該線路層上，且該介電層具有複數外露該線路層之開孔，以於該開孔中形成凸塊底下金屬層。
  6. 一種半導體封裝件，係包括：半導體元件，係具有主動面、相對該主動面之非 主動面、及相接該主動面與非主動面之側面，且該主動面上具有複數電極墊；介電層，係埋設該半導體元件，該介電層具有位於該主動面上之第一表面、及相對該第一表面之第二表面；絕緣層，係由該半導體元件之主動面沿該半導體元件之側面而埋設於該介電層中，且部分該絕緣層延伸至覆蓋該介電層之第二表面上，並令該半導體元件之非主動面外露於該絕緣層；以及線路層，係依該絕緣層由該半導體元件之主動面沿該半導體元件之側面延伸至該介電層之第二表面，以令該線路層埋設於該介電層中，且該線路層具有位於該介電層之第二表面上之電性連接墊，使該電性連接墊之位置係低於該半導體元件之主動面。
  7. 如申請專利範圍第6項所述之半導體封裝件，其中，該介電層之第二表面係結合該絕緣層。
  8. 如申請專利範圍第6項所述之半導體封裝件，其中，該介電層之材質係為聚亞醯胺或苯並環丁烯。
  9. 如申請專利範圍第6項所述之半導體封裝件，其中，該介電層之第一表面上係形成有開孔，以令該電性連接墊對應外露於該開孔。
  10. 一種半導體封裝件之製法，係包括：形成複數結合單元於一承載件上所定義之複數置晶區上，以令各該結合單元對應位於各該置晶區上； 設置複數半導體元件於該結合單元上，以令各該半導體元件對應位於各該結合單元上，該半導體元件具有主動面、相對該主動面之非主動面及相接該主動面與非主動面之側面，該主動面上具有複數電極墊，且該非主動面係接至該結合單元上；形成絕緣層於該承載件與該些半導體元件之主動面與側面上，且令該些電極墊外露於該絕緣層；形成線路層於該絕緣層上，且該線路層電性連接該些電極墊；以及移除該承載件與該結合單元。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該結合單元係為膠材。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該結合單元係以網版印刷、點膠方式或圖案化方式形成。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括形成線路重佈結構於該絕緣層與該線路層上，且該線路重佈結構電性連接該線路層。
  14. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括形成介電層於該絕緣層與該線路層上，且該介電層具有複數外露該線路層之開孔，以於該開孔中形成凸塊底下金屬層。
  15. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括形成介電層於該絕緣層與該線路層上，該介電 層係具有相對之第一表面與第二表面，且該介電層之第二表面接觸該絕緣層。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該介電層係埋設該半導體元件、絕緣層與該線路層。
  17. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該絕緣層係由該半導體元件之主動面沿該半導體元件之側面延伸至該承載件上，且該線路層具有位於該承載件上之電性連接墊，使該電性連接墊之位置係低於該半導體元件之主動面。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，復包括移除該承載件與該結合單元。
  19. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該介電層之第一表面上係形成有開孔，以令該電性連接墊對應外露於該開孔。
TW101124878A 2012-07-11 2012-07-11 半導體封裝件及其製法 TWI469294B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW101124878A TWI469294B (zh) 2012-07-11 2012-07-11 半導體封裝件及其製法
CN201210256347.3A CN103545277B (zh) 2012-07-11 2012-07-23 半导体封装件及其制法
US13/659,181 US9041189B2 (en) 2012-07-11 2012-10-24 Semiconductor package and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101124878A TWI469294B (zh) 2012-07-11 2012-07-11 半導體封裝件及其製法

Publications (2)

Publication Number Publication Date
TW201403774A TW201403774A (zh) 2014-01-16
TWI469294B true TWI469294B (zh) 2015-01-11

Family

ID=49913300

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101124878A TWI469294B (zh) 2012-07-11 2012-07-11 半導體封裝件及其製法

Country Status (3)

Country Link
US (1) US9041189B2 (zh)
CN (1) CN103545277B (zh)
TW (1) TWI469294B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104091793B (zh) * 2014-07-18 2016-09-21 华进半导体封装先导技术研发中心有限公司 提高可靠性的微凸点结构及制作方法
CN107768320A (zh) * 2016-08-18 2018-03-06 恒劲科技股份有限公司 电子封装件及其制法
FR3057993B1 (fr) * 2016-10-25 2019-04-19 3Dis Technologies Systeme electronique comportant une puce electronique formant boitier et procede de fabrication
KR102029535B1 (ko) * 2017-08-28 2019-10-07 삼성전기주식회사 팬-아웃 반도체 패키지
US10665522B2 (en) 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030134455A1 (en) * 2002-01-15 2003-07-17 Jao-Chin Cheng Method of forming IC package having upward-facing chip cavity
TW554500B (en) * 2002-07-09 2003-09-21 Via Tech Inc Flip-chip package structure and the processing method thereof
TW200638499A (en) * 2005-04-26 2006-11-01 Phoenix Prec Technology Corp Carrying structure of electronic component
TW201216426A (en) * 2010-10-06 2012-04-16 Siliconware Precision Industries Co Ltd Package of embedded chip and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
KR100609011B1 (ko) * 2003-12-05 2006-08-03 삼성전자주식회사 웨이퍼 레벨 모듈 및 그의 제조 방법
TWI229433B (en) * 2004-07-02 2005-03-11 Phoenix Prec Technology Corp Direct connection multi-chip semiconductor element structure
TWI237885B (en) * 2004-10-22 2005-08-11 Phoenix Prec Technology Corp Semiconductor device having carrier embedded with chip and method for fabricating the same
US20080258293A1 (en) * 2007-04-17 2008-10-23 Advanced Chip Engineering Technology Inc. Semiconductor device package to improve functions of heat sink and ground shield
KR20080105242A (ko) * 2007-05-30 2008-12-04 삼성전자주식회사 칩 스케일 반도체 패키지
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
US8119454B2 (en) * 2008-12-08 2012-02-21 Stmicroelectronics Asia Pacific Pte Ltd. Manufacturing fan-out wafer level packaging
US8541877B2 (en) * 2009-12-16 2013-09-24 Chia-Lun Tsai Electronic device package and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030134455A1 (en) * 2002-01-15 2003-07-17 Jao-Chin Cheng Method of forming IC package having upward-facing chip cavity
TW554500B (en) * 2002-07-09 2003-09-21 Via Tech Inc Flip-chip package structure and the processing method thereof
TW200638499A (en) * 2005-04-26 2006-11-01 Phoenix Prec Technology Corp Carrying structure of electronic component
TW201216426A (en) * 2010-10-06 2012-04-16 Siliconware Precision Industries Co Ltd Package of embedded chip and manufacturing method thereof

Also Published As

Publication number Publication date
CN103545277B (zh) 2016-10-05
TW201403774A (zh) 2014-01-16
US9041189B2 (en) 2015-05-26
CN103545277A (zh) 2014-01-29
US20140015125A1 (en) 2014-01-16

Similar Documents

Publication Publication Date Title
KR102170575B1 (ko) 휨 감소를 위한 인포 패키지 지지
TWI517274B (zh) 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
TWI582913B (zh) 半導體封裝件及其製法
TWI463619B (zh) 半導體封裝件及其製法
TWI570842B (zh) 電子封裝件及其製法
TWI544599B (zh) 封裝結構之製法
TWI541954B (zh) 半導體封裝件及其製法
TWI446501B (zh) 承載板、半導體封裝件及其製法
TWI551199B (zh) 具電性連接結構之基板及其製法
TW201643971A (zh) 晶圓級封裝及其製作方法
TWI543323B (zh) 中介板及其製法
TWI587458B (zh) 電子封裝件及其製法與基板結構
TWI611486B (zh) 半導體結構及其製法
TWI652774B (zh) 電子封裝件之製法
TWI469294B (zh) 半導體封裝件及其製法
TWI550783B (zh) 電子封裝件之製法及電子封裝結構
TWI544593B (zh) 半導體裝置及其製法
TWI545702B (zh) 半導體封裝件及其製法
TWI601259B (zh) 電子封裝件及其半導體基板與製法
TWI471952B (zh) 晶片尺寸封裝件之製法
TWI641094B (zh) 基板結構及其製法
TWI515841B (zh) 半導體封裝件及其製法
TW201637139A (zh) 電子封裝結構及電子封裝件之製法
TWI467723B (zh) 半導體封裝件及其製法
TWI556381B (zh) 半導體封裝件及其製法