TW201643971A - 晶圓級封裝及其製作方法 - Google Patents

晶圓級封裝及其製作方法 Download PDF

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Publication number
TW201643971A
TW201643971A TW104122470A TW104122470A TW201643971A TW 201643971 A TW201643971 A TW 201643971A TW 104122470 A TW104122470 A TW 104122470A TW 104122470 A TW104122470 A TW 104122470A TW 201643971 A TW201643971 A TW 201643971A
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Taiwan
Prior art keywords
wafer
semiconductor device
dummy
layer
bumps
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TW104122470A
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English (en)
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TWI616957B (zh
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施信益
施能泰
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華亞科技股份有限公司
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Publication of TW201643971A publication Critical patent/TW201643971A/zh
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Abstract

本發明披露一半導體元件，包含一中介層，具有一第一面及相對於第一面的第二面；至少一主動晶片，藉由複數個第一凸塊安裝至該第一面的一晶片接合區域內；至少一虛設晶片，安裝至該第一面的該晶片接合區域旁的一周邊區域內；一成型模料設置於該第一面上，且該成型模料覆蓋該至少一主動晶片與該至少一虛設晶片；以及複數個焊接凸塊，設置於該第二面上。

Description

晶圓級封裝及其製作方法
本發明概括而言係關於半導體封裝領域，特別是關於一種無基底或無穿矽通孔(through silicon via, TSV)的中介層及其製作方法。
半導體封裝領域中所熟知的扇出晶圓級封裝(FOWLP)，是藉由位於基底上的重佈線層(RDL)，例如位於具有穿矽通孔(TSV)的基底，將原本半導體晶粒的接墊重新佈線分配至一較大的區域。
重佈線層是在晶圓表面上形成介電層與金屬導線的疊層，將晶片原本的輸入/輸出(I/O)接墊重新佈線分配至一個間距較寬鬆的佈局範圍。上述重佈線的製作通常使用薄膜聚合物，例如苯併環丁稀(Benzocyclobutene, BCB)、聚亞醯胺(polyimind, PI)，或其他有機聚合物作為介電層材料，再以金屬化製程，例如鋁或銅，形成金屬導線，將晶片周圍的接墊重新佈線分配成陣列狀連接墊。
由於製程繁複，具有穿矽通孔的中介層基底成本較高，因此，使用具有穿矽通孔中介層的扇出晶圓級封裝也會比較昂貴，並不利於特定的應用場合。
此外，晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數(CTE)差異，容易導致封裝翹曲變形，也使得封裝整體的厚度增加。晶圓翹曲一直是該領域關注的問題。
晶圓翹曲使晶片與晶圓間的接合不易維持，使“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製，問題更為嚴重。因此，業界仍需要一個改良的晶圓級封裝方法，可以解決上述先前技術的問題。
本發明的主旨在於提供一種改良的半導體元件及其製作方法，可減少中介層上的成型模料用量，因而改善成型後的翹曲問題。
根據本發明提供的半導體元件，包含一中介層，具有一第一面及相對於第一面的第二面；至少一主動晶片，藉由複數個第一凸塊安裝至該第一面的一晶片接合區域內；至少一虛設晶片，安裝至該第一面的該晶片接合區域旁的一周邊區域內；一成型模料設置於該第一面上，且該成型模料覆蓋該至少一主動晶片與該至少一虛設晶片；以及複數個焊接凸塊，設置於該第二面上。
根據本發明一實施例，該虛設晶片藉由複數個設置在該周邊區域內的虛設接墊上的第二凸塊安裝至該第一面上。
根據本發明另一實施例，該虛設晶片直接藉由一黏著劑安裝至該第一面上。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。
本發實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參照第1圖至第8圖，為根據本發明一實施例的示意性剖面圖，例示使用無基底或無穿矽通孔的中介層製作一晶圓級封裝的方法。
如第1圖所示，預備一載板300。載板300例如為可卸式基底材料，可以包含一黏著層 (圖未示)。載板300的頂面上包含至少一介電層或鈍化層310。鈍化層310可包含有機材料，例如聚亞醯胺(polyimide, PI)，或無機材料，例如氮化矽、氧化矽或類似的材料。
接著，如第2圖所示，在鈍化層310上方形成重佈線層(RDL)410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如聚亞醯胺(polyimide, PI)，或無機材料，例如氮化矽、氧化矽或類似的材料，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據所述實施例，金屬層414可包含複數個凸塊墊415a和虛設接墊415b，自介電層412的頂面暴露出來。凸塊墊415a設置於晶片接合區域102內，而虛設接墊415b設置於晶片接合區域102外，例如設置在晶片接合區域102的周邊區域104內。
根據所述實施例，虛設接墊415b為孤立、閒置的接墊，未與重佈線層410的金屬導線電性連接。換句話說，當晶片封裝體在操作模式時，不會有訊號通過虛設接墊415b至其他地方。
如第3圖所示，在重佈線層410上形成複數個凸塊416a與416b，例如微凸塊，作為後續連接使用。凸塊416a可直接形成在金屬層414個別的凸塊墊415a上。凸塊416b可直接形成在金屬層414個別的虛設接墊415b上。在某些實施例中，形成凸塊416a與416b之前，可以在重佈線層410上形成一鈍化層或介電層(圖未示)。
如第4圖所示，形成凸塊416a與416b之後，個別的覆晶晶片或晶粒420a以主動面朝下面對重佈線層410，藉由凸塊416a安裝至重佈線層410上，形成“晶片對晶圓接合”的堆疊結構。這些個別的覆晶晶片或晶粒420a為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。
根據所述實施例，虛設晶片420b藉由凸塊416b安裝至晶片接合區域102旁的周邊區域104內。第8圖例示主動晶片420a與虛設晶片420b在重佈線層上的佈局方式。虛設晶片420b可以是矽晶片、晶粒、或尺寸與主動晶片420a接近的元件，但並不限於此。須了解的是虛設晶片420b也可包含其他材料，例如金屬、玻璃或陶瓷。
上述步驟完成後，可選擇性地在每一晶片或晶粒420a/420b下方填充底膠(圖未示)。隨後，進行熱處理，使凸塊416a和416b迴焊。
如第5圖所示，晶粒接合完成後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住安裝在重佈線層上的主動晶片420a與虛設晶片420b，同時也覆蓋住重佈線層410的頂面。成型模料500隨後會藉由一固化製程使之固化。成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
接著，可選擇性地研磨移除部分成型模料500的上部，使主動晶片420a與虛設晶片420b的頂面暴露出來。
由於晶片接合區域102的周邊區域104中大多都設有虛設晶片420b，因此可減少成形模料500的用量，降低甚至完全避免基底或晶圓發生翹曲變形的情況。根據所述實施例，虛設晶片420b也可稱之為翹曲控制虛設晶片。
如第6圖所示，形成成型模料500後，再將載板300剝離，使鈍化層310暴露出來，形成無穿矽通孔的中介層301。例如，可利用雷射剝離技術或紫外光照射技術來剝離載板300，但不限於此。
剝離載板300時，可提供另一個暫時性的載板(圖未示)固定於成型模料500上方。載板300剝離完成後，接著在鈍化層310形成開口，使金屬層的焊接墊暴露出來，然後在個別焊接墊上形成焊接凸塊或焊接球520。
隨後，如第7圖所示，進行切割製程，分隔出個別的晶圓級封裝10。
請參照第9圖至第13圖，為根據本發明另一實施例的示意性剖面圖，例示使用無基底或無穿矽通孔的中介層製作一晶圓級封裝的方法，其中仍沿用相同的附圖標記，表示相似的區域、材料層或元件。
請參考第9圖，如同前一個實施例，在鈍化層310上方形成重佈線層410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如聚亞醯胺(PI)，或無機材料，例如氮化矽、氧化矽或類似的材料，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據所述實施例，金屬層414包含複數個凸塊墊415，自介電層412的頂面暴露出來。凸塊墊415位於晶片接合區域102內。大致上，晶片接合區域102以外的周邊區域104不具有凸塊墊。重佈線層410包含複數個凸塊416，例如微凸塊，以供後續連接使用。凸塊416可直接形在金屬層414個別的凸塊墊415上。
如第10圖所示，形成凸塊416後，個別的覆晶晶片或晶粒420a以主動面朝下面對重佈線層410，藉由凸塊416安裝至重佈線層410上，形成“晶片對晶圓接合”的堆疊結構。可選擇性地在每一晶片或晶粒420a下方填充底膠(圖未示)。隨後，進行熱處理，使凸塊416迴焊。
根據所述實施例，虛設晶片420b藉由黏著劑430，直接固定在晶片接合區域102外的周邊區域104的重佈線層410的介電層412上。
如第11圖所示，晶粒接合完成後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住安裝在重佈線層上的主動晶片420a和虛設晶片420b，同時也覆蓋住重佈線層410的頂面。成型模料500隨後會藉由一固化製程使之固化。後續，可選擇性地研磨移除部分成型模料500的上部，使主動晶片420a與虛設晶片420b的頂面暴露出來。
如第12圖所示，形成成型模料500後，再將載板300剝離，使鈍化層310暴露出來，形成無穿矽通孔的中介層301。例如，可利用雷射剝離技術或紫外光照射技術來剝離載板300，但不限於此。
剝離載板300時，可以提供另一個暫時性的載板(圖未示)固定於成型模料500上方。載板300剝離完成後，接著在鈍化層310形成開口，使金屬層的焊接墊暴露出來，然後在個別焊接墊上形成焊接凸塊或焊接球520。
隨後，如第13圖所示，進行切割製程，分隔出個別的晶圓級封裝10。        該領域中的技術人士可輕易知道在本發明的教示範圍內，依然可做許多修改。因此，以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
102‧‧‧晶片接合區域
104‧‧‧周邊區域
300‧‧‧載板
310‧‧‧鈍化層
410‧‧‧重佈線層
412‧‧‧介電層
414‧‧‧金屬層
430‧‧‧黏著劑
500‧‧‧成型模料
520‧‧‧焊接凸塊
415/415a/415b‧‧‧凸塊墊
416/416a/416b‧‧‧凸塊
420a‧‧‧覆晶晶片
420b‧‧‧虛設晶片
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。        第1圖至第8圖為根據本發明一實施例的示意性剖面圖，例示使用無基底或無穿矽通孔的中介層製作一晶圓級封裝的方法，其中:              第1圖至第7圖為示意性剖面圖，為本發明一實施例的晶圓級封裝製程的中間產物；              第8圖為俯視圖，例示主動晶片與虛設晶片在重佈線層上的佈局；以及        第9圖至第13圖為為根據本發明另一實施例的示意性剖面圖，例示使用無基底或無穿矽通孔的中介層製作一晶圓級封裝的方法。
310‧‧‧鈍化層
410‧‧‧重佈線層
412‧‧‧介電層
414‧‧‧金屬層
500‧‧‧成型模料
520‧‧‧焊接凸塊
415a/415b‧‧‧凸塊墊
416a/416b‧‧‧凸塊
420a‧‧‧覆晶晶片
420b‧‧‧虛設晶片

Claims (10)

  1. 一半導體元件，包含:        一中介層，具有一第一面及相對於第一面的第二面；        至少一主動晶片，藉由複數個第一凸塊安裝至該第一面的一晶片接合區域內；        至少一虛設晶片，安裝至該第一面的該晶片接合區域旁的一周邊區域內；        一成型模料設置於該第一面上，且該成型模料覆蓋該至少一主動晶片與該至少一虛設晶片；以及        複數個焊接凸塊，設置於該第二面上。
  2. 如申請專利範圍第1項所述的半導體元件，其中該中介層包含一重佈線層。
  3. 如申請專利範圍第2項所述的半導體元件，其中該重佈線層包含至少一介電層與至少一金屬層。
  4. 如申請專利範圍第1項所述的半導體元件，其中該中介層不包含一穿矽通孔。
  5. 如申請專利範圍第1項所述的半導體元件，其中該主動晶片為一具有特定功能的主動積體電路晶片。
  6. 如申請專利範圍第5項所述的半導體元件，其中該主動晶片可包含一繪圖處理器、一中央處理器，或一記憶體晶片。
  7. 如申請專利範圍第1項所述的半導體元件，其中該虛設晶片為一虛設矽晶片。
  8. 如申請專利範圍第1項所述的半導體元件，其中該虛設晶片藉由複數個設置在該周邊區域的虛設接墊上的第二凸塊安裝至該第一面上。
  9. 如申請專利範圍第1項所述的半導體元件，其中該虛設晶片藉由一黏著劑直接安裝至該第一面上。
  10. 如申請專利範圍第1項所述的半導體元件，其中另包含一鈍化層位於該第二面上。
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US10043769B2 (en) 2018-08-07
US20210175188A1 (en) 2021-06-10
US20160358865A1 (en) 2016-12-08
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