TWI517274B - 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法 - Google Patents

晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法 Download PDF

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Publication number
TWI517274B
TWI517274B TW101109611A TW101109611A TWI517274B TW I517274 B TWI517274 B TW I517274B TW 101109611 A TW101109611 A TW 101109611A TW 101109611 A TW101109611 A TW 101109611A TW I517274 B TWI517274 B TW I517274B
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Prior art keywords
layer
wafer
forming
fabricating
dielectric layer
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TW101109611A
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English (en)
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TW201340221A (zh
Inventor
程呂義
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矽品精密工業股份有限公司
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Priority to TW101109611A priority Critical patent/TWI517274B/zh
Priority to CN201210097680.4A priority patent/CN103325696B/zh
Priority to US13/628,582 priority patent/US9269602B2/en
Publication of TW201340221A publication Critical patent/TW201340221A/zh
Application granted granted Critical
Publication of TWI517274B publication Critical patent/TWI517274B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Description

晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
本發明係關於半導體封裝件之製法，特別是關於一種提升精度之晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
第6452265號美國專利與第7202107號美國專利係提供一種晶圓級封裝之製法。請參閱第1A至1E圖，係為習知晶圓級半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載板10上。
如第1B圖所示，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a結合於該熱化離型膠層11上。
如第1C圖所示，以模壓(molding)方式形成一封裝膠體13於該半導體元件12與該熱化離型膠層11上。
如第1D圖所示，移除該熱化離型膠層11與該承載板10，以外露該半導體元件12之作用面12a。
如第1E圖所示，進行重佈線路層(Redistribution layer,RDL)及凸塊(Bump)之製程，即形成一線路結構14於該封裝膠體13與該半導體元件12之作用面12a上，令該線路結構14電性連接該半導體元件12之電極墊120。
惟，習知半導體封裝件1之製法中，該熱化離型膠層11具有撓性，其於模壓製程中之熱膨脹係數(Coefficient of thermal expansion,CTE)及受封裝膠體13之側推力將影響半導體元件12(如晶片)固定之精度，因而當進行重新排列之承載板10尺寸越大時，各該半導體元件12間之位置公差亦隨之加大，造成該RDL及Bump製程之良率損失。
再者，習知之製法中，先形成該封裝膠體13封裝該半導體元件12，再進行RDL製程，若於後續測試中，偵測該線路結構14之良率不佳時，需將半導體封裝件1整體作廢，亦即一併將良好之半導體元件12作廢，故習知製程容易浪費材料，亦即丟棄良好之半導體元件12，致使成本提高，因而完全不符合經濟效益。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種晶圓級封裝基板之製法，係包括：形成第一介電層於一承載板上，且該第一介電層形成有複數第一開孔以外露該承載板之部分表面；形成線路層於該第一介電層之部分表面與該第一開孔上；形成第二介電層於該第一介電層之部分表面與該線路層上，且該第二介電層形成有複數第二開孔以外露該線路層之部分表面；以及形成導電凸塊於該第二開孔中之線路層上，以電性連接該線路層。
前述之封裝基板之製法中，復可包括移除該承載板，以露出該線路層。
本發明復提供一種晶圓級半導體封裝件之製法，係包括：提供一承載封裝基板之承載板，該封裝基板包含有結合於該承載板上之第一介電層及設於該第一介電層上之第二介電層，該第一介電層上形成有線路層，且該線路層亦結合於該承載板上，而該第二介電層上係形成有導電凸塊，以電性連接該線路層；結合半導體元件於該導電凸塊上，該半導體元件具有結合至該導電凸塊上之作用面與相對該作用面之非作用面；形成封裝膠體於該第二介電層上，以包覆該半導體元件；以及移除該承載板，以露出該線路層。
前述之封裝件之製法中，該半導體元件之作用面上可具有導電部，以藉由點膠製程或迴銲製程，可將銲錫或膠材電性連接至該導電凸塊上。
前述之封裝件之製法中，該半導體元件係為單一晶片或堆疊晶片組結構。
前述之封裝件之製法中，該封裝膠體可外露該半導體元件之非作用面。
前述之封裝件之製法復可包括研磨該封裝膠體，以薄化其厚度。
前述之封裝件之製法中，復可包括於形成封裝膠體之前，可形成底膠於該半導體元件與該第二介電層之間。
前述之封裝件之製法中，復可包括切單製程。
前述之兩種製法中，形成該第一與第二介電層之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)、聚對二唑苯(Polybenzoxazole,PBO)、二氧化矽或氮化矽。
前述之兩種製法中，該承載板係可為矽晶圓、玻璃板、表面具鋁層之板體或鋁板；較佳地，可為表面具鋁層之矽晶圓。
前述之兩種製法中，形成該線路層之製程可包括：形成一金屬層於該第一介電層之全部表面與該第一開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該線路層於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
前述之兩種製法中形成該導電凸塊之製程可包括：形成一金屬層於該第二介電層之全部表面與該第二開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該導電凸塊於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
前述之兩種製法中，該導電凸塊係可含有銲錫材料，並迴銲該導電凸塊。
前述之兩種製法中，復可包括形成線路增層結構於該第一介電層與該第二介電層之間，且電性連接該線路層與該導電凸塊。
前述之兩種製法中，可藉由研磨製程或蝕刻製程，移除該承載板。
另外，前述之兩種製法中，復可包括於移除該承載板之後，形成導電元件於該露出之線路層上。
由上可知，本發明晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法，係藉由先製作線路層，再移除該承載板，故於移除該承載板之後無需再進行RDL製程。因此，相較於習知技術，本發明於製作線路層時，可避免熱化離型膠層之熱膨脹係數及撓性影響半導體元件固定之精度，因而當進行重新排列之承載板尺寸越大時，各該半導體元件間之位置公差不會隨之加大，故可精確控制半導體元件重新排列之精度。
再者，本發明之製法係先製作線路層，再置放半導體元件，故可先偵測該線路層之良率，待測試完成後，再置放該半導體元件，因而必要時只需將半成品作廢，而不需將半導體元件作廢。因此，相較於習知技術，本發明之製法不會浪費材料，亦即不會丟棄良好之半導體元件，因而有效降低成本，以符合經濟效益。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2K圖，係為本發明之晶圓級半導體封裝件2之製法之剖面示意圖。
如第2A圖所示，以塗佈方式形成一第一介電層21於一承載板20上，且進行圖案化製程，於該第一介電層21上形成複數第一開孔210，以外露該承載板20之部分表面。
於本實施例中，形成該第一介電層21之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)，且該承載板20係為矽晶圓、玻璃板、表面具鋁層之板體或鋁板，較佳為表面具濺鍍鋁層之矽晶圓，但該承載板20之種類僅需為剛性材質即可，並不限於上述。
如第2B圖所示，以濺鍍方式形成一第一金屬層22於該第一介電層21之全部表面與該第一開孔210上。
接著，以塗佈方式形成如光阻之阻層23a於該第一金屬層22上，且以曝光、顯影方式進行圖案化製程，於該阻層23a上形成複數開口230a，以外露該第一金屬層22之部分表面與該些第一開孔210中之第一金屬層22。
於本實施例中，該第一金屬層22可作為供電鍍用之導電層(seed layer)，且形成該第一金屬層22的材質為Ti、Cu、Ni、V、Al、W、Au或其組成，但不限於此。
如第2C圖所示，利用該第一金屬層22作為電流路徑，電鍍形成線路層24於該些開口230a中之第一金屬層22上。
於本實施例中，形成該線路層24之材質可為銅(Cu)或鋁(Al)等，但不限於此。
如第2D圖所示，剝除該阻層23a，且以蝕刻方式將該阻層23a下方之第一金屬層22移除。
如第2E圖所示，以塗佈方式形成第二介電層25於該第一介電層21之部分表面與該線路層24上，且以曝光、顯影方式進行圖案化製程，於該第二介電層25上形成複數第二開孔250，以外露該線路層24之部分表面。
接著，以濺鍍方式形成第二金屬層26於該第二介電層25之全部表面與該第二開孔250上。
於本實施例中，形成該第二介電層25之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)，且形成該第二金屬層26的材質為Ti、Cu、Ni、V、Al、W、Au或其組成，但該第二金屬層26的材質不限於此。
如第2F圖所示，以塗佈方式形成如光阻之另一阻層23b於該第二金屬層26上，且以曝光、顯影方式進行圖案化製程，於該另一阻層23b上形成複數開口230b，以外露該第二開孔250上及其周圍之第二金屬層26之表面。
接著，利用該第二金屬層26作為電鍍用之電流途徑，以電鍍形成導電凸塊27於該些開口230b中之第二金屬層26上，令該導電凸塊27電性連接該線路層24。
於本實施例中，該導電凸塊27係含有銲錫材料，如錫銀(Sn-Ag)無鉛銲料，且該銲錫材料中亦可含有Cu、Ni或Ge等，但該導電凸塊27之材質無特別限制。又該第二金屬層26亦作為凸塊底下金屬(Under Bump Metallurgy,UBM)。
如第2G圖所示，剝除該另一阻層23b，且以蝕刻方式將該另一阻層23b下方之第二金屬層26移除。接著，迴銲該導電凸塊27。
如第2G’圖所示，於另一實施例中，該第一與第二介電層21’,25’可為二氧化矽(SiO2)或氮化矽(silicon nitrate)，並以電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition,PECVD)之方式形成，且以乾蝕刻方式形成第一與第二開孔210’,250’。
再者，若該承載板20為鋁板或表面為濺鍍鋁層之矽晶圓，即可進行電測，以得到該線路層24與導電凸塊27之良率。因此，若偵測該線路層24與導電凸塊27之良率不佳時，即可將該半成品(即該承載板20及其上之結構)作廢，而不須進行後續之置晶與封裝製程，故本發明之製法可有效控管品質，以避免丟棄良好之半導體元件。
如第2H圖所示，接續第2G圖之製程，結合一半導體元件28於該導電凸塊27上，該半導體元件28具有結合至該導電凸塊27上之作用面28a與相對該作用面28a之非作用面28b。
於本實施例中，該半導體元件28上具有用以結合銅導電部280a之電極墊280，且可選擇性地於該導電部280a上形成銲錫或膠材280b，如：非導電銲膏(Non Conductive Paste,NCP)或異方性導電膜(anisotropic conductive film,ACF)等方式，以藉由迴銲製程或點膠製程，將導電部280a精準對位結合且電性連接於該導電凸塊27，以形成銲接點27’，令該半導體元件28固設於該第二介電層25上，如第2I圖所示。
再者，該半導體元件28係為單一晶片；而於其他實施例中，該半導體元件可為堆疊晶片組結構。
又，如第2H’圖所示，亦接續第2G圖之製程，係移除該承載板20，以露出該第一金屬層22，俾形成一晶圓級封裝基板2a。例如：若該承載板20為矽晶圓，可先藉由研磨製程移除該承載板20至一定之薄度後，再以乾蝕刻及化學機械研磨(Chemical Mechanical Polishing,CMP)之方式，移除剩餘之承載板20。
另外，如第2H”圖所示，亦可於第2D圖之製程後，形成線路增層結構24a於該第一介電層21之部分表面與該線路層24上，再形成第二介電層25於該線路增層結構24a上。
於本實施例中，該線路增層結構24a具有至少一增層介電層240與形成於該增層介電層240上之增層線路層241，且該增層線路層241電性連接該線路層24與該導電凸塊27。
如第2I圖所示，接續第2H圖之製程，形成底膠29a於該半導體元件28與該第二介電層25之間，再形成封裝膠體29b於該第二介電層25上，以包覆該半導體元件28與底膠29a。
如第2J圖所示，研磨該封裝膠體29b，以薄化其厚度或印字。
接著，移除該承載板20，以露出該第一金屬層22。例如：若該承載板20為矽晶圓，可先藉由研磨製程移除該承載板20至一定之薄度後，再以乾蝕刻及化學機械研磨(Chemical Mechanical Polishing,CMP)之方式，移除剩餘之承載板20。
如第2K圖所示，形成導電元件30於該露出之第一金屬層22上，令該第一金屬層22作為凸塊底下金屬(Under Bump Metallurgy,UBM)。之後，再進行切單製程。
於本實施例中，該導電元件30可為銲球、凸塊或導針等，並無特別限制。
再者，若接續第2G’圖之製程，將形成如第2K’圖所示之半導體封裝件2’。
又，亦可接續第2H”圖之製程，以形成具有該線路增層結構24a之半導體封裝件(圖略)。
另外，若於模壓製程中可克服氣洞問題，即可省略形成底膠29a之製程，直接形成封裝膠體29b’，如第2K’圖所示。或者，於研磨製程中，係可依厚度需求研磨該封裝膠體29b’，如第2K”圖所示之半導體封裝件2”，令該封裝膠體29b’之頂面與該半導體元件28之非作用面28b齊平，使該封裝膠體29b’外露該半導體元件28之非作用面28b，以增加散熱效果。
本發明之製法於移除該承載板20之後無需再製作線路層24，亦即先製作線路層24，再進行後續作業，如：形成封裝膠體29b,29b’,29b”，故該封裝膠體29b,29b’,29b”之熱膨脹係數不可能影響半導體元件28固定之精度，因而免去半導體元件28重複經RDL製程之熱效應影響。因此，當進行重新排列之承載板20尺寸越大時，各該半導體元件28間之位置公差不會隨之加大，故可精確控制半導體元件28重新排列之精度。例如：當半導體元件28表面之電極墊280間距為40um時，亦可在12吋晶圓(承載板20)的作業面積內精準對位其固定位置，而不受熱化離型膠層之熱膨脹係數及撓性之影響，不僅可大幅提高良率，且可節省成本。
再者，本發明之製法中，先製作線路層24，再置放該半導體元件28，故可先偵測該線路層24之良率，待測試完成後，再置放該半導體元件28。若該線路層24之良率不佳時，只需將半成品作廢，不需將半導體元件28作廢。因此，本發明之製法不會浪費材料，亦即不會丟棄良好之半導體元件28，故可節省製作成本。
又，若該承載板20之表面為導體，以於製作線路層24與導電凸塊27完成後，即可直接進行電測(不需外接其他電子裝置)，以確定得到良品後，再置放該半導體元件28，故不僅可大幅提高良率，且可節省製作之時間成本。
綜上所述，本發明之晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法，係藉由半導體元件上之導電部精準對位導電凸塊後，經封裝膠體固定後，再移除該承載板，故不會受熱化離型膠層影響半導體元件固定之精度，不僅有效提高良率，且可節省成本。
再者，藉由先製作線路層，以於偵測該線路層之良率之後，再置放該半導體元件，因而避免將良好之半導體元件與封裝件一同作廢，故可節省製作成本及提高良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’,2”．．．半導體封裝件
10,20．．．承載板
11．．．熱化離型膠層
12,28．．．半導體元件
12a,28a．．．作用面
12b,28b．．．非作用面
120,280．．．電極墊
13,29b,29b’,29b”．．．封裝膠體
14．．．線路結構
2a,2a’．．．封裝基板
21,21’．．．第一介電層
21a．．．第一表面
21b．．．第二表面
210,210’．．．第一開孔
22．．．第一金屬層
23a,23b．．．阻層
230a,230b．．．開口
24．．．線路層
24a．．．線路增層結構
240．．．增層介電層
241．．．增層線路層
25,25’．．．第二介電層
250,250’．．．第二開孔
26．．．第二金屬層
27．．．導電凸塊
27’．．．銲接點
280a．．．導電部
280b．．．銲錫或膠材
29a．．．底膠
30．．．導電元件
第1A至1E圖係為習知晶圓級半導體封裝件之製法之剖面示意圖；以及
第2A至2K圖係為本發明之晶圓級半導體封裝件之製法之剖面示意圖；其中，第2G’圖係為第2G圖之另一實施例，第2K’及2K”圖係為第2K圖之不同實施例；以及
第2A至2H’圖係為本發明之晶圓級封裝基板之製法之剖面示意圖；其中，第2H”圖係為第2H’圖之另一實施例。
2．．．半導體封裝件
21．．．第一介電層
21a．．．第一表面
21b．．．第二表面
210．．．第一開孔
22．．．第一金屬層
24．．．線路層
25．．．第二介電層
250．．．第二開孔
26．．．第二金屬層
27’．．．銲接點
28．．．半導體元件
28a．．．作用面
28b．．．非作用面
29a．．．底膠
29b．．．封裝膠體

Claims (28)

  1. 一種晶圓級封裝基板之製法，係包括：形成第一介電層於一承載板上，且該第一介電層形成有複數第一開孔以外露該承載板之部分表面，其中，該承載板或其表面為導體；形成線路層於該第一介電層之部分表面與該第一開孔上；形成第二介電層於該第一介電層之部分表面與該線路層上，且該第二介電層形成有複數第二開孔以外露該線路層之部分表面；形成導電凸塊於該第二開孔中之線路層上，以電性連接該線路層；以及進行電測。
  2. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，其中，該承載板係為矽晶圓、玻璃板、表面具鋁層之板體或鋁板。
  3. 如申請專利範圍第2項所述之晶圓級封裝基板之製法，其中，該承載板係為表面具鋁層之矽晶圓。
  4. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，其中，形成該第一與第二介電層之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(BenezOcy-clobutene,BCB)、聚對二唑苯(Polybenzoxazole,PBO)、二氧化矽或氮化矽。
  5. 如申請專利範圍第1項所述之晶圓級封裝基板之製 法，其中，形成該線路層之製程係包括：形成一金屬層於該第一介電層之全部表面與該第一開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該線路層於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
  6. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，其中，形成該導電凸塊之製程係包括：形成一金屬層於該第二介電層之全部表面與該第二開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該導電凸塊於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
  7. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，其中，該導電凸塊係含有銲錫材料，並迴銲該導電凸塊。
  8. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，復包括移除該承載板，以露出該線路層。
  9. 如申請專利範圍第8項所述之晶圓級封裝基板之製法，其中，係藉由研磨製程或蝕刻製程，移除該承載板。
  10. 如申請專利範圍第8項所述之晶圓級封裝基板之製 法，復包括於移除該承載板之後，形成導電元件於該露出之線路層上。
  11. 如申請專利範圍第1項所述之晶圓級封裝基板之製法，復包括形成該線路層之後，先形成線路增層結構於該第一介電層之部分表面與該線路層上，再形成該第二介電層於該線路增層結構上，使該線路增層結構電性連接該導電凸塊與該線路層。
  12. 一種晶圓級半導體封裝件之製法，係包括：提供一承載封裝基板之承載板，該封裝基板包含有結合於該承載板上之第一介電層及設於該第一介電層上之第二介電層，該第一介電層上形成有線路層，且該線路層亦結合於該承載板上，而該第二介電層上係形成有導電凸塊，以電性連接該線路層，且該封裝基板已經電測，其中，該承載板或其表面為導體；結合半導體元件於該導電凸塊上，該半導體元件具有結合至該導電凸塊上之作用面與相對該作用面之非作用面；形成封裝膠體於該第二介電層上，以包覆該半導體元件；以及移除該承載板，以露出該線路層。
  13. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，該承載板係為矽晶圓、玻璃板、表面具鋁層之板體或鋁板。
  14. 如申請專利範圍第13項所述之晶圓級半導體封裝件之 製法，其中，該承載板係為表面具鋁層之矽晶圓。
  15. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，形成該第一與第二介電層之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)、聚對二唑苯(Polybenzoxazole,PBO)、二氧化矽或氮化矽。
  16. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，形成該線路層之製程係包括：形成一金屬層於該第一介電層之全部表面與該第一開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該線路層於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
  17. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，形成該導電凸塊之製程係包括：形成一金屬層於該第二介電層之全部表面與該第二開孔上；形成阻層於該金屬層上，且該阻層形成有複數開口以外露該金屬層之部分表面；形成該導電凸塊於該些開口中之金屬層上；以及移除該阻層及其下之金屬層。
  18. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，該導電凸塊係含有銲錫材料，並迴銲該 導電凸塊。
  19. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，該封裝基板復包含有線路增層結構，係形成於該第一介電層與該第二介電層之間，且電性連接該線路層與該導電凸塊。
  20. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，該半導體元件之作用面上具有導電部，以藉由銲錫或膠材電性連接至該導電凸塊上。
  21. 如申請專利範圍第20項所述之晶圓級半導體封裝件之製法，其中，該半導體元件係藉由點膠製程或迴銲製程結合至該導電凸塊上。
  22. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，該半導體元件係為單一晶片或堆疊晶片組結構。
  23. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，復包括研磨該封裝膠體，以薄化其厚度。
  24. 如申請專利範圍第23項所述之晶圓級半導體封裝件之製法，其中，該封裝膠體係外露該半導體元件之非作用面。
  25. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，復包括形成封裝膠體之前，形成底膠於該半導體元件與該第二介電層之間。
  26. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，其中，係藉由研磨製程或蝕刻製程，移除該承 載板。
  27. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，復包括於移除該承載板之後，形成導電元件於該露出之線路層上。
  28. 如申請專利範圍第12項所述之晶圓級半導體封裝件之製法，復包括於移除該承載板之後，進行切單製程。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140078923A (ko) * 2012-12-18 2014-06-26 에스케이하이닉스 주식회사 반도체 장치
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
TWI525769B (zh) * 2013-11-27 2016-03-11 矽品精密工業股份有限公司 封裝基板及其製法
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
US9425178B2 (en) * 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
WO2016007175A1 (en) * 2014-07-11 2016-01-14 Intel Corporation Bendable and stretchable electronic devices and methods
TWI559416B (zh) * 2014-07-17 2016-11-21 Asia Pacific Microsystems Inc The fabrication of wafer - level package structure
CN104465586B (zh) * 2014-12-26 2018-07-10 江苏长电科技股份有限公司 一种圆片级封装结构及其工艺方法
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
CN105575823A (zh) * 2015-12-24 2016-05-11 南通富士通微电子股份有限公司 半导体器件扇出封装结构的制作方法
FR3051971B1 (fr) 2016-05-30 2019-12-13 Soitec Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
US10002848B1 (en) * 2017-06-12 2018-06-19 Powertech Technology Inc. Test method for a redistribution layer
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
JP7382170B2 (ja) * 2019-08-02 2023-11-16 ローム株式会社 半導体装置
TWI739413B (zh) * 2020-05-04 2021-09-11 力成科技股份有限公司 半導體裝置及其製造方法
KR20220034596A (ko) 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지
US11430762B2 (en) * 2020-12-30 2022-08-30 Alpha And Omega Semiconductor International Lp Method for semi-wafer level packaging
US20230086180A1 (en) * 2021-09-20 2023-03-23 Intel Corporation Deformable semiconductor device connection

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452265B1 (en) 2000-01-28 2002-09-17 International Business Machines Corporation Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion
US8089142B2 (en) * 2002-02-13 2012-01-03 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
DE10334576B4 (de) 2003-07-28 2007-04-05 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse
TWI324033B (en) * 2006-08-07 2010-04-21 Unimicron Technology Corp Method for fabricating a flip-chip substrate
US7863189B2 (en) * 2007-01-05 2011-01-04 International Business Machines Corporation Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
TWI355057B (en) * 2007-07-10 2011-12-21 Unimicron Technology Corp Wire bonding type package substrate having heat-co
CN101950729B (zh) * 2007-09-05 2012-09-26 精材科技股份有限公司 电子元件的晶圆级封装及其制造方法
US7838975B2 (en) * 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US8176628B1 (en) * 2008-12-23 2012-05-15 Amkor Technology, Inc. Protruding post substrate package structure and method
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
TWI395292B (zh) * 2009-12-31 2013-05-01 Advanced Semiconductor Eng 半導體封裝結構及其製造方法
US8951839B2 (en) * 2010-03-15 2015-02-10 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
KR101209980B1 (ko) * 2010-12-09 2012-12-07 주식회사 네패스 반도체 패키지 및 그 제조 방법
US9006099B2 (en) * 2011-06-08 2015-04-14 Great Wall Semiconductor Corporation Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump

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